JP3008571B2 - Light receiving device - Google Patents
Light receiving deviceInfo
- Publication number
- JP3008571B2 JP3008571B2 JP3187884A JP18788491A JP3008571B2 JP 3008571 B2 JP3008571 B2 JP 3008571B2 JP 3187884 A JP3187884 A JP 3187884A JP 18788491 A JP18788491 A JP 18788491A JP 3008571 B2 JP3008571 B2 JP 3008571B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- light receiving
- electrode
- receiving element
- concave portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は受光素子及びその製造方
法に関し、特に詳細には、フリップチップボンディング
可能なＰＩＮ型受光素子及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving device and a method of manufacturing the same, and more particularly to a PIN type light receiving device capable of flip chip bonding and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、ギガビットレベルでの光通信を行
うため、高速応答性及び高い光感度を有する受光素子が
求められてきている。そして、高速な応答性を実現する
ためには、入力容量を低減することが求められ、これを
達成するためにプリアンプを形成した基板上に直接ダイ
ボンディングするフリップチップボンディング技術が開
発されてきた。このようなフリップチップボンディング
を可能にした受光素子としてエレクトロニクスレターの
第２４巻、第１６号の１９８８年８月４日号の第９９５
頁に示されるものがある。この文献に開示される受光素
子の構造を図４に示す。そして、この受光素子のＰＩＮ
構造は、ｎ+ −ＩｎＰ基板１上に、ｎ−ＩｎＰのバッフ
ァ層２、ｎ−ＧａＩｎＡｓの光吸収層３、ｎ−ＩｎＰの
キャップ層４より構成され、ｐｎ接合は、キャップ層４
内にＺｎ拡散（図３において点線で囲まれた領域）を行
うことにより形成し、図３に示すように、化学的エッチ
ングによりメサ構造５を作成し、そのメサ構造５のキャ
ップ層４の上部にはＰ型電極６が、また、その周辺の領
域にはＮ型電極７が形成されている。そして、このＰ型
電極とＮ型電極は、図３に点線で示す基板８にフリップ
チップボンディングできるようにように実質的に同一平
面上に位置するように形成されている。2. Description of the Related Art In recent years, in order to perform optical communication at the gigabit level, a light receiving element having high-speed response and high optical sensitivity has been demanded. In order to realize high-speed responsiveness, it is required to reduce the input capacitance, and in order to achieve this, flip-chip bonding technology for directly die bonding on a substrate on which a preamplifier is formed has been developed. As a light receiving element capable of performing such flip-chip bonding, Electronics Letters, Vol. 24, No. 16, August 4, 1988, No. 995
Some are shown on the page. FIG. 4 shows the structure of the light receiving element disclosed in this document. And the PIN of this light receiving element
The structure is composed of a buffer layer 2 of n-InP, a light absorption layer 3 of n-GaInAs, and a cap layer 4 of n-InP on an n + -InP substrate 1.
The mesa structure 5 is formed by chemical etching as shown in FIG. 3, and the upper part of the cap layer 4 of the mesa structure 5 is formed as shown in FIG. , A P-type electrode 6 is formed, and an N-type electrode 7 is formed in a peripheral region thereof. The P-type electrode and the N-type electrode are formed so as to be positioned substantially on the same plane so that flip-chip bonding can be performed on the substrate 8 indicated by a dotted line in FIG.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記文献に開
示される受光素子は、図３に示すように、Ｎ型電極７を
取り出すためにｎ+ 基板を用いている。その為、ｎ+ 基
板による寄生容量が大きく、高速応答性を得ることが難
しかった。However, the light-receiving element disclosed in the above-mentioned document uses an n + substrate for extracting the N-type electrode 7 as shown in FIG. Therefore, the parasitic capacitance due to the n + substrate is large, and it has been difficult to obtain high-speed response.
【０００４】本願発明は上記課題を解決し、寄生容量が
小さく非常に高速な応答性を有するフリップチップダイ
ボンデイング用の受光素子及びそれの製造方法を提供す
ることを目的とする。An object of the present invention is to solve the above problems and to provide a light receiving element for flip chip die bonding having a small parasitic capacitance and a very high speed response, and a method of manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】本発明の受光装置は、一
対の基板側電極が設けられた支持基板と、素子搭載面が
基板側電極と対向するように支持基板に搭載される裏面
入射型の受光素子と、を備えた受光装置において、受光
素子は、半絶縁性半導体基板上に形成され、一端に閉塞
面を有し他端が開口する凹部と、凹部内に設けられ、閉
塞面側に一方の素子電極が位置し、開口側に他方の素子
電極が位置するＰＩＮ型受光部と、閉塞面側の一方の素
子電極から凹部側面に沿って凹部外の半絶縁性半導体基
板上に電極を引出す引出しリードと、開口側の他方の素
子電極上に設けられた引出し電極と、半絶縁性半導体基
板の凹部が形成された面の反対側の面に設けられた反射
防止膜と、を備え、引出しリード及び引出し電極は、実
質的に同一平面上で基板側電極に接続されることを特徴
とする。According to the present invention, there is provided a light-receiving device comprising: a support substrate provided with a pair of substrate-side electrodes; and a back-illuminated type mounted on the support substrate such that an element mounting surface faces the substrate-side electrodes. A light receiving element, which is formed on a semi-insulating semiconductor substrate, has a closed surface at one end and is open at the other end, and is provided in the concave portion; A PIN-type light-receiving portion in which one element electrode is located on the opening side and the other element electrode is located on the opening side, and an electrode is formed on the semi-insulating semiconductor substrate outside the recess along the side surface of the recess from the one element electrode on the closed surface side. And a lead electrode provided on the other element electrode on the opening side, and an antireflection film provided on a surface of the semi-insulating semiconductor substrate opposite to the surface on which the concave portion is formed. , The extraction lead and the extraction electrode are substantially coplanar. Characterized in that it is connected to the substrate electrode.
【０００６】[0006]
【０００７】[0007]
【作用】本発明は、上記のように、半絶縁性基板に設け
た凹部内に設けたＰＩＮ型の受光素子の一方の電極とな
る層から直接、半絶縁性基板に設けた凹部側面に沿って
設けた引出し電極を介してｎ型電極を基板上面に引出し
ている。そのため、基板が電気的に関与せずＮ型電極で
の寄生容量が小さい。According to the present invention, as described above, the present invention is directed to a method in which a layer serving as one electrode of a PIN-type light receiving element provided in a recess provided in a semi-insulating substrate is formed directly along a side surface of the recess provided in the semi-insulating substrate. The n-type electrode is led out to the upper surface of the substrate via the lead electrode provided. Therefore, the substrate is not electrically involved and the parasitic capacitance at the N-type electrode is small.
【０００８】また、半導体基板に設けた凹部内に受光素
子を形成することにより、受光素子の高さを調節でき、
その結果、受光素子の基板側の電極を基板表面に引出
し、受光素子の２つの電極を実質的に同一平面内に形成
することにより、フリップチップボンディング可能な受
光素子の製造が可能になる。Further, by forming the light receiving element in the recess provided in the semiconductor substrate, the height of the light receiving element can be adjusted.
As a result, the electrode on the substrate side of the light receiving element is pulled out to the surface of the substrate, and the two electrodes of the light receiving element are formed substantially in the same plane, thereby making it possible to manufacture a light receiving element capable of flip chip bonding.
【０００９】[0009]
【実施例】以下、図面を参照しつつ本発明に従う一実施
例である受光素子及びその製造方法について説明してい
く。尚、図面中の寸法比率は必ずしも実際の寸法比率と
は一致していない。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a light receiving device according to an embodiment of the present invention; Note that the dimensional ratios in the drawings do not always match the actual dimensional ratios.
【００１０】図１に本発明の受光素子の一実施例の断面
構造を示す。FIG. 1 shows a sectional structure of an embodiment of the light receiving element of the present invention.
【００１１】図１に示すように、半絶縁性ＩｎＰ基板１
０に形成された凹部１０ａ内にＰＩＮ型ホトダイオード
を構成する半導体層が形成されている。そして、このＰ
ＩＮ型ホトダイオードは基板１０側から、Ｎ層となるｎ
ーＩｎＰ層１１と、Ｉ層であって光吸収層となるｉ−Ｇ
ａＩｎＡｓ層１２の半導体多層構造を有しており、その
ｉ−ＧａＩｎＡｓ層１２の上部にはＺｎが拡散された領
域１３が設けられており、ｐｎ接合が形成され、領域１
３がＰ層として機能する。その上に基板１０全体には、
ＳｉＮの絶縁膜１４が形成されており、ｎ−ＩｎＰ層１
１の端部にはＮ型電極を引き出すための電極１５が、ま
たｉ−ＧａＩｎＡｓ層の１２の頂部にはＰ型電極１６が
設けられており、このＰ型電極１６上には、引出し電極
１８が設けられている。更に、電極１５上には、Ｎ型電
極を基板１０上面に引き出すための引出しリード１７が
設けられている。このリード７は、凹部の側面に沿って
伸び基板１０の上面に設けた引出し電極１８に接続され
ている。そして、この引出し電極１８と引出し電極１９
の上面は、フリップチップボンディング可能とするた
め、実質的に同一平面上に位置している。そして半導体
層、電極等の厚さ及び凹部の深さは、引出し電極１８と
引出し電極１９との上面が実質的に同一平面となるよう
選択されている。一方、基板１０の裏面側には反射防止
膜２０が設けられている。As shown in FIG. 1, a semi-insulating InP substrate 1
The semiconductor layer constituting the PIN photodiode is formed in the recess 10a formed at 0. And this P
The IN-type photodiode is formed by n
-An InP layer 11 and an i-G layer, which is an I layer and serves as a light absorbing layer.
It has a semiconductor multilayer structure of an aInAs layer 12, a region 13 in which Zn is diffused is provided above the i-GaInAs layer 12, a pn junction is formed, and a region 1 is formed.
3 functions as a P layer. On top of that, the entire substrate 10
An insulating film 14 of SiN is formed, and the n-InP layer 1 is formed.
An electrode 15 for extracting an N-type electrode is provided at one end of the first electrode, and a P-type electrode 16 is provided on the top of the i-GaInAs layer 12. An extraction electrode 18 is provided on the P-type electrode 16. Is provided. Further, on the electrode 15, a lead 17 for leading the N-type electrode to the upper surface of the substrate 10 is provided. The lead 7 extends along the side surface of the concave portion and is connected to an extraction electrode 18 provided on the upper surface of the substrate 10. The extraction electrode 18 and the extraction electrode 19
Are located on substantially the same plane to enable flip chip bonding. The thickness of the semiconductor layer, the electrodes and the like and the depth of the concave portion are selected so that the upper surfaces of the extraction electrode 18 and the extraction electrode 19 are substantially coplanar. On the other hand, an antireflection film 20 is provided on the back surface side of the substrate 10.
【００１２】このように構成したことによりＰＩＮ型ホ
トダイオードのＮ型電極での寄生容量を従来のｎ+ Ｉｎ
Ｐ基板を用いたものに比較して小さくすることができ
る。また、基板内に設けた凹部内にＰＩＮ型の受光素子
を設けているため、その受光素子の光吸収層の厚くする
ことができる。これにより、光感度の高い受光素子が実
現できる。With this configuration, the parasitic capacitance at the N-type electrode of the PIN photodiode can be reduced by the conventional n + In
The size can be made smaller than that using the P substrate. Further, since the PIN type light receiving element is provided in the concave portion provided in the substrate, the thickness of the light absorbing layer of the light receiving element can be increased. Thereby, a light receiving element with high light sensitivity can be realized.
【００１３】また、この受光素子を使用する場合には、
支持基板にフリップチップボンディングして使用する
が、この支持基板８側には、この引出し電極１８と引出
し電極１９が接続される一対の電極１８ａ、１９ａが設
けられ、これらとフリップチップボンディングにより互
いに接続できるようになっている。そして、上記実施例
の受光素子は、矢印で示す方向からの光を受光するよう
に用いられる。When this light receiving element is used,
A pair of electrodes 18a, 19a to which the extraction electrode 18 and the extraction electrode 19 are connected is provided on the support substrate 8 side by flip-chip bonding, and is connected to the support substrate 8 by flip-chip bonding. I can do it. The light receiving element of the above embodiment is used to receive light from the direction indicated by the arrow.
【００１４】以下、上記実施例の受光素子の製造方法に
ついて、図２及び図３を用いて説明する。Hereinafter, a method for manufacturing the light receiving element of the above embodiment will be described with reference to FIGS.
【００１５】まず、半絶縁性ＩｎＰ基板１０を準備し
（図２（ａ）参照）、この基板１０に所定の深さ、例え
ば２〜３μｍの深さの凹部１０ａを形成する。この凹部
の深さは、その凹部に形成するＰＩＮホトダイオードの
全体の厚さによって選択される。この凹部１０ａの形成
はウエットエッチング又はドライエッチングにより行
い、その側面１０ｂが出来るだけ傾斜するようにしてお
くことが好ましい。この状態を図１（ｂ）に示す。First, a semi-insulating InP substrate 10 is prepared (see FIG. 2A), and a concave portion 10a having a predetermined depth, for example, a depth of 2 to 3 μm is formed in the substrate 10. The depth of the recess is selected according to the overall thickness of the PIN photodiode formed in the recess. The recess 10a is preferably formed by wet etching or dry etching, and the side surface 10b is preferably inclined as much as possible. This state is shown in FIG.
【００１６】次に、ＰＩＮホトダイオードを構成する半
導体層となるｎ−ＩｎＰ層２１、ｉ−ＧａＩｎＡｓ層２
２をＯＭＶＰＥ法の結晶成長法により、凹部１０ａを形
成した基板１０上に順次成長させる。この状態を図１
（ｃ）に示す。Next, an n-InP layer 21 and an i-GaInAs layer 2 serving as semiconductor layers constituting a PIN photodiode
2 are sequentially grown on the substrate 10 on which the concave portions 10a are formed by the crystal growth method of the OMVPE method. This state is shown in FIG.
It is shown in (c).
【００１７】次に、ＳｉＮ膜を形成し、この膜をマスク
としてＺｎ拡散を行い、図１（ｃ）に示すようにＰＩＮ
ホトダイオードのｐ型層となるｐ−ＧａＩｎＡｓ領域２
３を形成する。Next, a SiN film is formed, Zn is diffused using this film as a mask, and as shown in FIG.
P-GaInAs region 2 serving as a p-type layer of a photodiode
Form 3
【００１８】その後、凹部１０ａ内及び基板上面の半導
体層の不要部分を除去し、図３（ｅ）に示すような構造
にする。これにより、図３（ｅ）に示すように、Ｐ層の
頂部とＮ層の一部が露出される。Thereafter, unnecessary portions of the semiconductor layer in the recess 10a and on the upper surface of the substrate are removed to obtain a structure as shown in FIG. Thereby, as shown in FIG. 3E, the top of the P layer and a part of the N layer are exposed.
【００１９】次に、ＳｉＮ膜２４を形成し、Ｎ型電極２
５とＰ型電極２６を形成する。この状態を図３（ｆ）に
示す。Next, an SiN film 24 is formed, and the N-type electrode 2 is formed.
5 and a P-type electrode 26 are formed. This state is shown in FIG.
【００２０】そして、金属膜を基板１０全面に形成し、
パターンニングして、図３（ｇ）に示すように、Ｎ型電
極２５から基板１０の上面に伸びる引出しリード２７
と、Ｐ型電極２６上には電極２８を形成する。上記製造
方法での各層の厚さは、基板上面の引出しリード２７の
上面が電極２８の上面と実質的に同一平面に位置するよ
うに選択する。また、この受光素子では、光は基板裏面
側から入射する。そこで光結合効率をあげるため、ＰＩ
Ｎホトダイオード形成後、基板を薄くし、反射防止膜２
９を形成する。この状態を図３（ｇ）に示す。Then, a metal film is formed on the entire surface of the substrate 10,
After patterning, as shown in FIG. 3G, a lead 27 extending from the N-type electrode 25 to the upper surface of the substrate 10 is formed.
Then, an electrode 28 is formed on the P-type electrode 26. The thickness of each layer in the above manufacturing method is selected so that the upper surface of the lead 27 on the upper surface of the substrate is located substantially on the same plane as the upper surface of the electrode 28. In this light receiving element, light enters from the back surface of the substrate. Therefore, to increase the optical coupling efficiency, PI
After forming the N photodiode, the substrate is thinned and the anti-reflection film 2 is formed.
9 is formed. This state is shown in FIG.
【００２１】本発明は上記実施例に限定されず、種々の
変形例が考えられ得る。The present invention is not limited to the above embodiment, and various modifications can be considered.
【００２２】具体的には、上記実施例では、ｎ型電極と
引出し電極を別々に形成しているが、同時に形成しても
よい。またＰＩＮホトダイオードのｐ型層の形成をＺｎ
拡散で行っているが、この代わりにｐ−ＧａＩｎＡｓ層
を成長させるようにしてもよSpecifically, in the above embodiment, the n-type electrode and the extraction electrode are formed separately, but they may be formed simultaneously. In addition, the formation of the p-type layer of the PIN
Although the diffusion is performed, a p-GaInAs layer may be grown instead.
【００２３】い。No.
【発明の効果】本発明の受光素子及びその製造方法で
は、半絶縁性ＩｎＰ基板を用い、ＰＩＮホトダイオード
のＮ型電極を直接引き出しているため、Ｎ型電極での寄
生容量が少ない。これにより、高速応答性を有する受光
素子を実現できる。According to the light receiving element and the method of manufacturing the same of the present invention, since the N-type electrode of the PIN photodiode is directly drawn using the semi-insulating InP substrate, the parasitic capacitance at the N-type electrode is small. Thereby, a light receiving element having high-speed response can be realized.
【図１】本発明に従う受光素子の一実施例の断面構造を
示す図である。FIG. 1 is a diagram showing a sectional structure of one embodiment of a light receiving element according to the present invention.
【図２】本発明に従う受光素子の製造方法の一実施例の
前半各工程での受光素子の断面構造を示す図である。FIG. 2 is a diagram showing a cross-sectional structure of the light receiving element in each of the first half steps of one embodiment of the method for manufacturing the light receiving element according to the present invention.
【図３】本発明に従う受光素子の製造方法の一実施例の
後半各工程での受光素子の断面構造を示す図である。FIG. 3 is a view showing a cross-sectional structure of the light receiving element in each step of the latter half of the embodiment of the method for manufacturing the light receiving element according to the present invention.
【図４】従来のフリップチップボンデイング用の受光素
子の断面構造を示す図である。FIG. 4 is a diagram showing a cross-sectional structure of a conventional light receiving element for flip chip bonding.
１…ｎ+ ＩｎＰ基板 １０…半絶縁性ＩｎＰ基板 １０ａ…凹部 １１…ＩｎＰ層 １２…ｉ−ＧａＩｎＡｓ層 １７…引出しリード ２６…Ｐ型電極 ２５…Ｎ型電極DESCRIPTION OF SYMBOLS 1 ... n + InP substrate 10 ... Semi-insulating InP substrate 10a ... Concave part 11 ... InP layer 12 ... i-GaInAs layer 17 ... Lead-out lead 26 ... P-type electrode 25 ... N-type electrode
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 31/02 - 31/024 H01L 31/10 - 31/119 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 31/02-31/024 H01L 31/10-31/119
Claims (1)
と、素子搭載面が前記基板側電極と対向するように前記
支持基板に搭載される裏面入射型の受光素子と、を備え
た受光装置において、 前記受光素子は、半絶縁性半導体基板上に形成され、一
端に閉塞面を有し他端が開口する凹部と、 前記凹部内に設けられ、前記閉塞面側に一方の素子電極
が位置し、前記開口側に他方の素子電極が位置するＰＩ
Ｎ型受光部と、 前記閉塞面側の一方の素子電極から前記凹部側面に沿っ
て前記凹部外の前記半絶縁性半導体基板上に電極を引出
す引出しリードと、 前記開口側の他方の素子電極上に設けられた引出し電極
と、 前記半絶縁性半導体基板の凹部が形成された面の反対側
の面に設けられた反射防止膜と、を備え、 前記引出しリード及び前記引出し電極は、実質的に同一
平面上で前記基板側電極に接続されることを特徴とする
受光装置。1. A light receiving device comprising: a support substrate provided with a pair of substrate-side electrodes; and a back-illuminated light-receiving element mounted on the support substrate such that an element mounting surface faces the substrate-side electrodes. In the device, the light receiving element is formed on a semi-insulating semiconductor substrate, and has a concave portion having a closed surface at one end and an open end at the other end. The concave portion is provided in the concave portion, and one element electrode is provided on the closed surface side. PI where the other element electrode is located on the opening side
An N-type light receiving portion; a lead lead for leading an electrode from the one element electrode on the closed surface side along the side surface of the concave portion to the semi-insulating semiconductor substrate outside the concave portion; And an antireflection film provided on a surface opposite to the surface of the semi-insulating semiconductor substrate on which the concave portion is formed, wherein the extraction lead and the extraction electrode are substantially A light receiving device connected to the substrate-side electrode on the same plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3187884A JP3008571B2 (en) | 1991-07-26 | 1991-07-26 | Light receiving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3187884A JP3008571B2 (en) | 1991-07-26 | 1991-07-26 | Light receiving device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0537005A JPH0537005A (en) | 1993-02-12 |
| JP3008571B2 true JP3008571B2 (en) | 2000-02-14 |
Family
ID=16213888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3187884A Expired - Lifetime JP3008571B2 (en) | 1991-07-26 | 1991-07-26 | Light receiving device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3008571B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09213831A (en) * | 1996-01-30 | 1997-08-15 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JP2003249675A (en) | 2002-02-26 | 2003-09-05 | Sumitomo Electric Ind Ltd | Light receiving element array |
| JP4279650B2 (en) * | 2003-10-24 | 2009-06-17 | 浜松ホトニクス株式会社 | Semiconductor photo detector |
| JP2005129776A (en) * | 2003-10-24 | 2005-05-19 | Hamamatsu Photonics Kk | Semiconductor light receiving element |
| JP6398409B2 (en) * | 2014-07-16 | 2018-10-03 | 三菱電機株式会社 | Light receiving element |
-
1991
- 1991-07-26 JP JP3187884A patent/JP3008571B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0537005A (en) | 1993-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4847210A (en) | Integrated pin photo-detector method | |
| US6399967B1 (en) | Device for selectively detecting light by wavelengths | |
| KR920009898B1 (en) | Photo-electric integrated circuit devices and its manufacturing method for receiver | |
| JP3008571B2 (en) | Light receiving device | |
| JPH05129638A (en) | Optical semiconductor device | |
| CN111785791A (en) | Ge photoelectric detector and preparation method thereof | |
| JPH0582829A (en) | Semiconductor light receiving element | |
| US20040126922A1 (en) | Photo diode, opto-electronic integrated circuit device comprising the same, and method for manufacturing the same | |
| JP2000223685A (en) | Photoelectric integrated circuit and heterojunction phototransistor | |
| JP3674255B2 (en) | Manufacturing method of light receiving element | |
| US6589848B1 (en) | Photodetector device and method for manufacturing the same | |
| JPH04263475A (en) | Semiconductor photodetector and manufacture thereof | |
| JP3139454B2 (en) | Photodetector with built-in circuit | |
| JPH01196182A (en) | Photodiode | |
| JPH06177414A (en) | Semiconductor element | |
| JP2847561B2 (en) | Semiconductor light receiving element | |
| JPH1117211A (en) | Semiconductor planar photodiode and device therewith | |
| JPH05145051A (en) | Optical semiconductor device | |
| JPH10200134A (en) | Semiconductor photo-sensitive element | |
| KR100440253B1 (en) | Photoreceiver and method of manufacturing the same | |
| JP2649862B2 (en) | Manufacturing method of photodetector with built-in circuit | |
| JPH02226777A (en) | Semiconductor light receiving element and manufacture thereof | |
| JPS62269368A (en) | Semiconductor photodetector device | |
| JP2023097802A (en) | Light receiving element and method of manufacturing light receiving element | |
| JPS61258471A (en) | Semiconductor integrated circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071203 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081203 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091203 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101203 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101203 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111203 Year of fee payment: 12 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111203 Year of fee payment: 12 |