JP2000223685A - Photoelectric integrated circuit and heterojunction phototransistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric integrated circuit and a heterojunction phototransistor in which trade-off between light receiving sensitivity and operating speed can be eliminated. SOLUTION: A photoelectric integrated circuit comprises a heterojunction bipolar transistor having first through fourth collector layers 102-105, a base layer 106 and an emitter layer 107 laminated on a substrate 101 and provided with a collector electrode 109, a base electrode 110 and an emitter electrode 111, and a photodiode(PD) having collector layers 102-105, a base layer 106 and first through fifth common semiconductor layers 102a-106a formed on the substrate 101 and provided with an n side electrode 109a and a p side electrode 110a formed simultaneously with the electrodes 109, 110. The photoelectric integrated circuit outputs a signal light 1 incident to the PD while converting into an electric signal and an inverted mesa 112 inclining inward in the thickness direction of the substrate 101 is provided the PD side end face of the substrate 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an optoelectronic integrated circuit and a heterojunction phototransistor used for receiving an optical signal in optical communication.

[0002]

2. Description of the Related Art As a device for realizing a high-speed and large-capacity optical communication system at low cost, an opto-electrical integrated circuit (hereinafter referred to as an optical-electrical integrated circuit) having a function of converting an ultra-high-speed optical signal into an electric signal with one chip and amplifying the electric signal. Hereinafter, it is referred to as “OEIC”.)
Also, a heterojunction phototransistor (hereinafter, referred to as “HPT”) having one element and having the above function has been developed. H
Since PT has an amplifying function, it can be regarded as having a part of a function as an opto-electric integrated circuit, and can be regarded as one of light receiving devices when integrated with an electronic device to form an OEIC. it can. As a receiving OEIC, the function of an OEIC that converts an ultra-high-speed optical signal into an electric signal and performs digital processing on the electric signal has been confirmed.

A receiving OEIC is configured by integrating a light receiving device and an electronic device on the same substrate. As a light receiving device, a photodiode (hereinafter, referred to as “PD”) or a heterojunction bipolar transistor (hereinafter, “H”) is used.
BT ”. ) Or an element having a metal-semiconductor-metal structure, and the like.
A BT, a heterojunction field effect transistor, or the like is employed. Above all, OEI integrating PD and HBT
C (hereinafter referred to as “PD-HBT OEIC”) and an OEIC (hereinafter, “HPT
-HBT OEIC ". ) Can share the semiconductor layer structure and the manufacturing process that constitute the light receiving device and the electronic device, and can greatly simplify the crystal growth and process for manufacturing the OEIC (for example, see No. 6-326120).

[0004] Such a conventional OEIC or HPT will be described below with reference to FIGS.

[PD-HBT OEIC] As shown in FIG. 3, on a semi-insulating InP substrate 301, a first collector layer 302, which is a sub-collector layer of InGaAs doped with an n-type impurity at a high concentration, and First semiconductor layer 302
a is laminated. On the first collector layer 302, an undoped or n-type impurity lightly doped InP
And a collector electrode 309 is provided. On the first semiconductor layer 302a, a second semiconductor layer 303a of InP doped with undoped or n-type impurities at a low concentration is laminated,
An n-side electrode 309a is provided.

On the second collector layer 303, undoped InGaAsP and n-type impurity doped InG
A third collector layer 304 composed of two layers of aAsP is laminated. On the second semiconductor layer 303a, undoped InGaAsP and n-type impurity-doped InGaAs
A third semiconductor layer 304a made of two layers of sP is stacked. On the third collector layer 304, an undoped I
A fourth collector layer 305 of nGaAs is stacked.
Undoped InGaAs is formed on the third semiconductor layer 304a.
s fourth semiconductor layer 305a is stacked.

Here, the third collector layer 304 is formed of a second collector layer 303 and a fourth collector layer 305 in order to reduce a carrier blocking effect due to conduction band discontinuity between the second collector layer 303 and the fourth collector layer 305. And the third semiconductor layer 304a is
To reduce a carrier blocking effect due to conduction band discontinuity between the second semiconductor layer 30 and the fourth semiconductor layer 305a.
3a and the fourth semiconductor layer 305a. In this example, the collector layer is constituted by the second to fourth collector layers 303 to 305 and the like.

On the fourth collector layer 305, an InGaAs base layer 30 heavily doped with p-type impurities is formed.
6 are stacked. On the fourth semiconductor layer 305a, p
A fifth semiconductor layer 306a of InGaAs doped with a high-type impurity at a high concentration is laminated. On the base layer 306, an InP emitter layer 307 doped with an n-type impurity
And a base electrode 310 is provided. A p-side electrode 310a is provided on the fifth semiconductor layer 306a. On the emitter layer 307, an InGaAs emitter cap layer 308 doped with an n-type impurity at a high concentration is laminated. Emitter cap layer 308
An emitter electrode 311 is stacked on top. Also,
The p-side electrode 310a on the PD side has an entrance window 31 for the signal light 1
2 are formed.

That is, the first to fourth collector layers 30 of the HBT
2 to 305 and the electrodes 309 and 310 and the first to fourth semiconductor layers 302a to 305a of the PD and the electrode 309
a, 310a have the same layer structure and manufacturing process. In other words, PD is the first to fourth semiconductor layers 302 common to the first to fourth collector layers 302 to 305 of the HBT.
a to 305a and the electrode 30 of the HBT.
The electrodes 309a, 31 formed simultaneously with the electrodes 9, 310
0a.

[0010] In such a PD-HBT OEIC,
When the signal light 1 enters from the entrance window 312, the incident light 1
Proceeds in the stacking direction, the fifth semiconductor layer 306a and the fourth semiconductor layer 305a absorb the signal light 1, the PD side acts as a light receiving device, and the HBT side acts as an electronic device.

[HPT] As shown in FIG. 4, a first collector layer 402, which is a sub-collector layer of InGaAs doped with a high concentration of n-type impurities, is laminated on a semi-insulating InP substrate 401. I have. On the first collector layer 402, a second collector layer 403 of InP doped with undoped or n-type impurities at a low concentration is laminated,
A collector electrode 409 is provided. On the second collector layer 403, a third collector layer 404 composed of two layers of undoped InGaAsP and InGaAsP doped with an n-type impurity is stacked. Third collector layer 40
On, a fourth collector layer 405 of undoped InGaAs is stacked.

Here, the third collector layer 404 and the fourth collector layer 405 are used to reduce a carrier blocking effect due to a conduction band discontinuity between the second collector layer 403 and the fourth collector layer 405. And intervenes between them. In this example, the second to fourth collector layers 40
The collector layer is constituted by 3 to 405 or the like.

On the fourth collector layer 405, an InGaAs base layer 40 heavily doped with p-type impurities is formed.
6 are stacked. On the base layer 406, an InP emitter layer 407 doped with an n-type impurity is stacked, and a base electrode 410 is provided. On the emitter layer 407, an n-type impurity highly doped In
An emitter cap layer 408 of GaAs is laminated. On the emitter cap layer 408, the emitter electrode 4
11 are provided. An entrance window 412 for the signal light 1 is formed in the emitter electrode 411.

In such an HPT, when the signal light 1 enters from the incident window 412, the incident light 1 passes in the stacking direction, and the base layer 406 and the fourth collector layer 405 absorb the signal light 1, and Acts as a light receiving device.

[HPT-HBT OEIC] HPT-H
BT OEIC is the PD-HBT OEI shown in FIG.
The PD part of C has a structure in which the HPT is changed to the HPT shown in FIG. 4, and operates in the same manner as described above.

[0016]

The conventional HPT, PD-HBT OEIC, HPT-HBT O
In EIC, since the optimal layer structure as a light receiving device and the optimal layer structure as an electronic device are different, there is a trade-off between light receiving sensitivity and operation speed,
High performance was hindered. In particular, in a digital directly-coupled OEIC in which an output signal of a PD is directly input to a digital IC to process a digital signal, a sufficient output is required to drive the digital IC as an electric signal output from the PD. If the sensitivity of the light receiving device is conventional, the sensitivity is too low, and it is extremely difficult to obtain a practical level of sensitivity and operation speed as an OEIC.

More specifically, the first problem is that the signal light 1 is absorbed by the absorption layer (the fourth and fifth semiconductor layers 305a and 306a in PD-HBTOEIC, the base layer 406 and the fourth collector layer 405 in HPT). The sensitivity is low due to the short distance through which the light passes. Here, it is conceivable to increase the sensitivity by increasing the thickness of the absorbing layer. However, in order to increase the operating speed of an electronic device such as an HBT, it is necessary to operate at a high current density. However, under such operating conditions, the influence of space charge is likely to appear, and moreover, The effect becomes more remarkable as the collector depletion layer is made thicker. Therefore, if the absorption layer is made thicker so that the light receiving device side such as a PD becomes highly sensitive, the operating speed of an electronic device side such as an HBT is greatly reduced. Resulting in.

The second problem is that the electrodes 310a, 41
Since the entrance windows 312 and 412 for the incident light 1 are formed in the first electrode 1, the parasitic resistance on the electrodes 310a and 411 is large. In order to increase the operation speed on the side of an electronic device such as an HBT, it is desirable to make the fifth semiconductor layer 306 and the base layer 406 thin, and a realistic sheet resistance obtained by doping a p-type impurity at a high concentration. Is about several hundred ohms per unit area, and the resistance increase caused by forming the entrance windows 312, 412 in the electrodes 310a, 411 is extremely large.

The third problem is that the fifth semiconductor layer 306 and the base layer 406 are uniformly doped with p-type impurities at a high concentration in the laminating direction. Electrons are applied to the first semiconductor layer 302a.
This means that pulling out to the side or the first collector layer 402 side is delayed, and a tail appears in the time response waveform of the electric signal.

In view of the above problems, an object of the present invention is to provide a photoelectric integrated circuit and a heterojunction phototransistor which can eliminate a trade-off between light receiving sensitivity and operation speed. .

[0021]

According to a first aspect of the present invention, there is provided an opto-electric integrated circuit in which a subcollector layer, a collector layer, a base layer, and an emitter layer are stacked on a substrate. A heterojunction bipolar transistor having a collector electrode, a base electrode, and an emitter electrode, and having, on the substrate, the subcollector layer of the heterojunction bipolar transistor, each semiconductor layer common to the collector layer and the base layer, A photodiode having each electrode formed simultaneously with the collector electrode and the base electrode of the hetero-junction bipolar transistor, wherein the photoelectric conversion circuit converts signal light incident on the photodiode into an electric signal and outputs the signal. An incident window through which a signal light is incident; Is provided on the side end surface of the side so as to be inclined so as to be depressed toward the inner side in the thickness direction of the substrate, thereby refracting the signal light incident from the incident window, in the laminating direction in the semiconductor layer of the photodiode. It is characterized in that it is made to pass obliquely with respect to it.

A photoelectric integrated circuit according to a second aspect of the present invention comprises:
In the optoelectronic integrated circuit of the first invention, the electrode of the photodiode formed simultaneously with the base electrode of the hetero-junction bipolar transistor is non-alloy ohmic.

A photoelectric integrated circuit according to a third aspect of the present invention comprises:
In the optoelectronic integrated circuit according to the first and second aspects of the present invention, the impurity concentration or the bandgap energy of the semiconductor layer of the photodiode common to the base layer of the heterojunction bipolar transistor is the collector of the heterojunction bipolar transistor. It is characterized in that the photodiode is reduced stepwise or continuously toward the semiconductor layer side of the photodiode common to the layer.

A photoelectric integrated circuit according to a fourth aspect of the present invention comprises:
In the optoelectronic integrated circuit according to the first to third aspects, the bandgap energy of the semiconductor layer of the photodiode which is common to the subcollector layer of the heterojunction bipolar transistor is larger than the energy corresponding to the wavelength of the signal light. It is characterized by the following.

According to a fifth aspect of the present invention, there is provided an opto-electric integrated circuit comprising:
A hetero-junction bipolar transistor having a collector electrode, a base electrode, and an emitter electrode laminated on a sub-collector layer, a collector layer, a base layer, and an emitter layer on a substrate; and the sub-collector layer of the hetero junction bipolar transistor on the substrate. A subcollector layer common to the collector layer, the base layer and the emitter layer, a collector layer, a base layer and an emitter layer,
A heterojunction phototransistor having a collector electrode, a base electrode, and an emitter electrode formed simultaneously with the collector electrode, the base electrode, and the emitter electrode of the heterojunction bipolar transistor, and a signal light incident on the heterojunction phototransistor. In an opto-electric integrated circuit that converts and outputs an electric signal, an incident window into which a signal light is incident is formed in a side end surface of the substrate on the side of the heterojunction phototransistor having an inclined shape depressed toward the inside in the thickness direction of the substrate. With this arrangement, the signal light incident from the incident window is refracted and passed obliquely with respect to the stacking direction in the layer of the heterojunction phototransistor.

A photoelectric integrated circuit according to a sixth aspect of the present invention
According to a fifth aspect of the present invention, the emitter electrode of the heterojunction phototransistor is non-alloy ohmic.

The photoelectric integrated circuit according to the seventh aspect of the present invention
In the optoelectronic integrated circuit according to the fifth and sixth aspects, the impurity concentration or band gap energy of the base layer of the heterojunction phototransistor decreases stepwise or continuously toward the collector layer of the heterojunction phototransistor. It is characterized by having.

According to an eighth aspect of the present invention, there is provided a photoelectric integrated circuit comprising:
In the fifth to seventh inventions, the bandgap energy of the subcollector layer of the heterojunction phototransistor is larger than the energy corresponding to the wavelength of the signal light.

According to a ninth aspect of the present invention, there is provided a heterojunction phototransistor for solving the above-mentioned problems, in which a subcollector layer, a collector layer, a base layer, and an emitter layer are laminated on a substrate to form a collector electrode, a base electrode, and a base electrode. In a heterojunction phototransistor comprising a heterojunction bipolar transistor having an electrode and an emitter electrode, and taking out the signal light incident on the heterojunction bipolar transistor as an electric signal, an incident window through which the signal light is incident is provided at a side end surface of the substrate on the side end surface of the substrate. By being provided so as to have an inclined shape depressed toward the inner side in the thickness direction, the signal light incident from the incident window is refracted and passed obliquely in the layer of the hetero-junction bipolar transistor with respect to the laminating direction. It is characterized by doing so.

According to a tenth aspect of the present invention, there is provided a heterojunction phototransistor according to the ninth aspect, wherein the emitter electrode is non-alloy ohmic.

According to a tenth aspect of the present invention, there is provided the heterojunction phototransistor according to the ninth and tenth aspects, wherein the impurity concentration or band gap energy of the base layer is stepwise or continuous toward the collector layer. It is characterized by a dramatic decrease.

A twelfth aspect of the present invention is the heterojunction phototransistor according to the ninth to tenth aspects, wherein the bandgap energy of the subcollector layer is higher than the energy corresponding to the wavelength of the signal light. It is characterized by being large.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an opto-electric integrated circuit (hereinafter referred to as "OEIC") and a heterojunction phototransistor (hereinafter referred to as "HPT") according to the present invention will be described below. The present invention is not limited to the following embodiment.

[PD-HBT OEIC] An embodiment in which the OEIC according to the present invention is applied to a PD-HBT OEIC will be described with reference to FIG. FIG. 1 is a schematic configuration diagram.

As shown in FIG. 1, a semi-insulating InP substrate 101 is provided with a high concentration of n-type impurity-doped InP.
A first collector layer 102 and a first semiconductor layer 102a, which are P subcollector layers, are stacked. On the first collector layer 102, a second collector layer 103 of InP doped with an undoped or n-type impurity at a low concentration is stacked, and a collector electrode 109 is stacked. On the first semiconductor layer 102a, a second semiconductor layer 103a of InP doped with undoped or n-type impurities at a low concentration is laminated, and an n-side electrode 109a is provided.

On the second collector layer 103, undoped InGaAsP and n-type impurity doped InG
A third collector layer 104 composed of two layers of aAsP is laminated. On the second semiconductor layer 103a, undoped InGaAsP and n-type impurity-doped InGaAs
A third semiconductor layer 104a composed of two layers of sP and sP is stacked. On the third collector layer 104, an undoped I
A fourth collector layer 105 of nGaAs is stacked.
Undoped InGaAs is formed on the third semiconductor layer 104a.
s fourth semiconductor layer 105a is stacked.

Here, the third collector layer 104 is formed of a second collector layer 103 and a fourth collector layer 105 in order to reduce a carrier blocking effect due to a conduction band discontinuity between the second collector layer 103 and the fourth collector layer 105. And the third semiconductor layer 104a is
To reduce a carrier blocking effect due to conduction band discontinuity between the second semiconductor layer 105a and the fourth semiconductor layer 105a.
3a and the fourth semiconductor layer 105a. In this example, a collector layer is constituted by the second to fourth collector layers 103 to 105 and the like.

On the fourth collector layer 105, the substrate 1
The base layer 106 of InGaAs doped with the p-type impurity at a higher concentration toward the 01 side is stacked. On the fourth semiconductor layer 105a, a fifth semiconductor layer 106a of InGaAs doped with a higher concentration of p-type impurities toward the substrate 101 is laminated. On the base layer 106, an InP emitter layer 107 doped with an n-type impurity
Are laminated, and a base electrode 110 is provided. The p-side electrode 110a is stacked on the fifth semiconductor layer 106a. On the emitter layer 107, an InGaAs emitter cap layer 108 doped with an n-type impurity at a high concentration is laminated. Emitter cap layer 108
On the upper side, an emitter electrode 111 is provided.

The electrodes 109 to 113 are all made of Pt / Ti / Pt / Au, so that a non-alloy ohmic contact can be obtained.

That is, the first to fourth collector layers 10 of the HBT
2 to 105 and the electrodes 109 and 110 and the first to fourth semiconductor layers 102a to 105a of the PD and the electrodes 109
a, 110a have a common layer structure and a common manufacturing process. In other words, the PD is a first to fourth semiconductor layer 102 common to the first to fourth collector layers 102 to 105 of the HBT.
a to 105a and the electrode 10 of the HBT.
The electrodes 109a, 11 formed simultaneously with the electrodes 9, 110
0a.

On the side surface of the substrate 101 on the PD side, there is formed a so-called inverted mesa 112 which is an entrance window which is inclined inward so as to be depressed toward the inside of the substrate 101. The reverse mesa 112 can be easily formed by using a wet etching solution having crystal plane selectivity such as bromomethanol.

In such a PD, the fourth and fifth semiconductor layers 105a and 106a function as absorption layers for the signal light 1 in the 1.55 μm band. Here, when the HBT operates at a high current density, a steep electric field is generated in the first semiconductor layer 102.
However, the second semiconductor layer 103 is the first semiconductor layer 1
Since it is on the 02 side, the operation can be stabilized even when a high electric field is applied, that is, the breakdown voltage can be increased.

In such a PD-HBT OEIC,
When the signal light 1 in the 1.55 μm band is incident from the reverse mesa 112 side in a direction along the surface of the substrate 101, the signal light 1 is bent at the incident end face of the reverse mesa 112, and After passing through the layers 102a to 104a obliquely with respect to the stacking direction, the fourth and fifth semiconductor layers 105a and 106a
Is absorbed by. The signal light 1 that has not been absorbed by the layers 105a and 106a and has passed through the layers 105a and 106a is reflected by the p-side electrode 110a and is reflected by the layer 1a.
It is absorbed again at 05a and 106a.

That is, by making the signal light 1 incident from the reverse mesa 112, the signal light 1 is refracted at the time of incidence and passed obliquely with respect to the stacking direction to increase the passing distance and to reduce n-type impurities. By applying the first semiconductor layer 102a of InP which is doped at a high concentration, the bandgap energy is made larger than the energy corresponding to the wavelength of the signal light 1, and the absorption of the incident light 1 in the first semiconductor layer 102a is suppressed. Then, the amount of incident light 1 absorbed by the fourth and fifth semiconductor layers 105a and 106a is increased, and the p-side electrode 110a
Is made non-alloy, the flatness of the electrode interface is enhanced, and the signal light 1 that has not been completely absorbed by the fourth and fifth semiconductor layers 105a and 106a is reflected by the p-side electrode 110a to form the fourth and fifth semiconductor layers 105a and 106a.
The five semiconductor layers 105a and 106a are again passed obliquely.

For this reason, the fourth and fifth semiconductor layers 105a, 1
06a, the distance of the signal light 1 increases, so that the fourth and fifth semiconductor layers 105a and 106a need not be thickened.
The sensitivity of the PD can be increased.

Further, since the signal light 1 is incident from the reverse mesa 112, it is not necessary to form an entrance window in the p-side electrode 110a, and the fifth semiconductor layer 106a is formed by the p-side electrode 110a.
Can be entirely covered, so that the resistance can be greatly reduced.

Further, by increasing the concentration of the p-type impurity doped in the fifth semiconductor layer 106a toward the substrate 101, electrons photoexcited in this region can be accelerated toward the collector layer by an internal electric field. No tailing appears in the time response waveform of the electric signal.

Therefore, such PD-HBT O
According to the EIC, a trade-off between the light receiving sensitivity and the operation speed can be eliminated.

[HPT] An embodiment of the HPT according to the present invention will be described with reference to FIG. FIG. 2 is a schematic configuration diagram thereof. However, for members similar to those in the above-described embodiment, the same reference numerals as those used in the description of the above-described embodiment will be used, and descriptions thereof will be omitted.

As shown in FIG. 2, on a semi-insulating InP substrate 201, an n-type impurity doped with a high concentration of n-type impurities is formed.
A first collector layer 202 which is a sub-collector layer of P is laminated. On the first collector layer 202, a second collector layer 203 of InP doped with undoped or n-type impurities at a low concentration is laminated, and the collector electrode 20 is formed.
9 are provided. On the second collector layer 203, an undoped InGaAsP and an n-type impurity doped I
A third collector layer 204 composed of two layers of nGaAsP is stacked. On the third collector layer 204, a fourth collector layer 205 of undoped InGaAs is laminated.

Here, the third collector layer 204 is formed of the second collector layer 203 and the fourth collector layer 205 in order to reduce the carrier blocking effect due to the conduction band discontinuity between the second collector layer 203 and the fourth collector layer 205. And intervenes between them. In this example, the second to fourth collector layers 20 are used.
A collector layer is constituted by 3 to 205 and the like.

On the fourth collector layer 205, a substrate 1
A base layer 206 of InGaAs doped with a p-type impurity at a higher concentration toward the 01 side is stacked. On the base layer 206, an InP emitter layer 207 doped with an n-type impurity is stacked, and a base electrode 210 is formed.
Is provided. On the emitter layer 207, an InGaAs emitter cap layer 208 doped with an n-type impurity at a high concentration is laminated. Emitter cap layer 20
An emitter electrode 211 is provided on 8.

The electrodes 209 to 211 are made of P
t / Ti / Pt / Au, so that an ohmic contact can be obtained without using a alloy.

On the side surface of the substrate 201, a so-called inverted mesa 212, which is an entrance window inclined inward so as to be concave toward the inside of the substrate 201, is formed. This reverse mesa 212
Can be easily formed by using, for example, a wet etching solution having crystal plane selectivity such as bromomethanol.

In such an HPT, the 1.55 μm band signal light 1 is applied to the reverse mesa 2 in the direction along the surface of the substrate 201.
12, the signal light 1 is turned into the inverted mesa 212.
Of the substrate 201 and the layers 202 to
The light passes through the substrate 204 obliquely with respect to the lamination direction and is absorbed by the fourth collector layer 205 and the base layer 206. The layer 2
05, 206, the layers 205, 206
Signal light 1 that has passed through the emitter cap layer 2
08, most of the light is reflected by the emitter electrode 211 and absorbed by the fourth collector layer 205 and the base layer 206.

That is, the PD-H of the above-described embodiment is used.
As in the case of the BT OEIC, the signal light 1 is
2, the signal light 1 is refracted at the time of incidence and is passed obliquely to the lamination direction to increase the passing distance, and is highly doped with n-type impurities.
By applying the first collector layer 202 of P, the bandgap energy is made larger than the energy corresponding to the wavelength of the signal light 1, and the first collector layer 202 of the incident light 1 is increased.
, The amount of incident light 1 absorbed by the fourth collector layer 205 and the base layer 206 is increased, and the emitter electrode 211 is made of a non-alloy, thereby improving the flatness of the electrode interface. The signal light 1 that has not been absorbed by the collector layer 205 and the base layer 206 is reflected by the emitter electrode 211 and is passed obliquely through the fourth collector layer 205 and the base layer 206 again.

For this reason, the PD-H of the above-described embodiment is used.
As in the case of the BT OEIC, the fourth collector layer 205
And the distance of the signal light 1 passing through the base layer 206 increases, so that the layers 205 and 206 need not be thickened.
The sensitivity on the light receiving device side can be increased.

Further, the PD-HBT of the above-described embodiment is used.
As in the case of the OEIC, by making the signal light 1 enter from the reverse mesa 212, it is not necessary to form an entrance window in the emitter electrode 211, and the emitter electrode 211 entirely covers the emitter layer 207 and the emitter cap layer 208. Therefore, the emitter resistance can be reduced, and miniaturization can be facilitated.

Further, the PD-HBT of the above-described embodiment is used.
As in the case of the OEIC, by increasing the concentration of the p-type impurity doped into the base layer 206 toward the substrate 201, electrons excited in this region can be accelerated toward the collector layer by an internal electric field. No tailing appears in the time response waveform of the electric signal.

Therefore, according to such an HPT,
As in the case of the PD-HBT OEIC described above, it is possible to eliminate the trade-off between the light receiving sensitivity and the operation speed.

[HPT-HBT OEIC] When the OEIC according to the present invention is applied to the HPT-HBT OEIC,
The PD portion of the PD-HBT OEIC shown in FIG. 1 is changed to the HPT shown in FIG. 2, and the same operation and effect as those of the above-described embodiment can be obtained. I do.

In each of the above-described embodiments, the photoexcited electrons are directed to the first to fourth semiconductor layers 102 to 105 and to the fourth and fourth semiconductor layers 102 and 105 by providing a gradient in the impurity concentration of the fifth semiconductor layer 106 and the base layer 206. 1-4 collector layers 202-2
The response speed is increased by quickly pulling out the layer to the side of the fifth layer. For example, by using InGaAsP whose composition is changed continuously or stepwise in the stacking direction for the fifth semiconductor layer and the base layer, the band gap of the layer is reduced. It is also possible to reduce the energy on the substrate side.

For the p-side electrode 110a of the PD and the emitter electrode 210 of the HPT, a non-alloy material having a high melting point, such as WSi, can be used.

The emitter cap layer 209 has InG
By applying aAsP, the absorption of the signal light 1 can be prevented.

As described above, the above-mentioned layer structure does not cause any trouble even if it is appropriately selected and changed without departing from the spirit of the present invention.

[0066]

According to the photoelectric integrated circuit and the heterojunction phototransistor of the present invention, the absorption sensitivity can be increased without increasing the thickness of the absorption layer, and a window through which signal light enters is formed in the electrode. Since there is no need, the parasitic resistance of the light receiving device can be reduced, and the element can be easily miniaturized. Therefore, it is possible to overcome the trade-off between the light receiving sensitivity of the light receiving device and the operation speed of the electronic device, and achieve high performance. As a result, for example, a practical level of sensitivity and operation speed can be obtained even in an opto-electric integrated circuit that processes a digital signal by directly inputting an output signal of a photodiode to a digital IC.

[Brief description of the drawings]

FIG. 1 shows a photoelectric integrated circuit according to the present invention as a PD-HBT.
FIG. 2 is a schematic configuration diagram of an embodiment when applied to OEIC.

FIG. 2 is a schematic configuration diagram of an embodiment of a heterojunction phototransistor according to the present invention.

FIG. 3 shows a PD-HBT as an example of a conventional photoelectric integrated circuit.
FIG. 2 is a schematic configuration diagram of an OEIC.

FIG. 4 is a schematic configuration diagram of a conventional heterojunction phototransistor.

[Explanation of symbols]

 1 signal light 101, 201 substrate 102, 202 first collector layer 102a first semiconductor layer 103, 203 second collector layer 103a second semiconductor layer 104, 204 third collector layer 104a third semiconductor layer 105, 205 fourth collector layer 105a Fourth semiconductor layer 106, 206 Base layer 106a Fifth semiconductor layer 107, 207 Emitter layer 108, 208 Emitter cap layer 109, 209 Collector electrode 109a P-side electrode 110, 210 Base electrode 110a N-side electrode 111, 211 Emitter electrode 112 , 212 Reverse mesa

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/73 31/10 F term (Reference) 4M118 AA01 AB05 BA02 CA09 CA15 CA40 FC09 FC15 FC16 5F003 BA21 BA27 BB01 BC04 BF06 BG06 BH08 BH99 BJ12 BM03 5F049 MA03 MA13 MB07 NA01 NA03 NB01 PA14 RA06 SE05 SE12 SE16 SE20 SS04 SS09 WA01 5F082 AA06 BC20 CA02 DA09

Claims (12)

[Claims] A sub-collector layer, a collector layer,
A heterojunction bipolar transistor in which a base layer and an emitter layer are stacked to have a collector electrode, a base electrode, and an emitter electrode; and the subcollector layer, the collector layer, and the base layer of the heterojunction bipolar transistor on the substrate, A photodiode having respective electrodes formed simultaneously with the collector electrode and the base electrode of the hetero-junction bipolar transistor, and converting signal light incident on the photodiode into an electric signal. In the opto-electrical integrated circuit for processing and outputting, by providing an incident window through which the signal light is incident on the side end surface of the substrate on the photodiode side so as to be inclined so as to be recessed inward in the thickness direction of the substrate, The signal light incident from the entrance window is refracted, and Optoelectronic integrated circuit is characterized in that so as to pass obliquely with respect to the stacking direction in the semiconductor layer of the diode. 2. The optoelectronic integrated circuit according to claim 1, wherein said electrode of said photodiode formed simultaneously with said base electrode of said heterojunction bipolar transistor is non-alloy ohmic. Integrated circuit. 3. The opto-electric integrated circuit according to claim 1, wherein an impurity concentration or a band gap energy of said semiconductor layer of said photodiode common to said base layer of said hetero-junction bipolar transistor is:
An optoelectronic integrated circuit, wherein the number of the photodiodes decreases stepwise or continuously toward the semiconductor layer side of the photodiode common to the collector layer of the heterojunction bipolar transistor. 4. The photoelectric integrated circuit according to claim 1, wherein a band gap energy of said semiconductor layer of said photodiode common to said sub-collector layer of said hetero-junction bipolar transistor is equal to that of signal light. An opto-electrical integrated circuit characterized in that the energy is greater than the energy corresponding to the wavelength. 5. A sub-collector layer, a collector layer,
A heterojunction bipolar transistor having a base layer and an emitter layer stacked thereon and having a collector electrode, a base electrode and an emitter electrode, and the sub-collector layer, the collector layer, the base layer, and the base layer of the heterojunction bipolar transistor on the substrate. A collector electrode, a base electrode, and a collector electrode formed simultaneously with the collector electrode, the base electrode, and the emitter electrode of the heterojunction bipolar transistor having a subcollector layer common to the emitter layer, a collector layer, a base layer, and an emitter layer; A heterojunction phototransistor having an emitter electrode, wherein the optoelectronic integrated circuit converts the signal light incident on the heterojunction phototransistor into an electric signal and outputs the electric signal. Heterojunction photo A signal light incident through the incident window is refracted by being provided on the side end surface on the transistor side so as to be inclined toward the inner side in the thickness direction of the substrate, and laminated in the layer of the hetero-junction phototransistor. An opto-electrical integrated circuit characterized in that the light is passed obliquely to a direction. 6. The optoelectronic integrated circuit according to claim 5, wherein said emitter electrode of said heterojunction phototransistor is non-alloy ohmic. 7. The opto-electric integrated circuit according to claim 5, wherein the impurity concentration or band gap energy of the base layer of the heterojunction phototransistor is more stepwise or closer to the collector layer of the heterojunction phototransistor. An optoelectronic integrated circuit characterized by a continuous decrease. 8. The opto-electric integrated circuit according to claim 5, wherein a band gap energy of said subcollector layer of said heterojunction phototransistor is larger than an energy corresponding to a wavelength of signal light. A photoelectric integrated circuit characterized by the following. 9. A sub-collector layer, a collector layer,
A heterojunction bipolar transistor having a base layer and an emitter layer stacked and having a collector electrode, a base electrode, and an emitter electrode, and having a heterojunction bipolar transistor having a collector electrode, a base electrode, and an emitter electrode. Is provided on the side end surface of the substrate so as to be inclined so as to be depressed toward the inner side in the thickness direction of the substrate, thereby refracting the signal light incident from the incident window, thereby forming the heterojunction bipolar transistor. The heterojunction phototransistor characterized in that it passes through the layer obliquely to the laminating direction. 10. The heterojunction phototransistor according to claim 9, wherein said emitter electrode is non-alloy ohmic. 11. The heterojunction phototransistor according to claim 9, wherein an impurity concentration or a band gap energy of said base layer decreases stepwise or continuously toward said collector layer. Heterojunction phototransistor. 12. The heterojunction phototransistor according to claim 9, wherein the bandgap energy of the subcollector layer is larger than the energy corresponding to the wavelength of the signal light. Transistor.