TW573367B - Method for manufacturing self-aligned rear electrode of photodiode - Google Patents

Abstract

A method for manufacturing a self-aligned rear electrode of a P+ amorphous silicon (P+ a-Si)/Intrinsic a-Si/N+ a-Si (PIN) thin film photodiode is disclosed. The method defines a first N+ a-Si layer and a top metal layer under the first N+ a-Si layer after the first N+ a-Si layer being formed on the top metal layer, and then forms a second N+ a-Si layer to cover the defined first N+ a-Si layer and the top metal layer, and performs an etching back step to make the top metal layer be covered by the first N+ a-Si layer and the second N+ a-Si layer, thereby forming the self-aligned rear electrode.

Description

573367 V. Description of the invention (1) The technical field to which the invention belongs: The present invention relates to a method for manufacturing a self-aligned rear electrode (Thin-Film Photodiode), In particular, it relates to the self of an elevated (P + Amorphous SiliCQn; p + a-Si) / intrinsic / N + amorphous silicon (pIN) film photodiode Method for manufacturing alignment electrode. Prior art: Generally, conventional image sensors (I m ag e Sen sor) or pixels (p i X e 1) elements 'such as photosensitive ^ a ^ polar body' are made directly on the broken substrate. However, with the miniaturization of the size of pixel elements, a multilayer interconnection structure is adopted to increase the circuit density. In this way, the photosensitivity will decrease due to light scattering, low u-shaped lens gain, and low fill factor (Fi 1 1 Fact or), which will affect the light intensity that the pixel element can capture. In order to solve the problem caused by the miniaturization of the size of the pixel element, currently, a raised type PI N thin film pixel element has been exhibited to improve the fill factor and thereby increase the light sensitivity. The so-called elevated pixel element refers to a pixel element that lifts its photodetector from a silicon substrate to an upper conductor layer above an interconnect structure. In this way, the light sensed by the photodetector does not need to pass through the interconnect structure, avoiding the occurrence of light scattering to affect the light intensity, and it does not need to focus through the U-shaped lens, and there will be no u-shaped lens gain Low problem. In addition, when the photodetector is fabricated on the upper conductor layer above the interconnect structure, the production area of the photodetector can be greatly increased, so that it can greatly increase 573367 V. Description of the invention (2) & gastric filling factor The intensity of light that can be captured. In addition, 'to prevent the back electrode of the pixel element and the like from coming into direct contact with the intrinsic semiconductor that is subsequently formed, the Schottky junction interface (Schottky junction interface)' is caused, which in turn causes vertical leakage current. The current solution is to add an N + semiconductor layer between the back electrode and the intrinsic semiconductor to isolate the back electrode from the intrinsic semiconductor. Please refer to FIG. 1 to FIG. 4, which are cross-sectional views showing a process for forming a conventional back electrode of a thin film photodiode. Firstly, a substrate 100 is provided. The substrate 100 provided here may be a component necessary for forming a photosensitive element, such as a transistor and an active region. Since the photosensitive diode is an elevated type, Therefore, the substrate 100 also includes an interconnect structure located on the transistor or the active region. Next, an upper metal layer 102 is deposited to cover the substrate 100, and an upper metal layer 102 is defined, and a part of the substrate 100 is exposed, and a desired pattern is formed on the substrate 100. The upper metal layer 102 has a structure as shown in FIG. 1. Then, the N + -type amorphous silicon layer 104 is deposited on the exposed substrate 100 and the upper metal layer 102 to form a structure as shown in FIG. 2. Photolithography and etching technology are used to define the N + type amorphous silicon layer 104, and a part of the N + type amorphous silicon layer 104 is removed, and a part of the substrate 100 is exposed to pattern the N + type Amorphous silicon layer 104. The patterned N + -type amorphous silicon layer 104 covers only the periphery of the upper metal layer 1 02, and the N + -type amorphous silicon layer 104 and the upper metal layer 1 0 2 that it covers constitute the back electrode 10 5. The structure shown in Figure 3. In order to ensure the reliability of the process, so that the N + -type amorphous silicon layer 104 can completely cover the upper metal layer 100 after the patterning process is completed, so 573367 V. Description of the invention (3) One 'one The thickness of the ^ -type amorphous silicon layer 104 is at least about 0.2 micrometers (m). Such a layer = the size of the non-inch crystal stone layer 104 will be much larger than that of the overlying upper metal layer. After the back electrode 105 is formed, the intrinsic amorphous silicon layer i 0 and the exposed substrate 100 are deposited. A P + i non- ^ layer 108 is deposited over the intrinsic amorphous silicon layer i 06. Among them, the p + type amorphous silicon layer 108, the intrinsic amorphous silicon layer 106, and the N + type amorphous silicon layer 104 constitute a piN thin film stack structure. After the PIN thin film stack structure is formed, a light-transmitting Indium Tin Oxide (ITO) layer 11 is covered with a P + -type amorphous silicon layer 108 as an electrode on the pixel element, and the fabrication of the pixel element is completed. (As shown in Figure 4). However, the size of the N + amorphous silicon layer 104 is much larger than that of the upper layer when the N + amorphous silicon layer 104 is produced to cover the back metal layer 105 and the upper metal layer 102 is limited by process technology. The size of the metal layer 102 is large, which triggers an extension rule, which in turn leads to an increase in the size of the pixel element or a decrease in the fill factor of the pixel element. Summary of the invention:

In view of the fact that the conventional backside electrode of the thin film photodiode is manufactured in the above process, it is limited by the process method, which results in that the size of the N + type amorphous stone layer coated on the conductive layer of the backside electrode cannot be effectively reduced, resulting in light sensitivity. The pixel size of the diode increases, and the intensity of light that the pixel can capture decreases. In addition, an additional mask step is required to define the N + type amorphous silicon layer on the conductor layer. Therefore, one of the main objects of the present invention is to provide a photodiode

Page 7 573367 V. Description of the invention (4) Self-aligned backside metal (Etching Back) technology metal layer, and it is quite easy to have a conductive material layer directly connected to another object of the present invention as a photodiode The conductive layer of the back electrode is punched on, and the dimensional strength of the pixel of the conductive layer polar body. Another object of the present invention is a method for manufacturing an electrode, which forms a self-aligned backside N + semiconductor buffer layer process cost. According to the purpose described above, the back electrode is self-aligned, wherein at least one of the substrates is sequentially stacked on the upper metal layer; the substrate; a second structure is formed, and the exposed crystalline silicon layer is covered to expose The manufacturing method of the electrode is to form an N + semiconductor buffer alignment method to complete the back side electrical effect to prevent the upper metal layer from touching and avoid vertical leakage. This is to provide a method using a surface electrode, which can form a complete package with a smooth thickness. Cover it. Therefore, to further enhance the image effectively is to provide a thin film electrode which can be etched back without the need for additional patterning. Therefore, the manufacturing method provided by the present invention further includes at least a stacked structure, a metal layer, and a substrate defined by the above-mentioned stacked structure N + type amorphous silicon layer; and removing The previously exposed substrate is fabricated by completely covering the upper layer with an etch-back layer. Therefore, the subsequent formation of an intrinsic semi-current. The self-aligning method can be used to make the remaining steps. The thin N + semiconductor can greatly reduce the light that the photodiode can capture. The back of the photodiode uses a photomask to simplify the self-alignment. The process of reducing the production of a photodiode includes: providing a substrate, the stacked structure including at least an N + -type amorphous silicon layer covering to expose a part of the second N + -type of the defined stack junction portion and form itself Aim at the back

Page 8 573367 V. Description of the invention (5) Surface electrode. The step of removing a part of the second N + -type amorphous silicon layer is automatic and can be achieved by an etch-back method. I. Alignment step By engraving the second N + type amorphous stone layer, it is possible to make the upper metal layer completely the first N + type amorphous silicon layer and align the amorphous silicon layer. Covered by layers. Therefore, it can not only prevent the subsequently formed = N + silicon layer from directly contacting the metal layer above the back electrode, but also avoid the gold leakage current guided by the Schottky interface formed by the amorphous metal layer and the intrinsic amorphous silicon layer. produce. In addition, the thickness of the vertical amorphous silicon layer covering the upper layer of gold can be greatly reduced, thereby reducing the pixel size and increasing the light intensity captured by the photosensitive type II. A visually acceptable embodiment: The present invention discloses a self-aligning manufacturing method of a PIN thin film photodiode, which is covered with a relatively thin layer of N + semiconductor buffers to isolate the electrodes on the back electrode using an etch-back technique. Conductor layer and intrinsic semiconductor layer. Therefore, it is not only avoidable; streamline, simplify the process, reduce costs, but also can reduce / increase the fill factor ... In order to make the invention ": =; = Provision, you can refer to the following description and cooperate with Figures 5 to 9 Please refer to Figure 5 to Figure 9 for the completeness and detail, which shows this hair ::. Self-aligned back side of a thin film photodiode = Example Example: The self-alignment of a thin film photodiode is raised. J = f sectional view. This hair is provided for the substrate 200, of which the noteworthy two V: power generation: First of all, the electrode system is applied to a photodiode and other photogenic diodes. The self-aligned back bottle of the invention is found in 7L pieces. provide

573367 V. Description of Invention (6)

The base material 200 may be a necessary element for forming a photosensitive element, such as a transistor and an active region. In addition, the photodiode of the present invention is of an elevated type, so the substrate 200 also includes an interconnect structure on the transistor or the active region. Since the composition of the substrate 2000 is not the focus of the present invention, the amount can be omitted. Next, for example, a chemical vapor deposition method or a sputtering method is used to form an upper conductor layer 202 to cover the substrate 200 as a conductive layer for the back electrode. The material of the upper conductor layer 202 may be, for example, a metal such as steel, metal, or aluminum-copper alloy. After the upper conductor layer 202 is formed, an N + type semiconductor buffer layer 20 4 is formed to cover the upper conductor layer 202 by a method such as electric mass gain chemical vapor deposition (PECVD), and the substrate 200 is formed as The stacked structure shown in FIG. 5. Among them, the material of the N + type semiconductor buffer layer 204 may be, for example, amorphous. After the N + -type semiconductor buffer layer 204 is formed, a pattern definition of the back electrode is performed using, for example, lithography and etching techniques to remove a portion of the N + -type semiconductor buffer layer 204 and a portion of the upper conductor layer 202, and form the substrate 200 In addition, there is an upper conductor layer 202 and an N + type semiconductor buffer layer 204 of a desired pattern, and a part of the substrate 200 is exposed. The structure formed is shown in FIG. 6.

After the pattern definition of the upper conductor layer 202 and the N + -type semiconductor buffer layer 204 is completed, another N + -type semiconductor buffer layer 206 is formed to cover the upper conductor layer 202 and the N + type by, for example, plasma gain chemical vapor deposition. The stacked structure formed by the semiconductor retardation layer 204 is covered on the exposed substrate 200 ′ to form the structure shown in FIG. 7. The material of the N + -type semiconductor buffer 204 may be, for example, amorphous silicon. Then, for example, part of the N + -type semiconductor buffer layer is removed by engraving.

573367 V. Description of the invention (7) 206, and a part of the substrate 200 is exposed, so that the remaining scale + type semiconductor buffer layer 20 6 and the N + type semiconductor buffer layer 20 4 completely cover the upper conductor layer 20 2 , As shown in Figure 8. Among them, the remaining N + -type semiconductor buffer layer 206, the N + -type semiconductor buffer layer 204, and the upper conductor layer 202 constitute a self-aligned back electrode 207. One feature of the present invention is that the N + -type semiconductor buffer layer 20 6 and the n + -type semiconductor buffer layer 20 4 can completely cover the upper conductor layer 202 by self-alignment. Therefore, a mask procedure for defining an N + type semiconductor buffer structure can be saved, thereby achieving the purpose of simplifying the process and reducing the process cost. In a preferred embodiment of the present invention, the thickness of the N + -type half-width of the side wall of the stacked structure formed by the N + -type semiconductor buffer layer 204 and the upper conductor layer 202 can be as small as about Q.Wm. , So it is much smaller than the 0/2 private melon. Therefore, compared with the conventional technology, the present invention can not only effectively reduce the size of the back electrode, but also achieve the purpose of reducing the pixel size, and can increase the fill rate of light. After the formation of 1 ′: using, for example, a plasma gain chemical vapor deposition technique: layer = and_semiconductor buffer layer m, and the exposed intrinsic semiconductor layer 208 may be, for example, a core conductor layer 2 0 2 is completely covered by the N + -type semiconductor buffer layer 2 + conductor buffer layer 204, so that t 1 can be prevented from directly contacting the upper conductor layer 202. In this way, "? Layer 208 body layer 2G8 and upper conductor layer 2G2 can generate a Schottky joint interface ^ half / 573367 V. Description of the invention (8) ^ ----_ Effective prevention, the Schottky joint between the two The vertical leakage current caused by the interface is generated. Then, a conductive layer 210 is formed on the intrinsic semiconductor layer 208 by, for example, plasma-benefit chemical vapor deposition. The material of the p + type layer 210 may be, for example, amorphous. The above-mentioned p + -type semiconductor; the body 210, the intrinsic semiconductor layer 208, and the N + -type half of the back electrode 207 are formed on the substrate layer 2 0 6 and the N + -type semiconductor buffer layer 2 0 4 to form p IN. A stacked structure. Then, a light-transmitting conductor layer 2 丨 2 is formed to cover the & type semiconductor layer 2 10 by, for example, sputtering deposition, and the structure shown in FIG. 9 is formed to complete the PIN film photodiode. Fabrication of components. Among them, the material of the light-transmitting conductor layer includes at least indium tin oxide. 9 In summary, one of the advantages of the present invention is that by using the etch-back technology, the formed N + semiconductor buffer layer can be self-aligned. Completely covers the upper conductor layer. Therefore, It is very easy to prevent the upper conductor layer from contacting the semiconductor material layer, and to effectively avoid vertical leakage current. Another advantage of the present invention is that the conductor layer of the back electrode can be smoothly passed through the etch-back step. The N + -type semiconductor buffer layer with a relatively thin thickness is formed on the ground: the conductor layer is completely covered. Therefore, the size of the pixels of the photodiode can be greatly reduced, thereby achieving the purpose of increasing the light intensity that the pixels can capture. Another advantage is that since the self-aligned back electrode can be formed in a self-aligned manner by the etch-back step, the procedure of defining a mask can be saved, thereby achieving the purpose of simplifying the process and reducing the cost of the process. If you are familiar with this technology What the person understands is that the above is only a comparison of the present invention.

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573367 V. Description of the invention (9) It is only a good example and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. Page 13 573367 Schematic illustration of the preferred embodiment of the present invention has been described in more detail in the preceding explanatory text with the following figures, where: Figures 1 to 4 show the conventionally raised thin film photodiodes And FIG. 5 to FIG. 9 are cross-sectional views illustrating a process of self-aligning a back electrode of a raised thin film photodiode according to a preferred embodiment of the present invention.

Comparative description of drawing numbers: 100 substrate 102 upper metal layer 104 N + type amorphous silicon layer 105 back electrode 106 intrinsic amorphous silicon layer 108 P + type amorphous silicon layer 110 indium tin oxide layer 200 substrate 202 upper conductor layer 204 N + Type semiconductor buffer layer 206 N + type semiconductor buffer layer 207 back electrode 208 intrinsic semiconductor layer 210 P + type semiconductor layer 212 light-transmitting conductor layer

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Claims (1)

573367 6. Scope of patent application 1. A method for manufacturing a self-aligned rear electrode of a photodiode, at least including: providing a substrate, wherein the substrate includes at least a stacked structure And the stack structure includes at least one upper conductor layer and a first type 1 semiconductor layer stacked on the upper conductor layer in order; defining the stack structure to expose a part of the substrate; forming a first Two N + -type semiconductor layers cover the defined stack structure and cover the exposed substrate; and a portion of the second N + -type semiconductor layer is removed to expose the substrate and form the self-alignment Back electrode. 2. The method for manufacturing a self-aligned back electrode of a photodiode according to item 1 of the scope of patent application, wherein the material of the upper conductive layer includes at least metal. 3. The method for manufacturing a self-aligned back electrode of a photodiode according to item 1 of the scope of the patent application, wherein the material of the first N + -type semiconductor layer includes at least amorphous silicon (a-Si). • The method for manufacturing a self-aligned back electrode of a photodiode as described in item 1 of the scope of patent application, wherein the material of the second N + type semiconductor layer includes at least amorphous silicon. Page 15 573367 VI. Patent Application Range 5. The method for manufacturing a self-aligned back electrode of a photodiode as described in item 1 of the patent application range, wherein the step of removing part of the second N + type semiconductor layer uses a Etching Back method. 6. The method for manufacturing a self-aligned back electrode of a photodiode as described in item 1 of the scope of patent application, wherein after the step of removing a portion of the second N + type semiconductor layer, it further includes forming at least one intrinsic ( An Intrinsic) semiconductor layer covers the self-aligned back electrode and the exposed substrate. 7. The method for manufacturing a self-aligned back electrode of a photodiode as described in item 6 of the scope of patent application, wherein the material of the intrinsic semiconductor layer includes at least amorphous silicon. 8. The method for manufacturing a self-aligned back electrode of a photodiode according to item 6 in the scope of the patent application, wherein after the step of forming the intrinsic semiconductor layer, the method further includes forming at least a P + type semiconductor layer Overlying the intrinsic semiconductor layer. 9. The method for manufacturing a self-aligned back electrode of a photodiode according to item 8 of the scope of the patent application, wherein the material of the P + type semiconductor layer includes at least amorphous silicon. 10. Self-aligning back of photodiode as described in item 8 of the scope of patent application Page 16 573367 6. Scope of applying for a patent The manufacturing method of the surface electrode, wherein after the step of forming the 51 semiconductor layer, it further includes at least forming a light-transmitting conductor layer to cover the p + -type semiconductor layer. The method for manufacturing a self-aligned back electrode of a photodiode according to the item, wherein the material of the light-transmitting conductor layer includes at least indium tin oxide (ιτο). 1 2 · The method of manufacturing a self-aligned back electrode of a photodiode as described in item 1 of the scope of patent application, wherein the photodiode system is an Elevated film photodiode. 13. A method for manufacturing a self-aligned back electrode of a photodiode, at least a substrate, wherein the substrate includes at least a stacked structure, and the stacked structure includes at least one upper metal layer and a A first N + -type amorphous silicon layer covers the upper metal layer; _. Defines the stacked structure to expose a part of the substrate, > the stacked structure defined after 4 v 丄 々 齑, and Forming a second N + plastic amorphous silicon layer overlying the exposed substrate; and 丄 & LC: I a 厝 to expose the substrate 'and remove a portion of the second N The + -type amorphous silicon layer forms the self-aligned back electrode. Photodiode self-alignment back 1 4 · Feel as described in item 13 of patent application scope 573367 6. Scope of patent application The method for manufacturing a surface electrode, wherein the photodiode system raises the film photodiode. 15. The method for manufacturing a self-aligned back electrode of a photodiode as described in item 13 of the scope of patent application, wherein the step of removing a portion of the second N + type amorphous silicon layer is by an etch-back method . 16. The method for manufacturing a self-aligned back electrode of a photodiode according to item 13 of the scope of patent application, wherein after the step of removing a part of the second N + type amorphous silicon layer, it further includes at least forming An intrinsic semiconductor layer covers the self-aligned back electrode and the exposed substrate. 1 7. The method for manufacturing a self-aligned back surface electrode of a photodiode as described in item 16 of the scope of patent application, wherein the material of the intrinsic semiconductor layer includes at least amorphous silicon. 1 8. The method for manufacturing a self-aligned back electrode of a photodiode as described in item 16 of the scope of patent application, wherein after the step of forming the intrinsic semiconductor layer, the method further includes forming at least a P + type amorphous silicon A layer covers the intrinsic semiconductor layer. 19. The method for manufacturing a self-aligned back electrode of a photodiode as described in item 18 of the scope of patent application, wherein after the step of forming the P + -type amorphous silicon layer, it further includes at least forming a light-transmitting conductor Layer overlying the P + type amorphous silicon layer Page 18 573367 6. The scope of patent application. 20 · The method for manufacturing a self-aligned back electrode of a photodiode as described in item 19 of the scope of patent application, wherein the material of the light-transmitting conductor layer includes at least indium tin oxide. 21. A method for manufacturing a self-aligned back electrode of a photodiode, at least comprising: providing a substrate, wherein the substrate includes at least a stacked structure, and the stacked structure includes at least one upper metal layer sequentially stacked Layer and a first N + type amorphous silicon layer cover the upper metal layer; define the stacked structure to expose a part of the substrate; form a second N + type amorphous silicon layer to cover the defined layer Stacking the structure and covering the exposed substrate; and performing an etching step to expose the substrate and leave the upper metal layer as the first N + amorphous silicon layer and the second N + Type amorphous silicon layer is completely covered. 2 2. The method for manufacturing a self-aligned back surface electrode of a photodiode as described in item 21 of the scope of patent application, wherein the photodiode system raises the thin-film photodiode. 2 3. The method for manufacturing a self-aligned back surface electrode of a photodiode as described in item 21 of the scope of patent application, wherein a part of the second N + type amorphous silicon is removed Page 19 573367 6. After the step of applying for the patent scope layer, it further includes forming at least an intrinsic semiconductor layer to cover the remaining first N + type amorphous silicon layer and the second N + type amorphous silicon layer, and exposing the On the substrate. 2 4 · The method for manufacturing a self-aligned back electrode of a photodiode as described in item 23 of the scope of patent application, wherein the material of the intrinsic semiconductor layer includes at least amorphous silicon. 25. The method for manufacturing a self-aligned back electrode of a photodiode as described in item 23 of the scope of patent application, wherein after the step of forming the intrinsic semiconductor layer, the method further includes at least forming a P + type amorphous silicon A layer covers the intrinsic semiconductor layer. 26. The method for manufacturing a self-aligned back electrode of a photodiode as described in item 25 of the scope of patent application, wherein after the step of forming the P + type amorphous silicon layer, it further includes forming at least indium tin oxide A layer covers the P + type amorphous silicon layer. Page 20