JPH04268853A - Data latching device for plug-in type package - Google Patents

Abstract

PURPOSE:To latch data immediately before taking-out to a receiving side package whether either a data transmitting plug-in terminal or a data latching plug-in terminal between the packages is taken out first in respect of the data latching device of a plug-in package for latching receive data to the receiving side package when the package capable of being put in and taken out is taken out. CONSTITUTION:This device is constituted by providing the data transmitting plug-in terminal 3 for transmitting the data from the transmitting side package 1 to the receiving side package 2, an inverted data transmitting plug-in terminal 4 for transmitting inverted data, a data inverting means 6 for inverting again the inverted data, a non-coincidence detecting means 8 for detecting non- coincidence between the receive data from both the plug-in terminals 3, 4, and a latch control means 9 to make a data latching means 7 latch the receive data immediately before the detection of the non-coincidence in response to the detection of the non-coincidence by the non-coincidence detecting means 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data latch device for a removable package for latching received data in a receiving package when a removable package is removed.

[0002] In a transmission device configured to exchange data between a plurality of packages, when a package is removed, it is necessary to latch (hold) the immediately preceding data in the receiving package.

0003

2. Description of the Related Art In order to latch data when a package is removed, a latch insertion/extraction terminal is provided between the packages in addition to a data transmission insertion/extraction terminal.

[0004] There are two methods for latching data: a method in which the data latch clock is transferred between packages via latch insertion/removal terminals, and a method in which the data latch clock is held in the receiving package and is held in the transmitting package. There is a method in which mounting information (insertion/extraction information) is transferred via a latch insertion/extraction terminal.

FIG. 6 shows a conventional example of a system in which a data latch clock is transferred between packages.

[0006] 1 is a sending package, and 2 is a receiving package. 3 and 5 are insertion/extraction terminals for data transmission and insertion/extraction terminals for latch. Data is transferred from the sending package 1 to the receiving package 2 via the data transmission insertion/extraction terminal 3 and the data latch clock via the latch insertion/extraction terminal 5, and the data input terminal of the D flip-flop 70 Input to the clock input terminal. Resistors 11 and 13 provided in the receiving package 2 are for pull-up purposes.

Therefore, when the packages 1 and 2 are inserted, that is, when both the insertion/removal terminals 3 and 5 are in the inserted state, the data ■ held by the rising edge of the clock pulse ■ is released as shown in FIG. , is output from the output terminal of the D flip-flop 70 until the clock pulse ■ rises next. ■ to ■ indicate signal waveforms at each position on the circuit.

[0008] Then, the latch insertion/removal terminal 5 is removed first.
After that, when the data transmission insertion/removal terminal 3 is disconnected, the two pulled-up input signals (data ■ and clock ■) of the D flip-flop 70 are both fixed at high level, as shown in FIG. The data ■ held by the rising edge of the clock pulse ■ continues to be output as is.

In this way, the data immediately before the terminal is disconnected is latched in the receiving package 2. However, in order to do so, the latch insertion/removal terminal 5 that transmits the clock pulse must be
It is necessary to prevent the data transmission insertion/extraction terminal 3 from coming out first.

FIG. 9 shows a conventional device in which the receiving package 2 has a clock for data latching, and transmitting package mounting information is transferred via the latch insertion/extraction terminal 5. 11 and 13 are pull-up resistors, and 76 is a timer for generating clock pulses.

FIG. 10 shows an example of the configuration of the latch circuit of the receiving package 2. In FIG. 71 and 72 are first and second D flip-flops. 73 and 75 are first and second inverters. A timer 76 supplies clock pulses to the two D flip-flops 71 and 72. 77 and 78 are an OR circuit and an AND circuit. 79 is OR circuit 7
7, and the delay time caused by the reset of the first D flip-flop 71 and the delay circuit 79 is longer than the delay time caused by the second inverter 75 and the AND circuit 78. It is set to be.

Here, when the packages 1 and 2 are inserted, a low level signal (2) is input to the receiving package 2 through the latch insertion/extraction terminal 5, as shown in FIG. As a result, the output of the AND circuit 78 is always at a low level, so the OR circuit 77 delays the input signal ■, which is the same as the input signal ■ from the first D flip-flop 71 side, by one clock pulse, and outputs the second is output to the data input terminal of the D flip-flop 72.

Furthermore, since the output from the first inverter 73 is input to the reset terminal of the first D flip-flop 71, the signal thereof is always at a high level. Therefore, from the second D flip-flop 72, the input data ■
Data (2) delayed by two clock pulses compared to is output. ■ to ■ indicate signal waveforms at each position on the circuit.

[0014] Then, the latch insertion/extraction terminal 5 is pulled out first,
After that, when the data transmission insertion/removal terminal 3 is disconnected, the input ■ from the latch insertion/removal terminal 5 to the first inverter 73 becomes high level, as shown in FIG.
The input to the reset terminal of the flip-flop 71 becomes low level, and the output from the first D flip-flop 71 is stopped.

However, since the input from the second inverter 75 to the AND circuit 78 becomes high level, the output (2) from the second D flip-flop 72 is directly input from the AND circuit 78 to the OR circuit 77. The data is again input to the second D flip-flop 72, and the second D flip-flop 72 continues to output the data.

In this way, the data transmission insertion/removal terminal 3
The data immediately before the data is removed is latched by the receiving package 2, but in order to do so, it is necessary to prevent the data transmission insertion/extraction terminal 3 from coming out earlier than the latch insertion/extraction terminal 5.

Therefore, in any type of conventional device, the pins of the data transmission insertion/extraction terminal 3 are made longer than the pins of the latch insertion/extraction terminal 5, so that when the package is removed, the latch The insertion/removal terminal 5 was designed to be removed earlier than the data transmission insertion/removal terminal 3.

[0018]

However, in reality, when removing the packages 1 and 2, warpage of the printed circuit boards of the packages 1 and 2, variations in the lengths of the terminal pins 3 and 5, or variations in the length of the packages 1 and 2, 2, the data transmission insertion/removal terminal 3 having a long pin may come out earlier than the short latch insertion/removal terminal 5.

Then, in any of the above-mentioned systems, when the latch insertion/extraction terminal 5 is removed, the latch D
There was a drawback that data could not be latched because no data was input to the flip-flop.

Therefore, the present invention provides a data latch device for insertion/removal packages that can latch the immediately preceding data in the receiving package, regardless of which of the insertion/removal terminals for data transmission between packages or the insertion/removal terminals for latching is pulled out first. The purpose is to provide.

[0021]

[Means for Solving the Problems] In order to achieve the above object, the data latch device for an insertion/removal package of the present invention transmits data from a sending package 1 to a receiving package 2, as shown in FIG. For both packages 1,
2, and a data transmission insertion/removal terminal 3 provided between both packages 1 and 2 for transmitting inverted data, which is an inversion of the above data, from the sending package 1 to the receiving package 2. an insertion/removal terminal 4 for transmitting inverted data that is removably provided; a data inversion means 6 for re-inverting the inverted data received by the receiving package 2 through the insertion/removal terminal 4 for transmitting inverted data;
Data latch means 7 for latching data received from the transmitting package 1 in the receiving package 2, and data received by the receiving package 2 through the data transmission insertion/removal terminal 3 and inversion of the data. a mismatch detecting means 8 provided in the receiving package 2 to detect a mismatch with the output data from the means 6; and in response to the mismatch detection by the mismatch detecting means 8;
The present invention is characterized in that a latch control means 9 is provided in the receiving package 2 to cause the data latch means 7 to latch the data received by the receiving package 2 immediately before the detection.

The data latch means 7 is a D flip-flop 70, and the latch control means 9 outputs the output signal from the mismatch detection means 8 and the output signal from the transmitting package 1 to the receiving package 2. It may be an AND circuit that inputs a clock and outputs a signal to the clock input terminal of the D flip-flop 70, and the data latch means 7 inputs a clock and outputs a signal to the clock input terminal of the D flip-flop 70. The first D flip-flop 71 is reset by the output signal from the latch control means 9, and the output data from the first D flip-flop 71 at that time is transmitted to the second D flip-flop 72. It may also be latched.

[0023]

[Operation] When the insertion/extraction terminal 3 for data transmission and the insertion/extraction terminal 4 for inverted data transmission are disconnected, the mismatch detection means 8 detects a mismatch between the two input data. Then, in response to this, data received by the receiving package 2 immediately before the detection is latched by the data latch means 7. Therefore, there is no need to provide length differences between the terminals of the insertion/extraction section, and data transmitted from the transmitting package 1 is normally latched in the receiving package 2 no matter which terminal is pulled out first.

[0024]

[Embodiment] An embodiment will be described with reference to the drawings.

FIG. 2 shows an embodiment of a system in which a clock for data latch is sent through the latch insertion/extraction terminal 5.
This is an improvement on the first conventional example shown in FIGS. 6 to 8. Note that the same parts as in the conventional example are given the same reference numerals, and the explanation thereof will be omitted.

Reference numeral 21 denotes an inverter provided in the sending package 1 to invert the transmitted data, and the inverted data transmission insertion/removal terminal 4 for transmitting the inverted data is aligned with the data transmission insertion/removal terminal 3. It is set in. Then, in the receiving package 2, the inverted data is again inverted by the inverter 6. 12
is a pull-up resistor.

In the receiving package 2, the signal from the insertion/extraction terminal 3 for data transmission and the signal from the insertion/extraction terminal 4 for inverted data transmission via the inverter 6 are connected to an exclusive OR circuit (mismatch detection means) 8. Enter.

[0028]The exclusive OR circuit 8
The output from the AND circuit 9 and the clock from the latch insertion/extraction terminal 5 are input to the AND circuit 9, and the output signal from the AND circuit 9 is input to the clock input terminal of the D flip-flop 70.

Therefore, when the packages 1 and 2 are inserted, the two input signals in the exclusive OR circuit 8 match, so there is a high level output to the AND circuit 9; A clock pulse is input to the D flip-flop 70 from the D flip-flop 70.

When packages 1 and 2 are removed, the exclusive OR circuit 8 outputs a low level because the two inputs do not match, and the clock input from the AND circuit 9 to the D flip-flop 70 is inhibited. Ru.

Reference numeral 19 denotes a delay circuit for delaying the data transmission time from the inverter 6 to the data input terminal of the D flip-flop 70 by more than the delay time generated on the exclusive OR circuit 8 and AND circuit 9 sides.

With this configuration, when the latch insertion/extraction terminal 5 comes out earlier than the two data transmission insertion/extraction terminals 3 and 4, the receiving side package is removed at that time in the same way as in the first conventional example. 2, the data being received continues to be output from the D flip-flop 70.

On the other hand, when the data transmission insertion/removal terminals 3 and 4 are removed before the latch insertion/removal terminal 5, the output d of the exclusive OR circuit 8 becomes a low level, as shown in FIG. Then, the clock input e to the D flip-flop 70 is inhibited, and the data g held at the previous rising edge of the clock input e continues to be output from the D flip-flop 70.

In this way, the data transmission insertion/removal terminal 3
, 4 is pulled out before the latch insertion/extraction terminal 5, the data received by the receiving package 2 immediately before is latched. Note that a to g indicate signal waveforms at each position on the circuit.

FIG. 4 shows an embodiment of a system for transmitting package mounting information on the sending side using the latch insertion/extraction terminal 5, which is an improvement on the second conventional example shown in FIGS. 9 to 12. The specific circuit configuration is that the D flip-flop 70 of the first embodiment shown in FIG. 2 is replaced with the circuit of the second conventional example shown in FIG. A reference numeral is given and the explanation of the circuit is omitted.

In the case of this embodiment as well, when the latch insertion/removal terminal 5 comes out earlier than the two data transmission insertion/extraction terminals 3 and 4, the receiver package 2 The data being received continues to be output from the second D flip-flop 72.

On the other hand, when the data transmission insertion/removal terminals 3 and 4 are removed before the latch insertion/removal terminal 5, the output k of the exclusive OR circuit 8 becomes a low level, as shown in FIG. (mismatch detection), the output l from the AND circuit 9 becomes low level, and the first D flip-flop 71 is reset. Therefore, similarly to the case of the second conventional example shown in FIG.
The output (r) continues to be output from the flip-flop 72. Note that h to r indicate signal waveforms at each position on the circuit.

[0038]

Effects of the Invention According to the data latch device for insertion/removal packages of the present invention, regardless of the order in which the insertion/extraction terminals between packages are removed, the received data immediately before the insertion/extraction terminals are removed is latched in the receiving package. Malfunctions caused by removing the package can be eliminated without special considerations for insertion/extraction operations.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a configuration diagram of the first embodiment.

FIG. 3 is a time chart diagram of the first embodiment.

FIG. 4 is a configuration diagram of a second embodiment.

FIG. 5 is a time chart diagram of the second embodiment.

FIG. 6 is a configuration diagram of a first conventional example.

FIG. 7 is a time chart diagram of a first conventional example.

FIG. 8 is a time chart diagram of a first conventional example.

FIG. 9 is a configuration diagram of a second conventional example.

FIG. 10 is a partial configuration diagram of a second conventional example.

FIG. 11 is a time chart diagram of a second conventional example.

FIG. 12 is a time chart diagram of a second conventional example.

[Explanation of symbols]

1 Sending side package 2 Receiving side package 3 Data transmission insertion/extraction terminal 4 Inversion data transmission insertion/extraction terminal 5 Latch insertion/extraction terminal 6 Inverter (data inversion means) 7 Data latch means 8 Exclusive OR circuit (mismatch detection means) 9
AND circuit (latch control means)

Claims (3)

[Claims] Claim 1: Both packages (1) are used to transmit data from a sending package (1) to a receiving package (2).
, 2), and a data transmission insertion/removal terminal (3) which is removably provided between the data transmission terminals (3), and the inverted data which is inverted from the above data is transferred from the transmission side package (1) to the reception side package (1).
2) a reverse data transmission insertion/removal terminal (4) which is removably provided between both packages (1, 2) to transmit data to
data inversion means (6) for re-inverting the inverted data received by the receiving package (2) through the inverted data transmission insertion/extraction terminal (4); data latch means (for latching data received from the side package (1);
7), and the receiving terminal for detecting a discrepancy between the data received by the receiving package (2) through the data transmission insertion/extraction terminal (3) and the output data from the data inverting means (6). In response to the mismatch detection by the mismatch detection means (8) provided in the side package (2) and the mismatch detection means (8), the data received by the receiving side package (2) immediately before the detection is detected by the mismatch detection means (8). The receiving side package (
2) A data latch device for an insertion/removal package, characterized in that a latch control means (9) provided in the above is provided. 2. The data latch means (7) is a D flip-flop (70), and the latch control means (9) outputs the output signal from the mismatch detection means (8) and the transmission side package (1). 2. The data latch device for an insertable/removable package according to claim 1, wherein the data latch device is an AND circuit that inputs a clock sent from the receiver package (2) to the receiving package (2) and outputs a signal to a clock input terminal of the D flip-flop (70). 3. The data latch means (7) includes first and second D flip-flops (71, 72),
The first D flip-flop (71) is reset by the output signal from the latch control means (9), and the output data from the first D flip-flop (71) at that time is transferred to the second D flip-flop. The data latch device for an insertion/removal package according to claim 1, wherein the data latch device is latched by (72).