JPH04268758A - Manufacture of josephson integrated circuit - Google Patents

Abstract

PURPOSE:To remove a parasitic circuit element produced in the part where an LCR circuit chip is bonded with a Josephson element chip. CONSTITUTION:A capacitance is formed onto a chip together with a Josephson element in an integrated circuit forming manner, and an LCR circuit is built in the same chip where a Josephson element is provided. At this point, the flattening of layers required for the formation of a Josephson element is carried out through a flattening process such as a liftoff or the formation of a pattern used for eliminating steps caused by a contact hole.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing Josephson integrated circuits, which are expected to constitute next-generation ultra-high-speed supercomputers.

0002

BACKGROUND OF THE INVENTION Josephson integrated circuits based on a latching mechanism are based on an AC power supply bias system, and are relatively large-scale (more than 500 gates) and high-speed (1
If you try to drive it to a high frequency (GigaHz or higher), an impedance filter such as an LC filter type is installed between the low impedance superconducting part and the high impedance external power supply wiring.
A transformer is required. In addition, in order to reliably input high-speed signals with a relatively low current level from the external signal wiring at room temperature to the Josephson device section at extremely low temperature, it is necessary to connect a room temperature section between the external signal wiring and the Josephson device section. An LC filter or the like is required to cut thermal noise. For the impedance transformers and filters mentioned above, LCR circuits composed of inductors, capacitors, and resistors are often used to obtain good functionality.

However, since these LCR circuits have a different element structure and manufacturing process from ordinary Josephson elements, they cannot be configured as an integrated circuit on the same chip as ordinary Josephson elements. and Josephson elements are multi-chip connected.

[0004] In recent years, Josephson devices that actively utilize artificially constructed capacitance circuit elements have appeared. However, since capacitors are difficult to form in the Josephson device process, these prototype devices often adopt a hybrid configuration in which only the capacitor is attached externally to the device.

[0005]

[Problem to be solved by the invention] When using multi-chip connections or connecting only external capacitors, it is inevitable that undesigned parasitic inductance and capacitance will occur at the bonding part, and these values cannot be controlled. difficult to make. Not only that, but it is often difficult to make superconducting contacts at bonding points, which generates a finite resistance.

These difficulties hinder the attempt to drive the Josephson element at high frequencies in the microwave region (1 GHz or higher). It also leads to a reduction in the operating margin of the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a Josephson integrated circuit that eliminates the parasitic circuit elements generated in the bonding portion in the prior art.

[0008]

[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a Josephson integrated circuit according to the present invention includes a capacitor forming step, a resistor layer forming step, and a wiring layer forming step, A method for manufacturing a Josephson integrated circuit (an integrated circuit having a Josephson junction as a circuit element) having an on-chip capacitor, the capacitor formation step comprising adding niobium (Nb) as a superconducting ground plane on a wafer substrate. The first insulator is deposited on the entire surface of the wafer and processed to form the first superconducting interconnect, and then an insulator is deposited on the entire surface of the wafer with the same thickness as the first superconducting interconnect, and then flattened to form the first insulator. A pattern is formed, and then a niobium oxide film (Nb2O
5) and then a third layer defining the area of the capacitor.
An insulator pattern is formed, and then a superconductor is deposited on the entire surface of the wafer and processed to form a capacitor upper electrode, which is a second superconducting wiring.The resistor layer forming step is as follows: A resistor layer is deposited on the entire surface of the wafer, processed to form resistor wiring, and then a fifth insulator pattern is formed as a protective layer for the resistor wiring against etching, and the wiring layer forming step A first contact hole is formed by etching the insulating layer on top of the first superconducting interconnect to make an electrical connection between the first superconducting interconnect and the third superconducting interconnect to be formed next. and then depositing superconductor over the entire wafer and processing it into a third superconducting interconnect, depositing an insulator the thickness of the third superconducting interconnect over the entire wafer,
A sixth insulator pattern is formed by planarization, and then a junction lower electrode, a fifth superconducting wiring, a junction tunnel barrier layer, and a junction upper part, which is a sixth superconducting wiring, are formed thereon. After forming a three-layer bonding structure consisting of electrodes, a seventh insulator pattern is formed by flattening and bonding, and then a third superconducting wiring and a seventh superconducting layer to be formed next are formed. etching a second contact hole in the seventh insulating layer for electrical connection with the conductive wiring;
A superconductor is deposited over the entire surface of the wafer and processed to form a seventh superconducting interconnect.

[0009] Furthermore, the film thickness of the second superconducting wiring is the sum of the film thickness of the third insulator and the film thickness of the fourth insulator to be formed next, and in addition, the film thickness of the resistor wiring After etching, an insulator is deposited on the entire surface of the wafer by the thickness of the resistor wiring and flattened to form a fourth insulator pattern, and in addition, a fifth insulator pattern is formed. After forming, the fourth insulating layer is etched to form a third contact hole for electrically connecting the second superconducting wiring to the third superconducting wiring to be formed next. .

[0010] After forming the sixth insulator pattern, superconductor is deposited on the entire surface of the wafer to the depth of the first contact hole and processed to cover the third contact hole. This forms the fourth superconducting wiring.

[0011]

Since the LCR circuit is reliably formed on-chip with the Josephson element, parasitic inductance, capacitance, and resistance are not generated at their bonding portions.

[0012] Furthermore, the LCR circuit will be formed of a superconducting integrated circuit. Due to the Meissner effect of the superconducting ground plane, the inductance of normal wiring decreases,
By forming a meandering inductor where the superconducting ground plane is removed, the inductor setting becomes more lumped. Since normal wiring becomes superconducting, the only resistance is an artificially set pure resistance, and the resistance setting is almost like a lumped constant.

These effects facilitate the operation of the Josephson device at high frequencies in the microwave range. It also greatly contributes to improving the operating margin of the device.

[0014]

[Embodiments] Hereinafter, embodiments of the present invention will be described based on the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing Embodiment 1 of a Josephson integrated circuit according to the present invention. In the figure, in the method for manufacturing a Josephson integrated circuit according to the present invention, as a first step, a superconducting ground plane (GND plane) is formed on a wafer substrate using niobium (
Nb) was deposited to a thickness of 500 nm over the entire surface, patterned with a resist, and processed by etching to form the first superconducting wiring (S1) 1, and Si was deposited on top of it without removing the resist.
After depositing an insulator such as O2 on the entire surface of the wafer to the same thickness of 500 nm as the first superconducting wiring (S1) 1, lift
By planarizing off the first insulator pattern (I
1) 9 is formed, and then a second insulator pattern (I2) is formed as a dielectric layer of the capacitor on the niobium surface by anodization.
) A niobium oxide film (Nb2O5) having a thickness of 35 nm was formed.

As a second step, after patterning the niobium oxide film, which will become the second insulator pattern 10, with a resist, an insulator such as SiO2 is deposited over the entire surface of the wafer to a thickness of 200 nm.
A third insulator pattern (I3) 11 defining the area of the capacitor was formed by depositing and lifting off.

As the third step, a superconductor such as niobium is deposited to a thickness of 250 nm on the entire surface of the wafer, patterned with resist, and then etched to form the capacitor upper electrode, which is the second superconducting wiring (S2) 2. Formed.

As a fourth step, a resistor layer made of molybdenum (Mo) or the like was deposited to a thickness of 80 nm over the entire surface of the wafer, patterned with a resist, and processed by etching to form a resistor wiring (R) 8.

As the fifth step, after patterning with resist, an insulator such as SiO2 is applied to the entire surface of the wafer to a thickness of 60 nm.
By depositing and lifting off, a fifth insulator pattern (I5) 13 was formed which would serve as a protective layer for the resistor wiring (R) 8 against etching.

As the sixth step, after patterning with resist, the insulator layer on the top of the first superconducting wiring (S1) 1 is taper-etched to form the first superconducting wiring (S1).
A first contact hole (GBC hole) is formed to make an electrical connection between the first contact hole 1 and the third superconducting wiring (S3) 3 to be formed next.

In the seventh step, a superconductor such as niobium is deposited to a thickness of 350 nm over the entire surface of the wafer, patterned with resist, and processed by etching to form the third superconducting interconnect (S3
) 3, deposit an insulator such as SiO2 on the entire surface of the wafer to a thickness of 350 nm for the third superconducting wiring (S3) 3 without removing the resist, and perform lift-off planarization to form a sixth insulator. A body pattern (I6) 14 was formed.

As the eighth step, a 150 nm junction lower electrode 10, which is the fifth superconducting wiring (S5) 5, is formed thereon.
After forming a three-layer junction structure consisting of a 300 nm junction tunnel barrier layer (J) 16 and a 300 nm junction upper electrode, which is the sixth superconducting wiring (S6) 6, it is planarized and bonded by an etch-back method. Then, a seventh insulator pattern (I7) 15 was formed.

As the ninth step, the third superconducting wiring (S
3) In order to make an electrical connection between 3 and the seventh superconducting wiring (S7) 7 to be formed next, a second contact hole (BCC hole) is formed in the seventh insulating layer (I7) 15 by taper etching. ) was formed.

As the tenth step, a superconductor such as niobium is deposited to a thickness of 400 nm over the entire surface of the wafer, patterned with resist, and processed by etching to form the seventh superconducting interconnect (
S7) 7 was formed.

By the above method, the capacitor could be easily and compactly incorporated into the element structure of the Josephson integrated circuit, and both the Josephson element and the LCR circuit operated normally.

(Embodiment 2) FIG. 2 is a sectional view showing Embodiment 2 of the present invention. In this example, as shown in FIG. 2, the film thickness of the second superconducting wiring (S2) 2 is
3) After forming the resistor wiring (R) 8, the total thickness of the fourth insulator (I4) 12 to be formed next is 280 nm, and the resist is removed. Instead, an insulator such as SiO2 is deposited on the entire surface of the wafer to a thickness of 80 nm for the resistor wiring, and then lifted off to form the fourth insulator pattern (I4) 12.
Further, a fifth insulator pattern (I5) 13 is formed.
After forming and patterning with resist, the fourth insulating layer (I4) 12 is taper etched to form the second superconducting wiring (S2) 2 and the third superconducting wiring (S2) to be formed next.
3) A third contact hole (EBC hole) for electrical connection with 3 was formed.

As a result of the lift-off and flattening of the resistor wiring, the level difference when forming the upper wiring is reduced.
Leakage between lines and between layers due to differences in base material has been reduced. Moreover, the insulating layer interposed between the first superconducting wiring 1 and the third superconducting wiring 3 is now two layers, and the insulation between the wiring 1 and the wiring 3 is significantly improved. In addition, the second superconducting wiring 2 and the third
The contact resistance with the superconducting wiring 3 has disappeared. This is considered to be because the resistor no longer diffuses into the second superconducting wiring.

(Embodiment 3) FIG. 3 is a sectional view showing Embodiment 3 of the present invention. In this embodiment, as shown in FIG.
After forming an insulator pattern (I6) 14, a superconductor such as niobium is deposited on the entire surface of the wafer to a depth of 315 nm in the first contact hole GBC, patterned with resist, and etched. Contact
The fourth superconducting wiring (S4) covers the hole (GBC).
) 4 was formed.

As a result, the flatness of the base when planarizing the Josephson junction was significantly improved, and the reliability of the Josephson junction planarization and cueing process was significantly improved. In addition, the wiring 4 exhibited an effect of protecting the wiring 3 from damage caused by cleaning and etching when forming the wiring 5 at the stepped portion of the GBC hole, and also had an effect of preventing disconnection of the wiring 3.

[0030]

As described above, by the method of the present invention, an LCR circuit can be reliably formed on-chip with a Josephson element. Therefore, parasitic inductance, capacitance, and resistance are no longer generated at the bonding portion between the LRC circuit and the normal Josephson element.

[0031] Furthermore, LCR circuits have been formed using superconducting integrated circuits. The Meissner effect of the superconducting ground plane lowers the inductance of regular wiring, and by forming a meandering inductor where the superconducting ground plane is removed, the inductor setting becomes more lumped. Since ordinary wiring becomes superconducting, the only resistance is an artificially set pure resistance, and the resistance setting is almost a lumped constant.

These effects facilitate the operation of the Josephson device at high frequencies in the microwave range. It also greatly contributed to improving the operating margin of devices. Therefore, the present invention greatly contributes to the development of Josephson integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an element structure in Example 1 of the present invention.

FIG. 2 is a sectional view showing an element structure in Example 2 of the present invention.

FIG. 3 is a cross-sectional view showing an element structure in Example 3 of the present invention.

[Explanation of symbols]

1 First superconducting wiring (S1) 2 Second superconducting wiring which is the upper electrode of the capacitor (
S2) 3 Third superconducting wiring (S3) 4 Fourth superconducting wiring (S4) 5 Fifth superconducting wiring (S5) which is the lower electrode of the junction
6. Sixth superconducting wiring (S6) which is the upper electrode of the junction
7 Seventh superconducting wiring (S7) 8 Resistor wiring (R) 9 First insulating pattern (I1) 10 Second insulating pattern made of niobium anodic oxide film (I2)

Claims (3)

[Claims] 1. A method for turning on and off a capacitor, which includes a capacitor formation step, a resistor layer formation step, and a wiring layer formation step.
A method for manufacturing a Josephson integrated circuit (an integrated circuit having a Josephson junction as a circuit element) in the form of a chip, in which the capacitor formation step involves depositing niobium (Nb) over the entire surface of a wafer substrate as a superconducting ground plane. , processed to form a first superconducting wiring, depositing an insulator on the entire surface of the wafer with the same thickness as the first superconducting wiring, and then flattening it to form a first insulating pattern. Next, a niobium oxide film (Nb2O5), which will serve as the second insulator pattern as the dielectric layer of the capacitor, is formed on the niobium surface by anodic oxidation, and then a third insulator pattern that defines the area of the capacitor is formed. Next, a superconductor is deposited on the entire surface of the wafer and processed to form the capacitor upper electrode, which is the second superconducting wiring. A fifth insulator pattern is deposited and processed to form a resistor wiring, and then a fifth insulator pattern is formed, which serves as a protective layer for the resistor wiring against etching. etching the insulator layer on top of the conductive interconnect to form a first contact hole for electrical connection between the first superconducting interconnect and a third superconducting interconnect to be subsequently formed; A superconductor is deposited on the entire surface of the wafer and processed to form a third superconducting wire, and an insulator is deposited on the entire surface of the wafer by the thickness of the third superconducting wire and flattened to form a sixth insulator pattern. Then, after forming thereon a three-layer junction structure consisting of a junction lower electrode as a fifth superconducting wiring, a junction tunnel/barrier layer, and a junction upper electrode as a sixth superconducting wiring, A seventh insulator pattern is formed by flattening and positioning the junction, and then a seventh insulator pattern is formed to establish an electrical connection between the third superconducting wiring and the seventh superconducting wiring to be formed next. A second contact hole is formed by etching in the insulating layer of the wafer, and then a superconductor is deposited on the entire surface of the wafer and processed to form a seventh superconducting wiring. A method for manufacturing integrated circuits. 2. The film thickness of the second superconducting wiring is the sum of the film thickness of the third insulator and the film thickness of the fourth insulator formed next, and in addition, the film thickness of the resistor wiring After etching, an insulator is deposited on the entire surface of the wafer by the thickness of the resistor wiring and flattened to form a fourth insulator pattern, and in addition, a fifth insulator pattern is formed. After the formation, the fourth insulating layer is etched to form a third contact hole for electrically connecting the second superconducting interconnect and a third superconducting interconnect to be formed next. A method of manufacturing a Josephson integrated circuit according to claim 1. 3. After forming the sixth insulator pattern,
A claim characterized in that a superconductor is deposited on the entire surface of the wafer to a depth of the first contact hole and processed to form a fourth superconducting wiring so as to cover the third contact hole. 2. The method for manufacturing a Josephson integrated circuit according to 2.