JPH04267445A - Memory controller - Google Patents

Abstract

PURPOSE:To allow a master to access a memory with higher response speed than that of the master and to allow the memory and the master to be synchronized with each other so as to enable data processing by making a memory cycle equal to the speed notified by the master. CONSTITUTION:A table ROM22 to which an n-bit parallel identification signal 21 is inputted is provided, and the identification signal 21 which serves as a signal informing of access by a master 16 is outputted simultaneously with the access. When the identification signal is inputted to the table ROM22, first count data 23 in the m-bit construction and second count data 24 in the m'-bit construction are outputted in resonse. The first count data 23 are inputted to a first counter 25 controlling the period of an RAS; while the second count data 24 are inputted to the second counter 26 controlling the timing of a CAS. An access signal is supplied to the load terminal of the first and second counters 25 and 26 as well as the set terminal of an RAS flag circuit 27.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a memory control device that controls memory, and more specifically, the present invention relates to a memory control device that controls memory, and more specifically, a plurality of masters such as a CPU (central processing unit) and a DMA (direct memory access) as memory access requesters. The present invention relates to a memory control device that can efficiently access memory.

0002

2. Description of the Related Art It is possible to form a complex system by connecting several additional devices to one basic device as necessary, such as when a sorter or automatic document feeder is attached to the main body of a copying machine. It is widely practiced in various fields. In such a case, if the master on the additional device side can utilize the memory provided in the basic device, the system will of course be operated smoothly and effectively.

By the way, data transmission and reception between a memory and a master is normally performed asynchronously.

FIG. 4 shows the timing control between the two devices in this case. As shown in FIG. 5A, when the master accesses the memory at time t1, processing such as writing data to the memory starts from this time. When such processing from the master side is completed, a response signal is transmitted from the memory at time t2, as shown in FIG. The master receives this response signal and sends out a response confirmation signal at time t3. The memory receives this response confirmation signal, and the series of controls ends at time t4.

[0005]

[Problem to be solved by the invention] In this way, conventionally,
When multiple masters with different access speeds are connected to a memory, control for writing and reading data is performed asynchronously so that the memory can accommodate each of these masters individually.

[0006] Therefore, at the end of each data processing task, a procedure is required in which the memory side sends a response signal, the master side confirms this, and sends the signal back to the memory. There was a problem that the time required for the work became long.

Furthermore, in conventional memory systems, there is a problem in that a master whose response speed is slower than the memory to be accessed cannot write data to the memory or read necessary data.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory control device that allows a master to access a memory having a faster response speed.

Another object of the present invention is to provide a memory control device that allows a memory and a master to perform data processing in synchronization.

0010

[Means for Solving the Problems] The invention according to claim 1 includes memory control means connected to the memory and controlling the memory;
When each master that accesses this memory transmits an identification signal indicating the access speed, an identification signal receiving means that receives this and the corresponding master at a speed according to the received identification signal is transmitted. The memory control device is provided with a memory cycle setting means for setting a memory cycle.

That is, in the invention as claimed in claim 1, the master sends an identification signal representing the access speed to the memory, and the memory side sets a memory cycle suitable for the master, thereby achieving the above-mentioned object. achieve.

In the invention as claimed in claim 2, the memory control means is connected to the memory and controls the memory, and when the master accessing the memory transmits an identification signal representing its own access speed at the time of access, The memory control device is provided with an identification signal receiving means for receiving the identification signal, and a memory cycle starting means for starting a memory cycle with the master according to the identification signal starting from the time of reception of the identification signal.

In other words, in the invention as claimed in claim 2, the master sends an identification signal indicating the access speed to the memory, and when the memory side receives this signal, a memory cycle suitable for the master starts. and achieve the above objectives.

[0014]

EXAMPLES The present invention will be explained in detail with reference to Examples below.

FIG. 2 shows a memory system to which a memory control device according to an embodiment of the present invention is applied. All or part of the data bus 11, address bus 12, and control bus 13 of this memory system includes a memory 14 for storing data, a memory control device 15 of this embodiment, and first to Nth masters 16-1. ,...,16-
N is connected. Here, the first to Nth masters 16-
1, . . . , 16-N refer to, for example, a CPU or a DMA. Note that in this embodiment, a DRAM (dynamic random access memory) is used as the memory 14.

FIG. 1 shows an outline of the configuration of the memory control device of this embodiment. The memory control device 15 is
Table R for inputting the n-bit parallel identification signal 21
It is equipped with an OM (read only memory) 22. Here, the identification signal 21 is the master 16 to be accessed.
This is a signal that informs the access speed of the data, and is output simultaneously with the access.

This table ROM 22 stores data corresponding to 2n types of access speeds. When the identification signal 21 is input to the table ROM 22, corresponding first count data 23 having an m-bit configuration and second count data 24 having an m'-bit configuration are output. The first count data 23 is R
A first counter 25 for controlling the cycle of AS (row address strobe), and second count data 24
are respectively input to a second counter 26 for controlling the timing of CAS (column address strobe). The load terminals of the first and second counters 25 and 26 and the set terminal of the RAS flag circuit 27 are supplied with an access signal 29 for setting the start of a cycle.

The carry signal 31 output from the carry terminal of the first counter is input to the clear terminal of the RAS flag circuit 27 to turn off the RAS flag. Further, the carry signal 32 output from the carry terminal of the second counter 26 is input to the set terminal of the CAS flag circuit 33 to turn on the CAS flag. This CAS flag is similarly turned off by the carry signal 31. From the RAS flag circuit 27, the RAS
The signal 35 and the CAS signal 36 are output from the CAS flag circuit 33, respectively.

The operation of the memory control device having such a configuration will be explained with reference to FIG. For example, assume that the first master 16-1 accesses the memory 14. In this case, the first master 16-1 outputs an identification signal 21 representing its own access speed at the same time it accesses the memory 14.

The table ROM 22, which has received the identification signal 21 at time t11, outputs first count data 23 and second count data 24, each having a count value corresponding to the access speed of the first master 16-1. do. The first count data 23 is supplied to a first counter 25 and its count value is preset. Similarly, the second
The count data 24 is supplied to a second counter 26 and its count value is preset. Also, at the same time t11, the access signal 29 is transmitted to the RAS flag circuit 27.
as shown in FIG. 3(a), negative logic RAS
Let the signal (RAS*) fall.

The first counter 25 and the second counter 26 count preset count values in synchronization with a clock signal (not shown). Then, first, time t1
2, the second counter 26 counts up to a preset count value and outputs a carry signal 32. Carry signal 32
sets the CAS flag circuit 33 and causes the negative logic CAS signal (CAS*) to fall as shown in FIG. 3(b).

Thereafter, the first counter 25 counts up to the preset count value and outputs a carry signal 31 at time t13. This carry signal 31 is RAS
The signal is input to the flag circuit 27 and the CAS flag circuit 33 to turn off these flags. As a result, both the RAS signal (RAS*) and the CAS signal (CAS*) fall.

In this way, in the memory control device of this embodiment, the RAS signal and the CAS signal are generated at timings corresponding to the access speed of the master 16. That is, the memory control device 15 responds according to the speed of the master 16 that has accessed it.

As described above, in the memory control device of this embodiment, each master 16 issues a flag indicating its own access speed, and the memory control device 15 determines this flag and adjusts the speed of the memory control device 15 to the speed of the master 16. . Therefore, the memory 14 can be shared even if the response speeds of these masters 16-1 to 16-N do not match.

[0025] In the embodiment, the memory control device starts the memory cycle using the reception time of the identification signal sent from the master as the starting point, but it is also possible to start the memory cycle using the time other than this as the starting point. good.

[0026]

As described above, according to the present invention, memory cycles can be adjusted to the speed notified by the master side. Therefore, even a relatively old master in an existing memory system can access the memory without replacing it, and an economical memory system can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory control device according to an embodiment.

FIG. 2 is a system configuration diagram of a memory system using the memory control device of this embodiment.

FIG. 3 is a timing diagram showing temporal changes in the RAS signal and CAS signal in this embodiment.

FIG. 4 is a timing diagram showing an example of communication between a conventional master and a memory.

[Explanation of symbols]

14 Memory 16-1 First master 16-2 Second master 15 Memory control device 23 Working memory

Claims (2)

[Claims] 1. Memory control means that is connected to the memory and controls it, and identification signal receiving means that receives an identification signal indicating the speed of access when each master accessing the memory transmits the identification signal. and memory cycle setting means for setting a memory cycle with a corresponding master at a speed according to a received identification signal. 2. Memory control means that is connected to the memory and controls it, and an identification signal receiver that receives an identification signal indicating its own access speed when a master accessing the memory transmits an identification signal when accessing the memory. means and
1. A memory control device comprising: memory cycle starting means for starting a memory cycle between the master and the master according to the identification signal, starting from the time of reception of the identification signal.