JPH04266035A - Structure for mounting semiconductor device - Google Patents
Structure for mounting semiconductor deviceInfo
- Publication number
- JPH04266035A JPH04266035A JP3026114A JP2611491A JPH04266035A JP H04266035 A JPH04266035 A JP H04266035A JP 3026114 A JP3026114 A JP 3026114A JP 2611491 A JP2611491 A JP 2611491A JP H04266035 A JPH04266035 A JP H04266035A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead
- mounting structure
- semiconductor device
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052737 gold Inorganic materials 0.000 claims abstract description 9
- 239000010931 gold Substances 0.000 claims abstract description 9
- 239000007772 electrode material Substances 0.000 claims abstract description 4
- 230000002265 prevention Effects 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 abstract description 7
- 238000005476 soldering Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical class [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 2
- 229910000846 In alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体素子の実装構造体
に関し、特にコンピューター，ビデオ，テレビ等あらゆ
る電子機器に利用できる、半導体素子の実装構造体に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting structure, and more particularly to a semiconductor element mounting structure that can be used in all kinds of electronic equipment such as computers, videos, and televisions.
【０００２】0002
【従来の技術】近年、コンピューター等の電子機器の可
搬性および利便性に対する要求が益々強まり、よりポー
タブルで高性能なコンピューター等の電子機器の出現が
期待されている。その中で、はんだバンプ等突起電極を
用いたフリップチップ実装法は、高性能で高密度の実装
方法として注目を浴びている。2. Description of the Related Art In recent years, there has been an increasing demand for the portability and convenience of electronic equipment such as computers, and the emergence of more portable and high-performance electronic equipment such as computers is expected. Among these, the flip-chip mounting method using protruding electrodes such as solder bumps is attracting attention as a high-performance and high-density mounting method.
【０００３】フリップチップ実装法で実装した実装構造
体として、半導体素子の取り出し電極にバリア層を形成
した後、はんだバンプを蒸着法，メッキ法等で形成した
ものがよく知られているが、この場合、半導体素子の取
り出し電極にバリア層を形成するため、工程が複雑にな
る。また、半導体ウエハプロセス中でこれを形成するの
で、半導体メーカーでないとこのような処理ができない
。そのために、半導体メーカーのこのような処理をして
いる特定の半導体素子のみにしか利用できず、アセンブ
リメーカーが自由に半導体素子を選んで実装することが
できないという問題がある。A well-known mounting structure mounted using the flip-chip mounting method is one in which a barrier layer is formed on the lead-out electrode of a semiconductor element, and then solder bumps are formed using a vapor deposition method, a plating method, etc. In this case, the process becomes complicated because a barrier layer is formed on the lead-out electrode of the semiconductor element. Furthermore, since this is formed during the semiconductor wafer process, only semiconductor manufacturers can perform such processing. Therefore, there is a problem in that it can only be used for specific semiconductor devices that are processed in this way by semiconductor manufacturers, and assembly manufacturers cannot freely select and mount semiconductor devices.
【０００４】そこで、半導体素子の取り出し電極にバリ
ア層を形成しないフリップチップ実装構造体が提案され
ている。その中の一つとして、図２に示すように、半導
体素子１の取り出し電極２に直接金バンプ３を形成し、
回路基板４の配線電極５にはんだバンプ６を形成し、金
バンプ３とはんだバンプ６を接続するフリップチップ実
装構造体がある。尚、半導体素子１の取り出し電極２以
外の部分には保護膜７が形成されている。[0004] Therefore, a flip-chip mounting structure in which a barrier layer is not formed on the lead-out electrode of a semiconductor element has been proposed. As one of them, as shown in FIG. 2, gold bumps 3 are formed directly on the extraction electrode 2 of the semiconductor element 1,
There is a flip chip mounting structure in which solder bumps 6 are formed on wiring electrodes 5 of a circuit board 4 and gold bumps 3 and solder bumps 6 are connected. Note that a protective film 7 is formed on a portion of the semiconductor element 1 other than the lead-out electrode 2.
【０００５】[0005]
【発明が解決しようとする課題】上記従来の半導体素子
の実装構造体は、半導体素子１の取り出し電極２にバリ
ア層を形成していないため、あらゆる半導体素子が利用
できるが、信頼性が低いという問題があった。特に、ヒ
ートショックによる熱応力によってバンプに歪が生じ、
破断することが最大の問題であった。[Problems to be Solved by the Invention] The conventional semiconductor element mounting structure described above does not have a barrier layer formed on the lead-out electrode 2 of the semiconductor element 1, so any semiconductor element can be used, but the reliability is low. There was a problem. In particular, thermal stress caused by heat shock causes distortion in the bumps,
Breaking was the biggest problem.
【０００６】例えば、はんだバンプ６にすず−鉛合金、
回路基板４の配線電極５に銅を用いた場合、はんだ中の
すずと配線電極の銅が相互拡散し、銅−すず合金層を形
成するため鉛が偏析し、ヒートサイクル試験等を行なっ
た場合、時間がたつと偏析した鉛の部分で破断するとい
う現象が起こる。本発明はこのような課題を解決するも
ので、信頼性の高い半導体素子の実装構造体を提供する
ことを目的とする。For example, the solder bumps 6 are made of tin-lead alloy,
When copper is used for the wiring electrodes 5 of the circuit board 4, the tin in the solder and the copper of the wiring electrodes interdiffuse, forming a copper-tin alloy layer, which causes lead to segregate, and when a heat cycle test etc. is performed. As time passes, a phenomenon occurs in which the lead breaks at the segregated part. The present invention solves these problems and aims to provide a highly reliable semiconductor element mounting structure.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体素子の実
装構造体は上記課題を解決するために、配線電極材料と
はんだの拡散防止層を、はんだバンプと回路基板の配線
電極との間に設けたものである。[Means for Solving the Problems] In order to solve the above problems, the semiconductor element mounting structure of the present invention provides a wiring electrode material and a solder diffusion prevention layer between the solder bumps and the wiring electrodes of the circuit board. It was established.
【０００８】[0008]
【作用】この構成により本発明の半導体素子の実装構造
体は、配線電極材料とはんだの拡散防止層を、はんだバ
ンプと回路基板の配線電極との間に設けたことにより、
配線電極中の銅と、はんだバンプ中の錫の相互拡散によ
り、銅−錫合金層の形成がなくなり、鉛が偏析し、温度
変化が繰り返された場合、時間がたつと、偏析した鉛の
部分で破断するという現象が起らないこととなる。[Function] With this configuration, the semiconductor element mounting structure of the present invention provides the wiring electrode material and the solder diffusion prevention layer between the solder bumps and the wiring electrodes of the circuit board.
Due to interdiffusion between copper in the wiring electrode and tin in the solder bump, the formation of a copper-tin alloy layer disappears, lead segregates, and if temperature changes are repeated, over time, the segregated lead portion This means that the phenomenon of breakage will not occur.
【０００９】[0009]
【実施例】以下、本発明の一実施例の半導体素子の実装
構造体について、図１を参照しながら説明する。同図に
おいて、１〜７は先に述べた従来例と全く同じであるの
で同一符号を付し説明を省略する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device mounting structure according to an embodiment of the present invention will be described below with reference to FIG. In the same figure, since 1 to 7 are completely the same as the conventional example described above, the same reference numerals are given and the explanation will be omitted.
【００１０】すなわち、まずバリア層が形成されていな
い通常の半導体素子１の取り出し電極２上に直接金バン
プ３を形成する。次に、セラミックを用いた回路基板４
の銅配線電極５上にニッケルを拡散防止層８として形成
し、その上にはんだバンプ６を形成する。そして半導体
素子１のパターン面を下向きにしてセラミックを用いた
回路基板４に向い合わせ、金バンプ３とはんだバンプ６
を接続し、はんだが溶融する温度にまで加熱してはんだ
バンプ６を溶融させ、金バンプ３とはんだバンプ６を結
合させた半導体素子の実装構造体を作製した。That is, first, gold bumps 3 are formed directly on the lead-out electrodes 2 of the normal semiconductor element 1 on which no barrier layer is formed. Next, a circuit board 4 using ceramic
Nickel is formed as a diffusion prevention layer 8 on the copper wiring electrode 5, and solder bumps 6 are formed thereon. Then, the patterned surface of the semiconductor element 1 is faced down to face the ceramic circuit board 4, and the gold bumps 3 and the solder bumps 6 are placed on the semiconductor element 1.
were connected and heated to a temperature at which the solder melts to melt the solder bumps 6, thereby producing a semiconductor element mounting structure in which the gold bumps 3 and the solder bumps 6 were bonded together.
【００１１】尚、本実施例では、はんだバンプ６にすず
−鉛系合金を使用したが、はんだバンプ６の材料は、イ
ンジウム系合金等、半導体素子１の取り出し電極２が溶
融しない温度で溶融するものであればよい。In this embodiment, a tin-lead alloy is used for the solder bumps 6, but the material of the solder bumps 6 may be an indium alloy or the like, which melts at a temperature that does not melt the lead electrode 2 of the semiconductor element 1. It is fine as long as it is something.
【００１２】また、拡散防止層８についても、銅とはん
だ材料の拡散を防止する役割をもつものであれば何でも
よい。Further, the diffusion prevention layer 8 may be any material as long as it has the role of preventing diffusion of copper and solder material.
【００１３】このような半導体素子の実装構造体に、耐
湿性を確保するために、半導体素子１とセラミックを用
いた回路基板４の隙間に熱硬化性樹脂を充填硬化した後
、ヒートショック試験、ＴＨＢ試験を行なった。このと
き用いた半導体素子１は、取り出し電極数２３個のＤＲ
ＡＭである。In order to ensure moisture resistance in such a semiconductor element mounting structure, after filling and hardening a thermosetting resin into the gap between the semiconductor element 1 and the ceramic circuit board 4, a heat shock test, A THB test was conducted. The semiconductor element 1 used at this time was a DR with 23 extraction electrodes.
It is AM.
【００１４】ヒートショック試験は、拡散防止層８を設
けていない従来の半導体素子の実装構造体と本実施例の
半導体素子の実装構造体とのそれぞれ２０個の半導体素
子１について、−５５℃〜１５０℃の条件で行なったと
ころ、５００サイクル時点で、従来の半導体素子の実装
構造体は２０個中８個しか正常に動作しなかったにもか
かわらず、本実施例の半導体素子の実装構造体は２０個
全数が正常に動作した。The heat shock test was carried out on 20 semiconductor elements 1 of the conventional semiconductor element mounting structure without the diffusion prevention layer 8 and the semiconductor element mounting structure of this embodiment at temperatures ranging from -55°C to When conducted under the condition of 150°C, only 8 out of 20 conventional semiconductor element mounting structures operated normally after 500 cycles, but the semiconductor element mounting structure of this example did not. All 20 units worked normally.
【００１５】ＴＨＢ試験についても同様に、拡散防止層
８を設けていない従来の半導体素子の実装構造体と本実
施例の半導体素子の実装構造体とのそれぞれ２０個の半
導体素子１について、温度８５℃、湿度８５％の環境で
半導体素子１の電源端子と接地端子との間に５Ｖの動作
電圧を印加しながら保持したところ、１０００時間の時
点で、従来の半導体素子の実装構造体は２０個中１８個
しか正常に動作しなかったにもかかわらず、実施例の半
導体素子の実装構造体は２０個全体が正常に動作した。Similarly, regarding the THB test, 20 semiconductor elements 1 of the conventional semiconductor element mounting structure without the diffusion prevention layer 8 and the semiconductor element mounting structure of this embodiment were tested at a temperature of 85%. When an operating voltage of 5V was applied between the power supply terminal and the ground terminal of the semiconductor element 1 in an environment of 85% humidity and 85% humidity, after 1000 hours, the number of conventional semiconductor element mounting structures was 20. Although only 18 of them operated normally, all 20 of the semiconductor element mounting structures of the example operated normally.
【００１６】[0016]
【発明の効果】以上の実施例の説明で明らかなように本
発明の半導体素子の実装構造体によれば、拡散防止層を
、はんだバンプと回路基板の配線電極との間に設けるこ
とにより、半導体素子の取り出し電極に直接、金バンプ
を形成し、これにはんだバンプを形成して回路基板の配
線電極と接続をとった半導体素子の実装構造体の信頼性
を著しく高めることができる。これにより、バリア層を
設けていない半導体素子のフリップチップ実装が可能に
なり、このような半導体素子の実装構造体の製品化を実
現できる。As is clear from the above description of the embodiments, according to the semiconductor element mounting structure of the present invention, by providing a diffusion prevention layer between the solder bumps and the wiring electrodes of the circuit board, The reliability of a semiconductor element mounting structure in which gold bumps are directly formed on the lead-out electrodes of the semiconductor element, and solder bumps are formed thereon and connected to the wiring electrodes of the circuit board can be significantly improved. This makes it possible to perform flip-chip mounting of a semiconductor element without a barrier layer, and to commercialize such a semiconductor element mounting structure.
【図１】本発明の一実施例の半導体素子の実装構造体の
断面図FIG. 1 is a cross-sectional view of a semiconductor element mounting structure according to an embodiment of the present invention.
【図２】従来の半導体素子の実装構造体の断面図[Figure 2] Cross-sectional view of a conventional semiconductor element mounting structure
１ 半導体素子 ２ 取り出し電極 ３ 金バンプ ４ 回路基板 ５ 配線電極 ６ はんだバンプ ８ 拡散防止層 1 Semiconductor device 2 Extraction electrode 3 Gold bump 4 Circuit board 5 Wiring electrode 6 Solder bumps 8. Diffusion prevention layer
Claims (1)
て、回路基板の配線電極に前記半導体素子の取り出し電
極を接続するとき、その接続部が、前記回路基板側から
順次、配線電極、配線電極材料とはんだの拡散防止層、
はんだバンプ、金バンプ、前記半導体素子の取り出し電
極で構成される半導体素子の実装構造体。1. When connecting the lead electrode of the semiconductor element to the wiring electrode of the circuit board with the pattern surface of the semiconductor element facing downward, the connecting portion is connected to the wiring electrode and the wiring electrode material in order from the circuit board side. and solder diffusion prevention layer,
A semiconductor element mounting structure comprising solder bumps, gold bumps, and lead-out electrodes of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3026114A JPH04266035A (en) | 1991-02-20 | 1991-02-20 | Structure for mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3026114A JPH04266035A (en) | 1991-02-20 | 1991-02-20 | Structure for mounting semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04266035A true JPH04266035A (en) | 1992-09-22 |
Family
ID=12184558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3026114A Pending JPH04266035A (en) | 1991-02-20 | 1991-02-20 | Structure for mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04266035A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148495A (en) * | 1994-11-25 | 1996-06-07 | Fujitsu Ltd | Semiconductor device, manufacture thereof, and adhesion evaluation method of semiconductor device bump |
| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
-
1991
- 1991-02-20 JP JP3026114A patent/JPH04266035A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148495A (en) * | 1994-11-25 | 1996-06-07 | Fujitsu Ltd | Semiconductor device, manufacture thereof, and adhesion evaluation method of semiconductor device bump |
| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6344690B1 (en) | 1997-09-08 | 2002-02-05 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6495441B2 (en) | 1997-09-08 | 2002-12-17 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6786385B1 (en) | 1997-09-08 | 2004-09-07 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
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