JPH0426573B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In the carrier wave pull-in auxiliary circuit, at the time of non-synchronization,
By alternately applying a 3-value carrier wave control signal and a 3-value sweeper signal to the voltage controlled oscillator,
Although resynchronization of the carrier wave regeneration circuit can be easily performed, since this circuit is entirely composed of digital circuits, variations in characteristics are reduced and it is easy to integrate into an IC.

[Industrial application field]

The present invention relates to an improvement in a carrier wave pull-in auxiliary circuit used in a digital multiplex radio demodulator.

FIG. 3 is a block diagram of a digital multiplex radio demodulator, and FIG. 4 is an explanatory diagram of the operation of FIG. 3.

Therefore, the operation shown in FIG. 3 will be explained with reference to FIG. In Figure 3, added to terminal IN,
For example, 64 orthogonal amplitude modulated waves are synchronously detected by the quadrature detector 1 using a regenerated carrier wave from a voltage controlled oscillator (hereinafter abbreviated as VCO) 45, and Ich and Qch baseband signals are obtained. This baseband signal is converted into a digital signal by analog/digital converters (hereinafter abbreviated as A/D converter) 2 and 3, and is sent to the outside as OUT-1 and OUT-2, as well as a phase error signal. It is added to a carrier wave regeneration circuit (hereinafter abbreviated as CR circuit) 4.

For example, when all the signal points shown in Figure 4 rotate in the direction of the arrow, looking at the signal point E, it is 1 because it is above the level E _I , 0 because it is to the left of the level E _Q , and the level D _I Since it is above 1, level D _Q
Since it is on the right side of
Added to 41 and 42. Therefore, this output 1,
0 is subtracted in an analog manner by the subtracter 43, and +1 is output as shown in Fig. 4. This is added to the VCO 45 through the low-pass filter 44 so that the output of the subtracter 43 becomes 0. The oscillation frequency is controlled.

This control method is +1, as shown in Figure 4-.
Control the VCO45 with a three-value control signal of 0, -1,
For example, +1 indicates that the oscillation frequency is lowered, 0 indicates that the oscillation frequency remains unchanged, and -1 indicates that the oscillation frequency is increased.

Here, the minimum bandwidth of the low-pass filter 44 is determined based on the stability of the radio frequency, but in order to improve the error rate, it is desirable to narrow this bandwidth to reduce output jitter of the VCO.

However, the quadrature detector 1, A/D converters 2 and 3,
A phase-locked loop (hereinafter referred to as
When the PLL (abbreviated as PLL) becomes disconnected, it becomes difficult to resynchronize the CR circuit, so a carrier wave pull-in auxiliary circuit is used to forcibly sweep the oscillation frequency of the VCO, but in order to miniaturize the device, It is desired that the configuration be such that it can be integrated into an IC.

[Conventional technology]

FIG. 5 shows a block diagram of a conventional example of the carrier wave pull-in assist method.

In the figure, when the PLL is disconnected and the CR circuit 4 becomes unsynchronized, the oscillation frequency of the VCO 45 is swept by, for example, a sawtooth wave sent from the low frequency oscillator 5 to enable resynchronization. Note that once the CR circuit is resynchronized, the output of the low frequency oscillator 5 is cut off and the synchronized state is maintained by the PLL.

[Problem that the invention seeks to solve]

However, because low-frequency oscillators oscillate at very low frequencies, for example several tens of Hz, it is difficult to always obtain the same characteristics due to deviations in the characteristics of the elements.
There is also the problem that it is difficult to convert it into an IC.

[Means for solving problems]

As shown in Fig. 1, the above problem is caused by the digital multiplex radio carrier regeneration circuit including an N frequency divider circuit 6 that divides the clock frequency by N, and a sweep pulse generated using the output of the N frequency divider circuit. When the sweep pulse generation circuit 8 and the carrier regeneration circuit are asynchronous,
This problem can be solved by the carrier wave pull-in auxiliary circuit of the present invention which includes a selector circuit 7 that alternately selects the phase error signal and the sweep pulse and applies them to the subtracter 43 using the output of the N frequency divider circuit.

[Effect]

In the present invention, a 3-value carrier control signal and a 3-value sweeper signal are alternately applied to the VCO via the low-pass filter 44 during non-synchronization, and the oscillation frequency thereof is swept to perform a pull-in search.

That is, the phase error signals from the EX-OR circuits 42 and 41 and the sweep pulse obtained by the sweep pulse generation circuit 8 using the frequency of the clock divided by N are sent to terminal C and terminal C of the selectors 72 and 71, respectively. In addition to D, terminal C and terminal D are alternately selected using a clock obtained by dividing this selector by N.

Therefore, the phase error signal and the sweep pulse are alternately converted into a three-value carrier control signal and a three-value sweeper signal by a subtracter 43, and are applied to the VCO via a low-pass filter 44, so that the VCO sweeps the oscillation frequency. However, since the pull-in search is performed periodically using the carrier wave control signal, resynchronization can be easily performed.

Note that since this circuit is entirely composed of digital circuits, there is little variation in characteristics and it can be integrated into an IC.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of FIG. Note that the same reference numerals indicate the same objects throughout the figures.

Therefore, the operation shown in FIG. 1 will be explained with reference to FIG.

(1) When the CR circuit is out of synchronization In Fig. 1, the synchronization alarm in the low state (L) is applied to the selector 73, so the terminal D is connected to the output side, and the clock whose frequency has been divided by N by the N frequency divider circuit 6 is applied to the selector 73. The selectors 71 and 72 are driven through the selector 73.

Furthermore, the frequency of the N-divided clock is further divided by 2 by the 2-frequency divider circuit 81 and added to the 2-bit counter 82, so this is counted and the upper bit _Q1 and lower bit _Q0 are output. Q ₁ is selector 7
2 terminal D, Q ₀ and Q ₁ are connected to EX-OR circuit 83.
After -OR is taken, they are respectively added to the terminal D of the selector 71 (see FIG. 2).

On the other hand, the terminals C of the selectors 72 and 71 have
Since the phase error signal shown in FIG. 4 whose value is determined every clock from the EX-OR circuits 42 and 41 is added, the two signals are alternately sent to the subtracter 43.
, and the output shown in FIG. 2 is obtained.

Here, part A is a ternary carrier control signal, and part B
The part is a three-value sweeper signal whose level changes from 0 → -1 → 0 → +1 → 0. When this signal is applied to the VCO through the low-pass filter 44, the signal shown in Fig. 2-
As shown in the figure, the oscillation frequency is swept, and resynchronization is attempted by periodically performing a pull-in search using the carrier wave control signal. Under the influence of the sweeper signal passed through the filter 44, the center frequency of the pull-in operation in the portion A changes. The period of the sweeper signal is N times the clock period, and by making it long enough, the change becomes gradual.
Does not interfere with retraction movement. Then, when the line condition improves and the center frequency of the pull-in operation comes close to the receiving frequency, the pull-in is performed, and when the pull-in is completed, the synchronization alarm becomes high (H).

(2) CR circuit synchronization When the CR circuit is synchronized, the synchronization alarm is in a high state, so a high state (H) is applied from the selector 73 to the selectors 72 and 71. Therefore, the selectors 72 and 71 select terminal C, and only the phase error signal is added to the subtracter 43 and converted into a three-value carrier control signal, and then passed through the low-pass filter 44.
Added to VCO.

〔Effect of the invention〕

As explained in detail above, since the carrier wave pull-in auxiliary circuit is composed of only digital circuits, there is little variation in characteristics and there is an effect that it can be easily integrated into an IC.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is a block diagram of a demodulator for digital multiplex radio, and Fig. 4 is an explanatory diagram of the operation of Fig. 3. , FIG. 5 shows a block diagram of a conventional example. In the figure, 4 is a carrier wave regeneration circuit, 6 is an N frequency divider circuit, 7 is a selector circuit, and 8 is a sweep pulse generation circuit.

Claims (1)

[Claims] 1. After the binary phase error signal from the analog/digital converter is converted into a ternary carrier wave control signal by a subtracter 43, it is sent to a voltage controlled oscillator via a low pass filter 44 and then sent to a regenerated carrier wave. The carrier wave regeneration circuit for digital multiplex radio that extracts the frequency of the clock includes an N frequency divider circuit 6 that divides the clock frequency by N, a sweep pulse generation circuit 8 that generates a sweep pulse using the output of the N frequency divider circuit, and the carrier wave regeneration circuit. When the circuit is asynchronous, a selector circuit 7 is added which alternately selects the phase error signal and the sweep pulse using the output of the N frequency divider circuit and applies the same to the subtracter 43. Retraction auxiliary circuit.