JPH04264635A - Measuring system for cpu occupied rate of program - Google Patents

Abstract

PURPOSE:To calculate the CPU occupied rate of a measured program which is considerably easily fixed to a specified execution level without the need of learning the load address of the measured program and without increasing the over head of an OS kernel part. CONSTITUTION:A counter 240 is provided in correspondence with the CPU execution level of the program and the counter corresponding to the execution level of an interrupted program fetched by an occupied rate measuring program which externally makes interruption at every interval is updated. Then, the corresponding CPU occupied rate of the program is obtained from a rate between the sum of the values of all the counters whose number is equal to that of the execution levels, and one value of the counter.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to a CPU for a specific program.
The present invention relates to a technique for calculating the occupancy rate, and in particular to a technique for calculating the CPU occupancy rate of a program with a specific execution right level in a system that distinguishes and uses a plurality of instruction execution rights as a CPU protection function.

0002

[Prior Art] Conventionally, this type of CPU occupancy calculation method involves knowing in advance the memory occupied address of the program to be measured, monitoring the execution address generated by the CPU externally, and calculating the occupied address of the program to be measured within a certain period of time. It was calculated by finding the passing ratio. Alternatively, it has been common practice to accumulate the absolute value of the CPU execution time allocated to the program to be measured in the core part (scheduler) of the system and calculate the proportion of the CPU execution time in a certain period of time.

0003

[Problem to be solved by the invention] The above-mentioned conventional CPU
In the former case, the occupancy rate calculation method requires knowing the load address of the program to be measured by some means, but in a relocatable system, it is impossible to know the load address of the program in advance. In the latter case, it is necessary to add a function to the scheduler section that reads the real-time timer between the time when control is passed to the program to be measured and the time when control is taken, calculates the difference, and adds up the difference, which has the disadvantage of reducing the performance of the scheduler. .

0004

[Means for Solving the Problems] The present invention provides a method for measuring the CPU occupancy rate of a program in a computer in which the CPU execution level of the program is one of a plurality of execution levels. The occupancy measurement program is started on the CPU by an external interrupt at every interval.
This occupancy measurement program retrieves the execution level of the interrupted program, updates one of the counters corresponding to the retrieved execution level, and calculates the ratio between the sum of all the values of the counters and the value of one of the counters. It is characterized by obtaining the CPU occupancy rate of the corresponding program.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIGS. 1 and 2 are diagrams showing the overall configuration of an embodiment of the present invention, and are a diagram showing a state in which interrupt processing ends and a diagram showing a state in which interrupt processing starts, respectively.

[0007] The program to be measured consists of its instruction section (CS1
) 100, data section (DS1) 110, and stack section (S
The task register (S1) is a type of HW register in the CPU, in which the memory start address of each part is stored in the task state table (TSS1) 130, and which indicates the address of the task state that the CPU is currently authorized to execute. TR)10 points to TSS1 (130).

[0008] Also, in this system, a task status table (TSS0) 230 is prepared for a startup program (composed of an instruction section 200, a data section 210, and a stack section 220) when an external CPU interrupt occurs. has been done. Book TS
S0 (230) points from the entry 301 corresponding to the interrupt of the interval timer 40 in the interrupt description table (IDT) 30 that stores the task status table group of the interrupt processing program prepared for each type of external interrupt of the CPU. has been done. Furthermore, the IDT30 is a type of HW register in the CPU.
It is pointed to by the DT address register (IDTR) 20.

The counter table (CNT) 240 is an area accessed by the instruction unit 200 and has entries for each type of CPU execution level possessed by the CPU. T.S.
According to FIG. 3, which details the information stored in S0 (230) or TSS1 (130), the offset is “2”.
The information from to "42" is a program-visible HW register value storage area of the CPU, and stores the HW register value set by the program having the current execution right of the CPU. Among these, the CS selector at offset "36" (details shown in FIG. 4) indicates the address of the instruction section, and a part of its contents (2 bits of the RPL section) indicates the CPU execution level. Therefore, in this example, C
There are four types of PU execution levels: "0" to "3". The BLP section with offset "0" indicates nesting information of a task status table, which will be described later, and points to the interrupted task status table.

Next, the operation of this embodiment when an interval timer interrupt occurs will be explained using FIG.

[0011] The interval timer 40, which is set in advance to generate an interrupt at extremely short regular intervals, keeps clocking in, and when the specified time (generally about 10 ms) has elapsed, the IDT is activated.
The task status table TSS0 (230) registered in the interval timer interrupt entry 301 in 30 is activated by the HW. In other words, the usage status of the HW register of the measurement target program (consisting of various resources pointed to by TSS1 (130)) that has been running up until now is all based on TSS1 (130).
) is stored internally in the format shown in Figure 3, and TR10 is the TSS
Point to 0 (230).

At this time, the BLP in TSS0 (230) points to TSS1 (130) of the interrupted program,
Furthermore, the value stored in the corresponding area in TSS0 (230) is set in the HW register of the CPU. As a result, the occupancy measurement program (instruction section 200, data section 210, stack section 220) prepared in advance for interval timer interrupt processing is activated.

[0013] The occupancy rate measurement program is TSS0 (230
), the task status table TSS1 (130) of the interrupted program is accessed, and the RPL section 2 of the CS selector is accessed from inside TSS1 (130) according to the format shown in FIG.
By obtaining the bit value "N", the execution level of the interrupted program can be known as "N". Thereafter, the occupancy measurement program updates the value of the area corresponding to the level "N" indicated by the RPL2 bit in the CNT table 240. This means that the counter of the execution level of the program that was running at the time of occurrence of the interrupt of the interval timer 40 has been updated.

After this, when the occupancy measurement program issues a CPU command to end the interrupt processing, TSS0 (230)
After storing the HW register value in the TS indicated by TSS0BLP
TR10 is updated to point to S1 (130), all CPU HW registers are recovered from TSS1, and the CPU
The U execution right will be returned to the interrupted program (the resources pointed to by TSS1).

As explained above, each time the occupancy rate measurement program is started, it simply accesses the task status table (TSS) of the interrupted program using the BLP in TSS0230 and uses the RPL part of the internal CS selector value. The CPU execution level of the interrupted program is obtained and the corresponding value in the CNT table 240 is updated.

Therefore, at any point in time, the CNT table 24
By calculating the ratio of the count value of a specific level to the sum of all counter values within 0, it is possible to obtain a value approximate to the CPU occupancy rate of the program having the CPU execution right of that specific level.

Generally, kernel programs (OS) and application programs use different execution levels from the viewpoint of protection functions, so if the execution level for applications or the execution level of the OS part is specified as the value of this specific level, it is extremely easy to use execution levels for application programs. It becomes possible to measure the CPU occupancy rate of the OS or the CPU occupancy rate (system overhead) of the OS.

[0018]

Effects of the Invention As explained above, the present invention measures the CPU occupancy rate of the program at each execution level by measuring the execution level of the program that has the right to execute the CPU at that time at extremely short regular intervals. It is possible to provide a method for obtaining an approximation. It avoids the drawbacks of the conventional technology, such as the need to know the load address of the program under test, or the increase in overhead of the OS kernel (scheduler), and makes it easy to fix the target to a specific execution level. This has the effect of being able to calculate the CPU occupancy rate of the measurement program. As long as the amount of overhead of the OS is known, this method has the effect of being a sufficiently practical CPU occupancy measurement method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the state of termination of interrupt processing according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a state of starting interrupt processing in the embodiment shown in FIG. 1;

[Figure 3] TSS0 (230) or TSS1 (130)
FIG.

FIG. 4 is a diagram showing details of the CS selector at offset “36” in FIG. 3;

[Explanation of symbols]

10 Task register (T with CPU execution right)
(HW register pointing to SS) 20 IDT address register (a type of HW register) 30 Interrupt description table (IDT) 40
interval timer

Claims (1)

[Claims] Claim 1: In a method for measuring the CPU occupancy rate of a program in a computer in which the CPU execution level of the program is one of a plurality of execution levels, counters are provided in the same number as the execution levels, and the CPU occupancy rate is measured by an external interrupt at regular intervals. , the occupancy measurement program retrieves the execution level of the interrupted program, updates one of the counters corresponding to the retrieved execution level, and calculates the sum of the values of all the counters. A method for measuring a CPU occupancy rate of a program, characterized in that the CPU occupancy rate of a corresponding program is obtained from the ratio of one value of the counter.