JPH04263189A - Serial access memory - Google Patents

Abstract

PURPOSE:To reduce a charging and discharging current which flows between a precharged transistor or a memory cell and a bit line when word lines at a serial access memory are selected. CONSTITUTION:Decoding patterns for an address counter 3, a word decoder 1 and a bit decoder 2 are constituted so that, after all memory cells connected to selected word lines have been accessed, a next word line can be selected. The number of selection operations of the word lines at a serial access memory can be reduced to a minimum, and a power consumption generated at the access operation of the serial access memory can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial access memory in which writing and reading are performed serially.

0002

2. Description of the Related Art In recent years, serial access memory (serial access line memory) has been widely used in the field of digital processing circuits included in computer terminal display devices, VTRs, digital TVs, etc., and image processing circuits included in facsimile machines. ) is often used.

Conventionally, for example, electronic technology 1987-1, 1
As shown in Figure 3 in "FIFO configuration high-speed line memory" on page 03, this function was realized using general-purpose RAM and ROM and peripheral circuits (address counters, etc.).
With the recent improvement in integration capabilities, special-purpose memories for specific applications in which RAM, ROM, and peripheral circuits are integrated into one chip, and various LSIs that also incorporate this dedicated memory have appeared. This brings about major benefits such as high speed, reduction in the number of peripheral components when designing a circuit that includes this memory, and ease of design.

FIG. 2 is a block diagram showing a conventional serial access memory. As shown in the figure, word lines W1 to Wn extend from the word decoder 1, and bit lines B1 to Bm extend from the bit decoder 2.
has been extended. In addition, address clock ACK is input to word decoder 1 and bit decoder 2,
An output from an address counter 3 which performs counting in synchronization with this and sequentially updates the count output value is provided.

Further, each word line W1 to Wn has memory cells M11 to M1m, M21 to M2m, M(n-1)1 to M(n-1)m and Mn, respectively.
1 to Mnm, and each bit line B1 to Bm has memory cells M11 to Mn1, M12 to Mn2, M1(m-1) to Mn(m-1) and M1, respectively.
m to Mnm are connected.

Note that the word lines between word lines W2 and Wn-1, the bit lines between bit lines B2 and Bm-1, and the memory cells associated therewith are omitted. Further, to simplify the explanation, bit bar lines in which the levels of signals on bit lines B1 to Bm in the SRAM are inverted will be omitted.

[0007] The sources of precharge transistors T1 to Tm are connected to the sides of each bit line B1 to Bm to which the bit decoder 2 is not connected, respectively.
A power supply voltage is applied to the drain and gate of m by the power supply terminal Vcc.

Next, the operation will be explained. Address counter 3 counts address clock ACK and provides a count output to word decoder 1 and bit decoder 2 as the count result. The word decoder 1 performs decoding to select only one of the word lines W1 to Wn according to the address count from the address counter 3, and the bit decoder 2 performs decoding according to the address count from the address counter 3. Decoding is performed to select only one of the bit lines B1 to Bm. In this way, reading or writing is performed on the contents of the only memory cell connected to each selected word line and bit line.

Note that the bit lines B1 to Bm are connected to a bit line selection transistor (not shown) in the bit decoder 2, and a sense amplifier and a write driver connected to this transistor select memory cells M11 to Mnm, respectively. Contents are read and written.

Addresses (11) to (nm) are assigned to each memory cell M11 to Mnm, for example, as shown in FIG. 2, and the memory cells are accessed in order from the memory cell with the smallest address value to the memory cell with the largest address value. Ru. Address counter 3 generates a count output in synchronization with address clock ACK, and word decoder 1 and bit decoder 2 perform decoding based on this count output, so word decoder 1, bit decoder 2, and address counter 3 perform serial access function. When realizing this, by appropriately configuring the count circuit for generating the count output in the address counter 3 and the decoding patterns of the word decoder 1 and bit decoder 2, the physical positions of the memory cells M11 to Mnm can be adjusted. There is no need for regularity in the relationship with the assigned addresses, and that relationship was not taken into account.

[0011]

[Problems to be Solved by the Invention] Conventional serial access memories are configured as described above, and in order to access a certain memory cell, the word line and bit line to which this memory cell is connected must be connected. One of each is selected. Furthermore, when a certain word line is selected, transfer gates (not shown) in all memory cells connected to the selected word line are turned on.

When a transfer gate in a memory cell is turned on, the potential of the bit line to which this memory cell is connected becomes the same level as the content stored in the memory cell.

Next, when another word line is selected, the transfer gates in the memory cells connected to this word line are similarly turned on. At this time, among the memory cells connected to the previously selected word line (for example, word line W1) and this newly selected word line (for example, word line W2), the memory cells that are connected to the same bit line are connected to the same bit line. Memory cells, that is, memory cells M11 and M21, M12 and M22, M1 (m-1) and M2 (m-
1) A case may occur in which the storage contents of M1m and M2m are different.

In this case, for example, when the memory content of the memory cell M11 is "0" and the memory content of the memory cell M21 is "1", in order to charge the potential on the bit line B1 from "L" to "H", , a transient current flows from the precharge transistor T1 to the bit line B1 until the potential on the bit line B1 is determined to be "H".

Conversely, the memory content of memory cell M11 is “1”.
”, when the memory content of memory cell M21 is “0”, in order to discharge the potential on bit line B1 from “H” to “L”, the voltage on bit line B1 is set to “L”. A transient current flows from the bit line B1 to the memory cell M21 during the period .

[0016] Therefore, in order to access all the memory cells in this serial access memory (in serial access memory, all memory cells are accessed once in one cycle), the word line must be The more times the selected state changes from one selected state to the selected state, the higher the possibility that a transient current will flow, and the greater the power consumption.

The present invention was made in order to solve the above-mentioned problems, and it reduces the bit line charging/discharging current that occurs when each memory cell M11 to Mnm in a serial access memory is accessed one by one. The purpose is to obtain serial access memory that can be reduced.

[0018]

[Means for Solving the Problems] A serial access memory according to the present invention connects a word line different from the selected word line after all memory cells connected to the selected word line are accessed. Configured to select.

[0019]

[Operation] The serial access memory of the present invention selects a word line different from the selected word line after all memory cells connected to the selected word line are accessed. The number of word line selections can be minimized when all memory cells in the serial access memory are accessed once.

[0020]

[Embodiment] Figure 1 shows a serial access system according to the present invention.
FIG. 2 is a block diagram illustrating an example of a memory. As shown in the figure, from word decoder 1 to word lines W1 to Wn
is extended from bit decoder 2 to bit line B
1 to Bm have been extended. Further, the word decoder 1 and the bit decoder 2 have an address clock A.
An output from an address counter 3 is provided which inputs CK, performs counting in synchronization with this, and sequentially updates the count output value.

Further, each word line W1 to Wn has memory cells M11 to M1m, M21 to M2m, M(n-1)1 to M(n-1)m and Mn, respectively.
1 to Mnm, and each bit line B1 to Bm has memory cells M11 to Mn1, M12 to Mn2, M1(m-1) to Mn(m-1) and M1, respectively.
m to Mnm are connected.

The sources of precharge transistors T1 to Tm are connected to the sides of each bit line B1 to Bm to which the bit decoder 2 is not connected, respectively, and the sources of precharge transistors T1 to Tm are connected to the sides of each bit line B1 to Bm to which the bit decoder 2 is not connected.
A power supply voltage is applied to the drain and gate of m by the power supply terminal Vcc.

Next, the operation will be explained. Address counter 3 counts address clock ACK and provides a count output to word decoder 1 and bit decoder 2 as the count result. The word decoder 1 performs decoding to select only one of the word lines W1 to Wn according to the address count from the address counter 3, and the bit decoder 2 performs decoding according to the address count from the address counter 3. Decoding is performed to select only one of the bit lines B1 to Bm.

In this way, reading or writing is performed on the contents of the only memory cell connected to each selected word line and bit line.

Each memory cell M11 to Mnm is shown in FIG.
Addresses (11) to (nm) as shown in
are assigned, and the memory cells are accessed in this order.

That is, first, word line W1 and bit line B1 are selected, and memory cell M11 assigned address (11) is accessed. Next, the word line W
Bit line B2 is selected while bit line B2 remains selected, and memory cell M12 to which address (12) is assigned is accessed. In this way, the bit lines Bm-1 and Bm are selected while the word line W1 is kept in the selected state, and the addresses (1(m-1)) and (1m
) are accessed to memory cells M1 (m-1) and M1m.

Next, word line W1 is set to a non-selected state and word line W2 is set to a selected state, and memory cells M21 to M2m assigned addresses (21) to (2m) are sequentially accessed. Next, the word line W2 is made unselected, the word line Wn-1 is made selected, and the address (
Memory cells M(n-1)1 to M(n-1)m to which (n-1)1) to ((n-1)m) are assigned are sequentially accessed. Finally, the word line Wn-1 is made unselected, the word line Wn is made selected, and the address (n1
) to (nm) are accessed in the order of memory cells Mn1 to Mnm to complete one cycle, and then the word lines W1 . is selected.

By accessing in this manner, the number of times a word line changes from a non-selected state to a selected state during one cycle becomes n, which is the number of word lines.

The address counter 3 can be constituted by a simple binary counter, and among the plurality of count outputs of this binary counter, for example, the count output a is given to the word decoder 1, and the count output b is given to the bit decoder 2. , so that the count output b changes m times, which is the number of bit lines, during the period in which the value of the count output a changes once, and the value of the count output b changes n times, which is the number of word lines.
It may be configured to return to the original value after changing twice. Further, the word decoder 1 has a decoder circuit configured to sequentially select word lines W1 to Wn according to changes in the value of the count output a from the address counter 3, and the bit decoder 2 has a decoder circuit configured to sequentially select word lines W1 to Wn according to changes in the value of the count output a from the address counter 3.
The decoder circuit may be configured to sequentially select bit lines B1 to Bm according to changes in the value of .

As described above, according to the present invention, all the memory cells connected to the selected word line are accessed, and then the word line connected to the memory cell to be accessed next is selected. Therefore, the number of times a word line is selected is equal to the number of word lines, and the transient current that flows when selecting a word line can be minimized.

In this embodiment, the word lines W1 to Wn are selected in the order of W1 to Wn, and the bit lines B1 to Bm are selected in the order of B1 to Bm.
This order may be performed in any order as long as all word lines are selected once in one cycle and all bit lines are selected once when a certain word line is in the selected state.

Further, the present invention is applicable not only to a standalone serial access memory but also to a serial access memory included in a semiconductor integrated circuit.

[0033]

[Effects of the Invention] As described above, according to the present invention, a word line different from the selected word line is selected after all memory cells connected to the selected word line are accessed. This minimizes the number of times a word line is selected when accessing all memory cells in a serial access memory, and minimizes the transient current that flows to determine the bit line level when selecting a word line. This has the effect of reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a serial access memory according to the invention.

FIG. 2 is a block diagram illustrating a conventional serial access memory.

[Explanation of symbols]

1 Word decoder 2 Bit decoder 3 Address counter W1 ~ Wn Word line B1 ~ Bm Bit line M11~Mnm memory cell

Claims (1)

[Claims] 1. A serial access memory that performs writing and reading serially, wherein after all memory cells connected to a selected word line are accessed, a word line different from the selected word line is accessed. A serial access memory characterized by being selective.