SE7409882L - - Google Patents

Info

Publication number
SE7409882L
SE7409882L SE7409882A SE7409882A SE7409882L SE 7409882 L SE7409882 L SE 7409882L SE 7409882 A SE7409882 A SE 7409882A SE 7409882 A SE7409882 A SE 7409882A SE 7409882 L SE7409882 L SE 7409882L
Authority
SE
Sweden
Prior art keywords
transistor
node
voltage
logical
output
Prior art date
Application number
SE7409882A
Other languages
Unknown language ( )
Inventor
N Kitagawa
C-K Kuo
M S Briner
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US385203A external-priority patent/US3909631A/en
Priority claimed from US05/385,122 external-priority patent/US3940747A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of SE7409882L publication Critical patent/SE7409882L/

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1484941 Transistor switching circuits TEXAS INSTRUMENTS Inc 1 Aug 1974 [2 Aug 1973 (5)] 33988/74 Heading H3T [Also in Division G4] A sense amplifier 6, Fig. 4, in an LSI semiconductor random access memory (see Divisions G4-G6) comprises cross-coupled driver transistors 3, 31 having sense nodes A, B respectively coupled to left-hand and right-hand halves of the respective column D n of the memory, the sense nodes A, B being each precharged to a predetermined voltage level representing approximately halfway between the voltage levels corresponding to logical 1 and logical 0 prior to each read or write operation. Data is stored in the form of opposite logic indications on each side of the sense amplifier 6, e.g. a logical 1 is stored as a high level signal in the left-hand half of the column D n and as a low level signal in the righthand half. In operation, lines PVG1 and PVG0 of a charging circuit 38 are precharged to voltage levels respectively representing logical 1 and 0, these voltage levels being combined by a transistor 5 to give the predetermined voltage level which is applied to capacitors C, D of dummy cells located on each side of the sense amplifier 6. Selection of a storage cell of the memory to the left of sense amplifier 6 simultaneously selects the right-hand dummy cell, and vice versa, so that the voltage from the selected storage cell and the predetermined voltage level are respectively applied to the sense nodes A, B. If a logical 1 is applied to node A, transistor 3<SP>1</SP> conducts and clamps node B to ground potential, node A charging up to logical 1 from a positive voltage source V DD via a transistor 15, the converse occurring if a logical 0 is supplied to node A. At the end of the charging up of node A its voltage may be read out or overwritten, but it is in any case supplied back to the selected storage cell for refreshing purposes. Selection of a storage cell of a particular row for reading or writing thereby causes all the storage cells of that row to be refreshed. An address buffer one stage of which is shown as 2 in Fig. 8, receives an input A 0 from external TTL and produces true and complement outputs #A 0 , #A 0 suitable for the MOS logic of the memory. By means of the direct connection of the source of a driver transistor 25 to the buffer input A 0 , it is stated that a smaller and faster first inverter transistor 26 may be employed than in the prior art. In operation, a node 29 is precharged from source V DD via a transistor 27, the node 29 then being conditionally discharged depending on the gate voltage of transistor 25 which in turn depends on the voltage applied to input A 0 . If the voltage at output A 0 is high, that at output A 0 is low and, since a transistor 31 is conducting, power is thereby dissipated via transistors 31 and 39. This power is conserved by transistors 71, 73 sensing the high voltage level at output A 0 and turning off transistor 39 via a transistor 51. No current thereby flows through transistor 31, but transistor 31 is still on and so clamps output A 0 to ground potential. Operation is analogous when output #A 0 is low and #A 0 is high, output A 0 then being clamped to ground potential. Reference has been directed by the Comptroller to Specifications 1,409,910 and 1,244,683.
SE7409882A 1973-08-02 1974-07-31 SE7409882L (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US38499473A 1973-08-02 1973-08-02
US38520173A 1973-08-02 1973-08-02
US38513873A 1973-08-02 1973-08-02
US385203A US3909631A (en) 1973-08-02 1973-08-02 Pre-charge voltage generating system
US05/385,122 US3940747A (en) 1973-08-02 1973-08-02 High density, high speed random access read-write memory

Publications (1)

Publication Number Publication Date
SE7409882L true SE7409882L (en) 1975-02-03

Family

ID=27541399

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7409882A SE7409882L (en) 1973-08-02 1974-07-31

Country Status (12)

Country Link
JP (1) JPS5046049A (en)
BE (1) BE818317A (en)
CH (1) CH594955A5 (en)
DD (1) DD116339A5 (en)
DE (1) DE2437396A1 (en)
FR (1) FR2239737B1 (en)
GB (1) GB1484941A (en)
HU (1) HU171057B (en)
IT (1) IT1018806B (en)
NL (1) NL7410423A (en)
RO (1) RO82918B (en)
SE (1) SE7409882L (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525224A (en) * 1975-07-02 1977-01-14 Hitachi Ltd 1trs-type memory cell
DE2646245A1 (en) * 1975-10-28 1977-05-05 Motorola Inc MEMORY CIRCUIT
FR2337917A1 (en) * 1976-01-08 1977-08-05 Mostek Corp Direct access semiconductor memory - has input and output registers and column and row address registers (SW 4.7.77)
JPS58139399A (en) * 1982-02-15 1983-08-18 Hitachi Ltd Semiconductor storage device
JPS6085492A (en) * 1983-10-17 1985-05-14 Hitachi Ltd Dynamic memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3514765A (en) * 1969-05-23 1970-05-26 Shell Oil Co Sense amplifier comprising cross coupled mosfet's operating in a race mode for single device per bit mosfet memories
US3678473A (en) * 1970-06-04 1972-07-18 Shell Oil Co Read-write circuit for capacitive memory arrays
BE789500A (en) * 1971-09-30 1973-03-29 Siemens Ag SEMICONDUCTOR MEMORY WITH SINGLE TRANSISTOR MEMORIZATION ELEMENTS
US3838404A (en) * 1973-05-17 1974-09-24 Teletype Corp Random access memory system and cell

Also Published As

Publication number Publication date
NL7410423A (en) 1975-02-04
HU171057B (en) 1977-10-28
CH594955A5 (en) 1978-01-31
IT1018806B (en) 1977-10-20
BE818317A (en) 1974-11-18
JPS5046049A (en) 1975-04-24
GB1484941A (en) 1977-09-08
RO82918B (en) 1984-09-30
DE2437396A1 (en) 1975-02-13
FR2239737A1 (en) 1975-02-28
RO82918A (en) 1984-08-17
DD116339A5 (en) 1975-11-12
FR2239737B1 (en) 1980-12-05

Similar Documents

Publication Publication Date Title
US4062000A (en) Current sense amp for static memory cell
US3678473A (en) Read-write circuit for capacitive memory arrays
US5239502A (en) Bit storage cell
US5040146A (en) Static memory cell
US5243573A (en) Sense amplifier for nonvolatile semiconductor storage devices
US5539691A (en) Semiconductor memory device and method for reading and writing data therein
US4031415A (en) Address buffer circuit for semiconductor memory
US6707751B2 (en) Semiconductor integrated circuit device
US3962686A (en) Memory circuit
US5208773A (en) Semiconductor memory device having bit lines and word lines different in data reading and data writing
US4054865A (en) Sense latch circuit for a bisectional memory array
US4598389A (en) Single-ended CMOS sense amplifier
US4860257A (en) Level shifter for an input/output bus in a CMOS dynamic ram
US3688264A (en) Operation of field-effect transistor circuits having substantial distributed capacitance
US4380055A (en) Static RAM memory cell
KR910004733B1 (en) Semiconductor memory device having data bus reset circuit
KR0155986B1 (en) Semiconductor memory device
US3705390A (en) Content addressed memory cell with selective bit writing
US4114192A (en) Semiconductor memory device to reduce parasitic output capacitance
SE7409882L (en)
JPH01169798A (en) Semiconductor memory device
US3644905A (en) Single device storage cell for read-write memory utilizing complementary field-effect transistors
JPH06132747A (en) Semiconductor device
US4542484A (en) Sense amplifier with high speed, stabilized read-out
US6133781A (en) Semiconductor device utilizing unnecessary electric charge on complementary signal line pair

Legal Events

Date Code Title Description
NAV Patent application has lapsed

Ref document number: 7409882-3