JPH04262620A - Clock signal synchronizing device - Google Patents

Abstract

PURPOSE:To obtain an internal clock synchronously with an external clock in a short time especially and less frequency fluctuation in the device obtaining the internal clock synchronously with the external clock entered externally. CONSTITUTION:An internal clock generated from an internal clock generating circuit 4 is frequency-divided by a frequency divider circuit 6. Then a frequency divider control circuit 8 controls the frequency divider circuit 6 and is operated synchronously with an external clock. Moreover, when the internal clock and the external clock are almost synchronized by the control operation of the frequency divider circuit 6 and the frequency divider control circuit 8, the synchronization state is maintained by the control operation of a comparison means 7 and a control signal generating circuit 5.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

[Field of Industrial Application] The present invention relates to a clock signal synchronizer for synchronizing an internal clock used inside a specific device with an external clock input from the outside. The present invention relates to a clock signal synchronization device that is useful when applied to a clock generation circuit inside a digital tape recorder in order to operate the recorder synchronously.

0002

2. Description of the Related Art A digital tape recorder, which is known as a type of information equipment, operates based on an internal clock (internal clock signal) generated from a clock generation circuit built into the tape recorder. Multiple units, e.g. 2
When two digital tape recorders are operated synchronously, their internal clocks must be synchronized. That is, if the internal clocks of two digital tape recorders are completely synchronized, the two digital tape recorders will operate as if they were one digital tape recorder.

[0003] In this way, in order to synchronize the internal clocks of two digital tape recorders in order to operate them synchronously, it is sufficient to send a synchronization clock from one to the other. In this case, the digital tape recorder on the synchronizing side (the other one) receives the synchronization clock sent from one of the devices as an external clock (external clock signal) and synchronizes its internal clock generation circuit with the external clock. to control.

As such a conventional clock signal synchronization device, a device described in Japanese Patent Application Publication No. 16942/1980 is known. This device is a clock signal synchronization device for a digital tape recorder, and is described as a component of a system for duplicating the digital signal of another device as it is. The clock synchronizer described here has a PL
They are synchronized by an L circuit.

[0005]

[Problem to be solved by the invention] By the way, P
In a conventional clock signal synchronizer using an LL circuit, P
Since fluctuations, which are an inherent property of the LL circuit, cannot be avoided, there is a problem in that the period of the generated clock fluctuates frequently.

That is, a PLL circuit has the property that even if it is synchronized with an external clock, fluctuations inevitably occur within a certain range around the synchronized period. To avoid this fluctuation, it is desirable to use a variable frequency crystal oscillator circuit whose oscillation period can be controlled to a certain extent, but if the clock signal synchronizer is configured only within this controllable range, it will take a long time before the clocks are synchronized. Another problem arises in that it takes a long time. For example, it takes tens of thousands of clocks to synchronize, so a corresponding amount of time is required.

The present invention has been made in response to the above-mentioned problems, and it is an object of the present invention to provide a clock signal synchronization device that can synchronize an internal clock with an external clock in a short period of time.

[Configuration of the invention]

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a clock signal synchronization device for synchronizing an internal clock generated from an internal clock generation circuit with an external clock input from an external terminal. an internal clock generation circuit whose oscillation period can be controlled by a control signal; a frequency division circuit that divides the frequency of the internal clock generated from the internal clock generation circuit; and a frequency division output of the frequency division circuit and input from an external terminal. a comparison means for comparing the phases of external clocks; a control signal generation circuit for generating a control signal to be applied to the internal clock generation circuit based on the output of the comparison means; and a control signal generation circuit for generating a control signal to be applied to the internal clock generation circuit in synchronization with the external clock The present invention is characterized in that it includes a frequency division control circuit that controls the timing of the start of a cycle.

0010

[Operation] In the above structure, the frequency of the internal clock generated from the internal clock generation circuit is divided by the frequency division circuit under the control operation of the frequency division control circuit. This internal clock is compared in phase with the external clock by the comparison means, and if they do not match, the operation of the internal clock generation circuit is controlled by the comparison means and the control signal generation circuit until they match. The internal clock can be synchronized with the external clock by matching the phases of both clocks.
By using a circuit with a narrow oscillation period, such as a variable frequency crystal oscillation circuit, as the internal clock generation circuit, the internal clock can be synchronized with the external clock in a short time.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the clock signal synchronization device of the present invention, in which 1 is an external terminal, 2 is an output terminal, and an external clock is input to the external terminal 1, and the output terminal 2 is an output terminal.
outputs an internal clock synchronized with the external clock. 3 is a control terminal to which a synchronization command signal is input when synchronization is required.

Reference numeral 4 denotes an internal clock generation circuit, which is composed of, for example, a frequency variable crystal oscillation circuit whose oscillation period can be varied within a narrow range.This internal clock generation circuit 4 always generates an internal clock regardless of the phase of the external clock. ing. The period of this internal clock can be controlled by a control signal output from a control signal generation circuit 5, which will be described later. This control range may be a narrow range that can follow fluctuations in the period of the external clock.

6 is a frequency dividing circuit for dividing the internal clock output from the internal clock generating circuit 4;
It is equipped with an N terminal and an LD terminal, and is connected to the frequency division control circuit 8 described later.
Frequency division is started at the timing when a frequency division start signal is applied from , and until this frequency division start signal is applied, the frequency division operation is not performed even if an internal clock is applied. That is, when an input is applied to the EN terminal, the frequency dividing operation is started at the falling edge of the signal input to the LD terminal. The internal clock generated by frequency division is output from the output terminal 2 and also to the comparison means 7.

Comparing means 7 compares the phases of the internal clock outputted from the frequency dividing circuit 6 and the external clock inputted from the external terminal 1, and outputs a signal according to the comparison result to the control signal generation circuit 5. do.

Reference numeral 5 denotes a control signal generation circuit which outputs a control signal to the internal clock generation circuit 4 in response to the output signal from the comparator 7 to match the phases of the internal clock and the external clock.

Reference numeral 8 denotes a frequency division control circuit, and a frequency division start signal that gives the frequency division circuit 6 the timing to start frequency division operation in response to a synchronization command signal input to the control terminal 3 when synchronization is required. Output.

The frequency division control circuit 8 is composed of a first flip-flop 9, a second flip-flop 10, and a third flip-flop 11.

The first flip-flop 9 has an S terminal, a Q terminal, and a CLR terminal, and when an input is applied to the S terminal, the output from the Q terminal is inverted, and when an input is applied to the CLR terminal, it is reset. The output of the Q terminal also operates to return to its original state.

The second flip-flop 10 has a DI terminal,
It is equipped with a Q terminal, a CLR terminal, and a CK terminal, and captures the state of the DI terminal at the falling edge of the signal applied to the CK terminal, inverts the output of the Q terminal, and
It operates so as to be reset by input to the LR terminal.

The third flip-flop 11 has an AI terminal,
It is equipped with a Q terminal and a BI terminal, and the state of the AI terminal can be read from the BI terminal.
It operates to take in the signal applied to the terminal at the timing of the fall, invert the output of the Q terminal, and return the output state of the Q terminal to its original state after a preset time T has elapsed.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

Note that A is an external clock input to the external terminal 1, B is a synchronization command signal input to the control terminal 3, and C is a synchronization command signal input to the control terminal 3.
is the output signal of the second flip-flop 10, D is the output signal of the third flip-flop 11, and E is the internal clock output from the frequency dividing circuit 6.

[0024] An external clock A is input to the external terminal 1 at a regular constant cycle, as shown at times T1 to T5. Assume that in this state, the synchronization command signal B is input to the S terminal at time T12. Then, T12
The first flip-flop 9 is set at the timing of , and this Q terminal is inverted. Next, at time T2, the external clock A is input to the CK terminal, so that the output signal C of the second flip-flop 10 is inverted.
This state is maintained until time T3 when the next external clock A is input.

Next, the external clock A is input to the BI terminal at time T3, so that the third flip-flop 11 operates and outputs the inverted output signal for the preset time T as described above. Q with D as the division start signal
from the terminal to the LD terminal of the frequency divider circuit 6.

As a result, the frequency dividing circuit 6 starts the frequency dividing operation at the timing when the frequency dividing start signal D is applied. This frequency division operation is performed as follows.

First, after the start of frequency division, the internal clock E outputted from the frequency dividing circuit 6 is applied to the comparator 1, and its phase is compared with the external clock A. At this time, there is a phase (time) of T between the internal clock E and the external clock A. Therefore, the comparator 1 outputs a corresponding comparison result signal to the control signal generating circuit 5. Subsequently, the control signal generation circuit 5 outputs a control signal corresponding to the phase T to the internal clock generation circuit 4. Therefore, internal clock generation circuit 4
controls so that the internal clock E is output by varying the oscillation period. This internal clock generating circuit 4 has a variable range of about 400 PPM, for example, and the period of the internal clock E is controlled within this variable range.

Such a series of control operations is repeated at timings after T4, and the internal clock E gradually synchronizes with the external clock over a period of several clocks. When the comparison means 1 no longer detects a phase difference, both are synchronized. According to this embodiment, by using a variable frequency crystal oscillation circuit with a narrow variable range of oscillation period as the internal clock generation circuit 4, synchronization can be achieved within several clocks. Therefore, the internal clock E can be synchronized with the external clock A in an extremely short time.

As described above, according to this embodiment, even if the internal clock generation circuit is configured with a circuit whose oscillation period can be varied within a narrow range, such as a variable frequency crystal oscillation circuit, it is possible to convert the internal clock to the external clock in a short time. Since it becomes possible to synchronize, it is useful when applied to applications where a plurality of digital tape recorders etc. are operated synchronously.

[0030]

As described above, according to the present invention, even if the variable range of the oscillation cycle of the internal clock generation circuit is narrow, the internal clock can be synchronized with the external clock in a short time. A clock synchronization device with less frequency fluctuation can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a clock signal synchronization device of the present invention.

FIG. 2 is a timing chart illustrating the operation of this embodiment.

[Explanation of symbols]

4 Internal clock generation circuit 5 Control signal generation circuit 6 Frequency divider circuit 7. Comparison means 8 Frequency division control circuit 9 First flip-flop 10 Second flip-flop 11 Third flip-flop A External clock E Internal clock

Claims (2)

[Claims] 1. A clock signal synchronizer for synchronizing an internal clock generated from an internal clock generation circuit with an external clock input from an external terminal, comprising: an internal clock generation circuit whose oscillation period can be controlled by a control signal; a frequency dividing circuit that divides the frequency of the internal clock generated from the internal clock generating circuit; a comparison means that compares the frequency division output of the frequency division circuit and the phase of an external clock input from an external terminal; and an output of the comparison means. a control signal generation circuit that generates a control signal to be applied to the internal clock generation circuit based on the external clock; and a frequency division control circuit that controls the timing of the start of frequency division of the frequency division circuit in synchronization with the external clock. A clock signal synchronization device characterized by: 2. A clock signal synchronization device according to claim 1, wherein said internal clock generation circuit is comprised of a variable frequency crystal oscillation circuit.