JPH04261240A - Preamble extraction circuit - Google Patents

Abstract

PURPOSE:To realize a timing recovery circuit able to attain high speed locking by facilitating the extraction of a timing signal component in the timing recovery circuit receiving a GMSK modulation wave having a preamble signal including 0/1 alternate pattern at its head so as to recover the timing. CONSTITUTION:An in-phase component of a demodulated base band signal 1 and an orthogonal component resulting from converting the sign are added by an adder 11, at which a DC component is eliminated and the amplitude is doubled and the result is inputted to a timing extraction filter 4 provided at the outside of the system of the timing recovery system PLL circuit 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GMSK modulated wave receiver, particularly to a preamble extraction circuit suitable for high-speed pull-in of a timing recovery circuit and preamble signal detection.

0002

[Prior art] As a conventional technology, for example,
As shown in Publication No. 198133 "Burst Wave Preamble Extraction Circuit", there is a method of extracting the fundamental wave component of a 0, 1 alternating pattern from either one of the components (in-phase or quadrature component) of the demodulated baseband signal. . This will be explained using FIG. 2.

Either one of the demodulated baseband signals 1 is input to a timing extraction filter 4 having a high Q, and fundamental frequency components of a 0, 1 alternating pattern are extracted. This extracted output is compared with a threshold value 5 by a level comparator 6 to detect the arrival of a preamble signal, and is held in a level judgment output hold circuit 7. Therefore, when detecting the arrival of the preamble signal, the phase difference signal calculated by the phase error calculation section 8 from the output of the timing extraction filter 4 is given from the phase correction amount setting value switch 9 as the phase offset correction amount of the timing recovery system PLL circuit 3. This enables high-speed pull-in of timing regeneration.

In normal timing recovery, the phase comparator 2 converts the in-phase and quadrature components of the demodulated baseband signal into the reference clock 10 of the timing recovery system PLL circuit 3 and the reference clock 1 of the timing recovery system PLL circuit 3.
0 and this phase difference information is input as phase control information to the timing recovery system PLL circuit 3 to perform timing recovery.

[0005]

[Problem to be Solved by the Invention] However, when the above-mentioned conventional technology is applied to the GMSK modulation method, generally in the case of a 0,1 alternating pattern, the demodulated baseband signal has small amplitude fluctuations and has a DC component. , it is difficult to extract the fundamental frequency component, and it takes time to obtain a stable output, so there is a serious drawback that the high-speed initial phase pull-in of the timing signal is lost. In order to solve this drawback, the present invention uses the signal obtained by adding the demodulated baseband signal as the input of the timing extraction filter.
It is an object of the present invention to provide a timing recovery circuit that facilitates extraction of basic components of an alternating pattern and performs high-speed pull-in.

[0006]

[Means for solving the problem] In GMSK modulation, 0,
When transmitting one alternating pattern, if the initial phase is 0 [rad], the phase φ(t) is centered around π/4 [rad] as shown in Figure 3, and the time 2 is twice the time of one time slot T [sec].
The phase change is one round trip in T [sec]. Therefore, the in-phase component COSφ of the demodulated baseband signal at this time
(t) and the orthogonal component sinφ(t) have a waveform as shown in FIG. 4 with the center at the square root of 1/2 and one period of 2T [sec]. In order to achieve the above object, the present invention provides an output signal obtained by adding the in-phase component cosφ(t) of the demodulated baseband signal and the orthogonal component -sinφ(t) whose sign is inverted, outside the timing recovery system PLL circuit 3. The input signal is used as an input to a timing extraction filter.

[0007]

As a result, in the addition output of the demodulated baseband signal, the DC component is canceled and at the same time the amplitude is doubled, and the fundamental frequency component of the 0, 1 alternating pattern is stably extracted at the input of the timing extraction filter.

[0008]

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In-phase component cosφ(t) of demodulated baseband signal 1
The adder 11 adds −sinφ(t), which is obtained by inverting the sign of the demodulated baseband signal sinφ(t). This addition cancels the DC component and doubles the amplitude.

Next, this addition output is input to a timing extraction filter 4 having a high Q, and fundamental frequency components of the 0, 1 alternating pattern are extracted. As described above, the input signal to the extraction filter 4 has no DC component and has double the amplitude compared to the conventional one, so the extraction of the fundamental frequency component in the extraction filter 4 becomes extremely easy, and high-speed acquisition is maintained. By comparing this extracted output with the threshold value 5 in the level comparator 6, the arrival of the preamble signal is detected.
It is held in the level judgment output hold circuit 7. Therefore, when detecting the arrival of the preamble signal, the phase difference signal calculated by the phase error calculation section 8 from the output of the timing extraction filter 4 is given from the phase correction amount setting value switch 9 as the phase offset correction amount of the timing recovery system PLL circuit 3. This enables high-speed pull-in of timing regeneration.

During normal timing reproduction, the in-phase and quadrature components of the demodulated baseband signal are detected by the phase comparator 2.
The phase is compared with the reference clock 10 of the timing regeneration system PLL 3, and this phase difference information is used as the timing regeneration system PL.
It is input as phase control information of the L circuit 3 and timing reproduction is performed. This system is equivalent to a timing regeneration system that has been commonly used in the past.

[0011]

Effects of the Invention According to the present invention, by simply adding one adder at a low cost, the drawbacks of the conventional 0,1 alternating pattern transmission preamble of a GMSK modulated wave can be eliminated and the reproduction timing can be significantly increased. It is possible to pull in the initial phase of . Furthermore, as a result, the increase in error rate due to initial timing phase pull-in delay can be eliminated, and the effect is significant.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing one embodiment of the present invention.

FIG. 2 is a functional block diagram showing an example of a conventional preamble extraction circuit.

FIG. 3 is a signal phase transition diagram during 0,1 alternating pattern transmission.

FIG. 4 is a waveform diagram of a demodulated baseband signal.

[Explanation of symbols]

1 Demodulated baseband signal 2 Phase comparator 3 Timing recovery system PLL circuit 4 Bandpass filter 5 Level judgment threshold 6 Level comparator 7 Output hold circuit 8 Phase error calculation section 9 Phase correction amount setting switch 10 Reference clock 11 Adder

Claims (1)

[Claims] Claim 1: In a timing recovery circuit that receives a GMSK modulated wave starting with a preamble signal including an alternating pattern of 0 and 1 and performs data timing recovery, the in-phase component of the demodulated baseband signal and the orthogonal component whose sign is inverted A preamble extraction circuit characterized in that means for extracting the fundamental wave component of the 0, 1 alternating pattern from the addition output of the preamble is provided outside the timing reproduction system PLL circuit.