JPH04255250A - Method of forming multilayer interconnection - Google Patents

Abstract

PURPOSE:To prevent a short circuit from occurring between adjacent wrings by a method wherein a coating attached to the side wall of an opening is removed through etching with an alkaline solution, and a metal layer is selectively grown on the metal wiring inside the opening. CONSTITUTION:When a silicon oxide film 4 is etched and an opening 6 is provided so as to reach a tungsten wiring 3, a coating 7 mainly composed of fluoride is attached to the side wall of the opening 6 due to the over etching of the silicon oxide 4 and foreign objects such as the residues of a photoresist film 5 and others are attached to the surface of the silicon oxide film 4. The surface including the base of the opening 6 is treated with an alkaline solution for instance, an ammonia solution to remove the coating 7 mainly formed of fluoride and the residue 8. In succession, a tungsten layer 9 is selectively grown on the surface of the tungsten wiring 3 inside the opening 6 to fill up the opening 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming multilayer wiring.

0002

[Background Art] In recent years, as large-scale integrated circuit devices have become more highly integrated, the aspect ratio (depth/diameter) of openings in interlayer insulating films provided to connect lower-layer wiring and upper-layer wiring has become larger. However, in the technique of forming an opening in the interlayer insulating film on the lower wiring and then depositing a metal layer using a normal sputtering method to form the upper wiring, the metal layer is deposited closely on the sidewall of the opening. However, there were problems in that connection failures between upper and lower layer wiring were likely to occur, and connection resistance was high. Therefore, in order to solve this problem, a method has been adopted in which a high melting point metal layer such as tungsten is selectively formed inside the opening by chemical vapor deposition to fill the inside of the opening.
Prior to the growth of high melting point metals, the substrate surface was treated with dilute hydrofluoric acid.

FIGS. 2A to 2D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method for forming multilayer wiring.

First, as shown in FIG. 2A, a lower tungsten interconnect 3 is formed on a silicon oxide film 2 provided on a silicon substrate 1, and the surface including the tungsten interconnect 3 is oxidized by plasma CVD. A silicon film 4 is deposited to form an interlayer insulating film. Next, a photoresist film 5 is applied onto the silicon oxide film 4 and patterned.

Next, as shown in FIG. 2B, the silicon oxide film 4 is etched by a reactive ion etching method using carbon tetrafluoride gas using the photoresist film 5 as a mask to reach the tungsten wiring 3. Openings 6 are formed and photoresist film 5 is removed. Usually, when etching this silicon oxide film 4, over-etching is performed by about 20 to 50%, so a film 7 mainly composed of fluoride adheres to the side wall of the opening 6, and this film 7 is attached to the photoresist film 5. Even after removing it, it remains on the side wall of the through hole. Furthermore, foreign matter 8 may adhere to the silicon oxide film 4 .

Next, as shown in FIG. 2C, after the substrate surface is treated with dilute hydrofluoric acid, a tungsten layer 9 is selectively grown in the opening 6 by low pressure chemical vapor deposition.

Next, as shown in FIG. 2(d), an aluminum alloy film is deposited and patterned on the surface including the tungsten layer 9 by a conventional sputtering method to form an upper layer of aluminum wiring 10.

[0008]

[Problems to be Solved by the Invention] In this conventional method for forming multilayer wiring, the surface is treated with dilute hydrofluoric acid before the tungsten layer is selectively grown inside the opening. Since the film containing fluoride as a main component is not removed, a tungsten layer also grows on the film above the opening, and a tungsten layer is formed on the interlayer insulating film, resulting in short circuits between wires if the wire spacing is narrow. There is a risk that it will happen.

Furthermore, if the removal of the photoresist film is insufficient or if foreign matter adheres to the surface of the interlayer insulating film, a tungsten layer will also grow on the interlayer insulating film. There is a problem that short circuits occur between wiring lines.

0010

[Means for Solving the Problems] A method for forming a multilayer wiring according to the present invention includes forming an interlayer insulating film on a surface including underlying metal wiring, and selectively etching the interlayer insulating film on the metal wiring to open the layer. a step of forming a hole to expose the surface of the metal wiring; a step of removing the film attached to the side wall of the opening through the etching using an alkaline aqueous solution; and a step of exposing the surface of the metal wiring in the opening to a chemical vapor The method includes a step of selectively growing a metal layer using a phase growth method to fill the opening.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), a lower tungsten wiring 3 is formed on a silicon oxide film 2 provided on a silicon substrate 1, and an interlayer is formed on the surface including the tungsten wiring 3 by plasma CVD. A silicon oxide film 4 is deposited as an insulating film. Next, a photoresist film 5 is applied onto the silicon oxide film 4 and patterned.

Next, as shown in FIG. 1B, the silicon oxide film 4 is etched by a reactive ion etching method using carbon tetrafluoride gas using the photoresist film 4 as a mask, and the tungsten wiring 3 is etched. After forming the opening 6 to reach the photoresist film 5, the photoresist film 5 is removed using oxygen plasma. Here, due to over-etching of the silicon oxide film 4 when forming the opening 6, a coating 7 mainly composed of fluoride adheres to the side wall of the opening 6, and the photoresist film 5
It remains even when it is removed using oxygen plasma or the like. In addition, foreign matter 8 such as the residue of the photoresist film 5 is attached to the surface of the silicon oxide film 4 .

Next, as shown in FIG. 1(c), the surface including the openings is treated with an alkaline aqueous solution, for example, an ammonia aqueous solution, for about 10 to 60 seconds to remove the coating 7 and the residue 8 mainly composed of fluoride. After removing, wash thoroughly with water and dry.

Next, as shown in FIG. 1(d), tungsten is selectively deposited on the surface of the tungsten wiring 3 in the opening 6 by a low pressure chemical vapor deposition method using tungsten hexafluoride and a silane reduction method. A layer 9 is grown to fill the opening 6. Next, an aluminum alloy film is deposited by sputtering on the surface including the tungsten layer 9 and selectively etched to form an upper layer of aluminum wiring 10.

Here, the time for treatment with the alkaline aqueous solution varies depending on the amount of the film attached to the side wall of the opening, but at least 1.
A time of about 0 seconds is required, and if it is too long, the surface of the underlying wiring exposed in the opening will be etched, so a time of about 60 seconds at most is optimal.

Note that an aluminum alloy or aluminum wiring may be used instead of the tungsten wiring 3 in the lower layer, and in this case, trimethylammonium hydride oxide is used to remove the film mainly composed of fluoride attached to the opening. Aqueous solutions can be used.

Further, instead of the tungsten layer 9 filling the inside of the opening, an aluminum layer may be selectively grown by a low pressure vapor phase growth method using dimethyl aluminum hydride as a raw material gas and hydrogen as a carrier gas.

[0020]

Effects of the Invention As explained above, the present invention can improve the growth of a fluoride-based film of the lower wiring metal attached to the side wall of the opening provided in the interlayer insulating film and the growth of the metal layer on the interlayer insulating film. By treating the surface with an alkaline aqueous solution to remove core foreign particles, the metal layer selectively grown inside the opening can be prevented from growing outside the opening, thereby preventing short-circuits between adjacent wirings. It has the effect of preventing.

Furthermore, since the natural oxide film formed on the surface of the lower wiring exposed inside the opening can be removed with this alkaline aqueous solution, the metal layer can be selectively grown with good uniformity inside the opening, and the metal layer can be selectively grown in the opening. It also has the advantage of reducing connection resistance.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a conventional method for forming multilayer wiring.

[Explanation of symbols]

1 Silicon substrate 2,4 Silicon oxide film 3 Tungsten wiring 5 Photoresist film 6 Opening part 7 Film mainly composed of fluoride 8 Foreign matter 9 Tungsten layer 10 Aluminum wiring

Claims (2)

[Claims] 1. A step of forming an interlayer insulating film on a surface including the underlying metal wiring, and selectively etching the interlayer insulating film on the metal wiring to form an opening and exposing the surface of the metal wiring; removing a film attached to the side wall of the opening by the etching using an alkaline aqueous solution;
A method for forming a multilayer wiring, comprising the step of selectively growing a metal layer on the surface of the metal wiring in the opening by chemical vapor deposition to fill the inside of the opening. 2. The method for forming multilayer wiring according to claim 1, wherein the alkaline aqueous solution is an ammonia-based organic alkaline aqueous solution.