JPH03173125A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a contact resistance of an interconnection layer and to form an electrode interconnection whose reliability is high by a method wherein, before a second conductor layer is formed so as to come into contact with the surface of a substrate of a conductor layer such as a first interconnection layer or the like, the surface of the conductor layer is exposed to an atmosphere of a mixed gas composed of hydrogen gas and a gas containing at least one kind of halogen atoms while it is being irradiated with light. CONSTITUTION:An element isolation and insulating film 2 is first formed on the surface of a p-type silicon substrate 1; an element region is formed; then, a diffusion layer 3 is formed. At this time, a spontaneous oxide film 6 is formed on the surface. In addition, a silicon oxide film 4 is formed by a CVD method or the like; a contact hole 5 is made in the film; a resist is stripped off and removed. At this time, the spontaneous oxide film 6 is formed on the diffusion layer 3 at the bottom. The substrate 1 is placed in a vacuum container; a gas atmosphere of hydrogen and chlorine is formed; the diffusion layer 3 and the silicon oxide film 4 are etched when they are irradiated with light of a mercury lamp; the spontaneous oxide film 6 is removed. The substrate 1 is transferred to a CVD apparatus; a tungsten film 7 is filled into the contact hole 5. Thereby, an interconnection layer which is uniform and whose contact resistance is small is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to reducing contact resistance.

(Prior Art) In recent years, large-scale integrated circuits (LSI) have come to be widely used in important parts of computers and communication equipment. These LSIs are manufactured by integrating a large number of active elements or passive elements on a semiconductor substrate several millimeters square by connecting them to form an electric circuit.

This integration is progressing more and more, and research into miniaturizing and increasing the density of component elements is progressing rapidly, and the production of ultra-highly integrated circuits is also being put into practical use.

Such high integration of LSIs is brought about by miniaturization of elements. For example, IMDRAM, 256KSR
VLSIs such as AM are manufactured using design standards of 1 to 1.26 m, and are being manufactured using submicron design standards for the purpose of higher integration.

However, this miniaturization is making it increasingly difficult to manufacture VLSIs. Taking wiring technology as an example, the reduction in design standards reduces the wiring width, but as the number of active elements increases, it is necessary to route thinner and more complex wiring, and contact holes also become deeper and thinner. There is a tendency.

For this reason, there is a problem in that the conventionally used aluminum alloy wiring formed by the sputtering method cannot provide sufficient coverage.

This is because the film thickness becomes thinner at the bottom of the connection hole due to a phenomenon called shadowing.

In addition, the overhang shape of the aluminum wiring also causes so-called "holes" to occur when an insulating film is formed on the aluminum wiring. When forming multilayer wiring, "su" also deteriorates the processing accuracy of the upper layer. As described above, with the miniaturization of elements, a problem arises in that the reliability of aluminum wiring decreases.

Therefore, various efforts have been made to improve the reliability of aluminum wiring.

One of the wiring structures is to use aluminum-based general wiring in the horizontal part of the wiring, and to use buried wiring in which tungsten, aluminum, or the like is buried in contact holes in the vertical part.

This wiring structure is shown in FIG.

In this wiring structure, an aluminum-based first wiring layer 113 is formed on an insulating layer 112 formed on the surface of a semiconductor substrate 111, an insulating film 114 covering the upper layer is opened, and a connection hole 115 is selected. A tungsten film 118 is embedded by a CVD method or the like, and a second wiring layer 119 formed above the second wiring layer 119 and the first wiring layer 113 are connected via this tungsten film 118.

According to this wiring structure, since the contact hole is filled with the W film, problems such as step breakage are solved compared to general wiring in which aluminum wiring directly extends.

However, this wiring structure also has problems.

This is a tungsten film 118 formed by selective CVD method or the like.
This is a problem with the natural oxide film that is formed on the substrate surface prior to the formation of the oxide film.

For example, the selective CVD method for tungsten W uses a mixed gas of a W halide such as tungsten hexafluoride WF6 and a reducing agent such as hydrogen H2 or silane SH4 as a raw material gas.
This method uses a low-pressure CVD method to grow a W film only on the surface of a conductor such as an aluminum alloy film, and does not form it on an insulating film such as a silicon oxide film. It has been found that the natural oxide film on the surface plays an important role in the characteristics during W deposition and the electrical characteristics between the deposited W and the underlying conductor.

In the VLSI process, when moving from one process to the next, the substrate must be transported in the atmosphere. At this time, the conductor film existing on the substrate surface is oxidized by oxygen in the atmosphere, and a natural oxide film grows on the surface.

That is, normally, elements are formed in a substrate, an insulating film is deposited, and a connection hole or interlayer connection hole is formed for contacting the element region in the substrate or the lower wiring region, and then the connection hole or the interlayer connection hole is formed. Selected CV for interlayer connection hole
A method of forming a D film is used. In reality, after forming connection holes or interlayer connection holes, a resist stripping process and a surface cleaning process are performed.
200: According to 1), the process proceeds in the order of removing the natural oxide film in the W film forming area, cleaning with pure water, drying steps, and placing the substrate in a CVD furnace. However, even with this method, the substrate is exposed to the atmosphere again in the pure water cleaning and drying steps after the dilute hydrofluoric acid treatment, so there is a problem in that a natural oxide film grows again on the surface of the metal region.

When attempting to deposit a W film on a substrate on which this natural oxide film was formed, phenomena such as the W film not being able to grow uniformly, the deposition reproducibility not being achieved, and the contact resistance becoming extremely high were observed. Therefore, in order to solve this problem, contact holes 115 are formed in the silicon oxide layer 114 in order to clean the substrate surface without exposing it to the atmosphere and to minimize the growth of the natural oxide film. After exposing the first wiring layer 113, the natural oxide film on the surface of the first wiring layer 113 is removed by dry etching using, for example, chlorine gas, and the upper conductor layer is removed by transporting under reduced pressure. A method of forming embankments has been proposed.

However, in dry etching using a halogen-based gas, a large amount of halogen atoms remain on the surface of the underlying conductor.

These remaining halogen atoms increase the contact resistance between conductors, accelerate corrosion of aluminum alloy wiring, and become a cause of decreased wiring reliability. In addition, if a large amount of halogen atoms remain on the surface of the underlying conductor, selective CVD of the metal film may cause abnormal growth such as local growth of the metal film on the surface of the underlying conductor or growth with a changed phase. The problem was that it caused

(Problems to be Solved by the Invention) In this way, selective CVD can be used to
In order to maintain good contact resistance with the second wiring layer which is selectively formed on the wiring layer through contact holes etc., after forming the contact holes and prior to the growth of the wiring layer in Section 2, halogen gas is added. When dry etching is performed, atomic atoms remain on the surface of the first wiring layer, causing corrosion of the first wiring layer, abnormal growth during growth of the second wiring layer, etc. There was a problem.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a method for reducing the contact resistance of a wiring layer and forming highly reliable electrode wiring.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the method of the present invention, prior to forming a second conductor layer so as to be in contact with the substrate surface or a conductor layer such as a first wiring layer, while irradiating the second conductor layer with light, , exposing the surface on which the second conductor layer is formed, that is, the surface of the substrate or the surface of the conductor layer such as the first wiring layer, to a mixed gas atmosphere consisting of hydrogen gas and a gas containing at least one type of halogen atom. There is.

(Function) According to the method of the present invention, the surface on which the second conductor layer is formed is exposed to a mixed gas atmosphere consisting of hydrogen gas and a gas containing at least one type of halogen atom while irradiating light. light promotes the activation of halogens,
Natural oxide film can be etched well.

In this case, compared to RIE, no active species are implanted into the substrate and no halogen is physically left on the surface.

Furthermore, since the reaction surface is irradiated with light, desorption of reaction products is also promoted. Therefore, compared to down-flow one-type plasma etching, there is an effect that halogen is less likely to remain on the surface.

By the way, the above surface etching reaction proceeds as follows.

Chain initiation reaction H2→2H (1) AX+λ→A×X (2) A: Metal X: Halogen atom λ: Light AX: Gas-phase compound chain growth reaction containing halogen atom H+AX-4X+AH or HX+A (3)
→HX+H(4) A+H2→AH+H(5) Chain termination reaction 2 H-" H2(6) A+X→AX (7) Therefore, H
By controlling the concentrations of 2 (hydrogen) and AX (a gas phase compound containing a halogen atom), the halogen atom concentration can be controlled.

Furthermore, since the chain is instantaneously stopped by stopping the supply of H2 or AX, the halogen atom concentration can be easily controlled.

By controlling the halogen atom concentration in this manner, it is possible to remove the natural oxide film and prevent halogen atoms from remaining on the surface of the conductor layer.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Example 1 In this example, a tungsten film is formed by selective CVD in a contact hole formed on a diffusion layer formed on the surface of a silicon substrate via an insulating film.

First, as shown in Figure 1(a), p of the specific resistance 5Ω
Forming an element isolation insulating film 2 on the surface of a mold silicon substrate 1,
Form an element region.

Thereafter, as shown in FIG. 1(b), arsenic ions are implanted and activated to form a diffusion layer 3. At this time, a natural oxide film 6 is formed on the surface of the diffusion layer.

Furthermore, as shown in FIG. 1C, a silicon oxide film 4 is formed by CVD or the like.

Then, as shown in FIG. 1(d), a contact hole 5 is formed in the silicon oxide film 4 using a conventional photolithography method and a reactive ion etching (RIE) method, and the resist is removed using oxygen plasma. Peel and remove. At this time, a natural oxide film 6 is formed on the surface of the diffusion layer 3 at the bottom of the contact hole 5.
is formed.

The substrate with the contact holes 5 formed in this way was placed in a vacuum container, and the hydrogen flow rate was 200 cc/1n.

Chlorine (C1: maximum absorption wavelength 340 nm) flow rate 50cc
/win, pressure 5 Q II Torrm gas atmosphere is formed, 500W mercury lamp (wavelength 254, 313,
Etching was performed for 200 seconds while irradiating with light (365 ns) (FIG. 1(e)). By this etching, the diffusion layer is etched at an etching rate of 20 people/in, and the silicon oxide is etched at an etching rate of 70 people/a+in. In this way, the natural oxide film is removed by etching.

Here, the light may be irradiated in the direction of arrow 1 so as to be parallel to the substrate, or in the direction of arrow 2 so as to be perpendicular to the substrate, as shown in the conceptual diagram of the device in Fig. 2. Although irradiation may be performed, the etching speed is higher when irradiated in the direction of arrow 2, and is approximately twice that when irradiated in the direction of arrow 1.

Here, irradiation was performed in the direction of arrow 2.

Then, as shown in Figure 1 (), the substrate after surface etching was transferred to a CVD apparatus without exposing it to an oxidizing atmosphere, the substrate temperature was set to 350°C, and tungsten hexafluoride (
WFs) Flow rate 10 cc/sin, silane flow In 10
Tungsten film 7 is buried in the contact hole at cc/l1lin, pressure of 10 mTorr, and deposition rate of 0°2μ+IlZ.

In this way, it is possible to form a uniform wiring layer with low contact resistance.

In addition, in the surface etching process shown in FIG. 1(e), the etching rate of the silicon oxide film and the amount of residual chlorine on the substrate surface after treatment when the hydrogen flow rate was varied from 0 to 1000 cc/mln. The relationship between X-ray photoelectron spectroscopy (X
Figure 3 shows the results obtained by determining 71?3 using the PS) method.

As a result, it can be seen that when the hydrogen flow rate is 0, a large amount of residual chlorine is observed, but when the hydrogen flow rate is set to 200 cc/ml, the residual chlorine decreases rapidly.

Further, when the hydrogen flow rate is less than 100 cc/win, defects such as abnormal growth of β-phase tungsten or increased resistance may occur due to chlorine atoms remaining on the surface.

Furthermore, in Example 1, chlorine gas was irradiated with light and the process was carried out at room temperature without temperature control.
By heating to 0 to 600 DEG C., as shown in FIG. 4, it becomes possible to increase the etching rate and further shorten the etching time.

In addition, in the first embodiment, chlorine gas was used as the etching gas, but it is only necessary to remove the natural oxide film, and HCI
, Br2. HBr, NF3. Gas phase compounds containing other halogen atoms such as BCl3 and SF6 may also be used.

Furthermore, the partial pressure of the gas phase compound containing halogen atoms is diluted with a rare gas such as argon or helium, nitrogen, etc., and the etching rate during etching by light irradiation is slowed down. You may also do so.

Further, although a mercury lamp is used as a light source, a halogen lamp, an ultraviolet laser, or the like may also be used.

Further, in the above embodiments, the formation of a contact to an n-type diffusion layer was explained, but it is also applicable to the formation of a contact to a type diffusion layer formed by implantation of boron (B) ions, etc. Not even.

Example 2 Next, a second embodiment of the present invention will be described.

In this example, the hydrogen flow fjk in which abnormal growth occurred in Example 1
Even in the case of 100 cc/win or less, hydrogen plasma treatment is performed after etching with hydrogen and chlorine gas to remove chlorine atoms on the surface and form a wiring layer with low contact resistance. .

That is, after forming the contact hole 5 according to the steps shown in FIG. 1(a) to FIG. 1(d), a surface etching step as shown in FIG. 1(r) is performed at a hydrogen flow rate of 100 cc/w.
After etching with hydrogen and chlorine gas, hydrogen 500 cc/ll1in, pressure 2011T
Orr s High frequency power 100W, substrate bias -100
V, hydrogen plasma treatment was performed for a treatment time of 90 seconds. As a result of measuring the surface of the substrate after this hydrogen plasma treatment by XPS, no chlorine was detected, indicating that chlorine atoms were removed.

Then, as shown in FIG. 1(f'), the surface-etched substrate was transferred to a CVD apparatus without being exposed to an oxidizing atmosphere, the substrate temperature was set to 350°C, and the tungsten hexafluoride (WF6) flow rate was 10 cc/cm. min, silane flow rate 10
The tungsten film 7 is buried in the contact hole at cc/1n, pressure 10 raTorr, and deposition rate 0° 2 μm/min.

In this way, the tungsten film 7 can be buried well without abnormal growth, and a uniform wiring layer with low contact resistance can be formed.

Note that even in this hydrogen plasma processing step, the processing time can be shortened by irradiating the plasma or the substrate with 500 W mercury lamp light or the like.

Further, in this hydrogen plasma treatment step, hydrogen may be diluted with a rare gas such as argon.

Example 3 In Example 2, residual chlorine atoms were removed using hydrogen plasma generated by high-frequency discharge, but hydrogen plasma generated by microwave discharge may also be used.

That is, in the same manner as in Example 2, after photo-etching with a mixed gas of hydrogen gas and chlorine gas, as shown in the conceptual diagram of the apparatus in FIG. , hydrogen plasma generated with microwave power of 50 W was transported onto the substrate and processed. As a result of XPS measurement of the substrate surface after this hydrogen plasma treatment, no chlorine atoms were detected, indicating that chlorine atoms were removed by the hydrogen plasma treatment.

Then, in exactly the same manner as in Example 2, as shown in FIG. )Flow rate 10 cc/a+in
, silane flow 17110 cc/1n, pressure 10 a+T
The tungsten film 7 is buried in the contact hole at a deposition rate of 0.2 μI11/min.

In this way, the tungsten film 7 can be buried well without abnormal growth, and a uniform wiring layer with low contact resistance can be formed.

Note that even in this hydrogen plasma processing step, the processing time can be shortened by irradiating the plasma or the substrate with 500 W mercury lamp light or the like.

Further, in this hydrogen plasma treatment step, hydrogen may be diluted with a rare gas such as argon.

Example 4 Next, as a fourth example, a method of performing surface etching by adding mercury vapor as a photosensitizer when etching is performed while irradiating light will be described.

That is, after forming the contact hole 5 in the same manner as in the above embodiment, when photo-etching is performed using a mixed gas of hydrogen gas and chlorine gas, the hydrogen gas is heated to a mercury reservoir (25° C.).
Hydrogen flow rate 100 cc/min as mercury vapor-containing gas through a contact area 2 cj ).

Chlorine gas flow rate 50 cc/1n, pressure 50a+Torr
Under these conditions, while irradiating with 5000W mercury lamp light,
Etching is performed for 200 seconds.

The surface of the substrate after this surface etching treatment was subjected to Jl determination using XPS, and the chlorine atom concentration was found to be low.

This is because chlorine is activated by energy transfer from mercury that has been activated by absorbing light (photosensitization reaction), and the concentration of chlorine active species relative to the chlorine flow rate is significantly higher than in a system that does not contain mercury. This is thought to be because most of the chlorine atoms become active species and contribute to surface etching, so the residual chlorine atoms are significantly reduced.

Then, in exactly the same way as in the previous embodiment, as shown in FIG. Embed.

In this way, the tungsten film 7 can be buried well without abnormal growth, and a uniform wiring layer with low contact resistance can be formed.

In this example, chlorine gas was used as the etching gas, but it is sufficient that the natural oxide film is removed.
CI, Br2. HBr, NF 3
, BCl3, SF6, and other gas phase compounds containing halogen atoms may also be used.

In addition, a chemical compound containing a halogen atom with argon,
The partial pressure of the gas phase compound containing halogen atoms may be controlled by diluting it with a rare gas such as helium, nitrogen, etc., and the etching rate during etching by light irradiation may be slowed down.

Furthermore, mercury as a photosensitizer may be guided onto the substrate using not only hydrogen but also a rare gas such as argon, nitrogen, etc. as a carrier.

Example 5 In Examples 1 to 4 described above, the formation of a conductor layer in a contact hole has been described, but ITI can also be applied when a metal layer is pasted on the surface of a diffusion layer. This example will be explained.

That is, as shown in FIG. 6(a), an element isolation insulating film 12 is formed on the surface of a p-type silicon substrate 11, an element region is formed, and arsenic ions are implanted and activated to form a diffusion layer. form 3. At this time, a natural oxide film 16 is formed on the surface of the diffusion layer.

Thereafter, as shown in FIG. 6(b), this substrate 11 was placed in a vacuum container in exactly the same manner as in Example 1, and hydrogen flow rate was 200 cc/ml, chlorine (C1: maximum absorption wavelength 3).
40 nm) Flow rate 50 cc/1n, pressure 50 mTor
Etching was performed for 200 seconds while irradiating light from a 500 W mercury lamp (wavelength: 254, 313, 365 tv) under a rm cc/1n atmosphere.

By this etching, the diffusion layer is etched at an etching rate of 20 people/11 inch, and the silicon oxide is etched at an etching rate of 70 people/11 inch.
Etched at an etching speed of 10+In.

In this way, the natural oxide film 16 is removed by etching.

Furthermore, as shown in FIG. 6(C), and FIG.
The substrate after surface etching was transferred to a CVD apparatus, the substrate temperature was 350°C, the tungsten hexafluoride (WFe) flow rate was 10 cc/ml, and the silane flow rate was 10 cc/ml. 10cc/e+in
Tungsten@17 is selectively formed on the surface of this diffusion layer 13 at a pressure of 10 mTorr and a deposition rate of 0.2 μm/min.

In this way, it is possible to form a uniform tungsten film 17 without generating an abnormal bottom length.

Embodiment 6 Furthermore, the present invention is applicable to multilayer wiring.

A case will be described in which multilayer wiring is performed as Example 1P16.

First, as shown in FIG. 7(a), a p-type silicon substrate 2
After forming a desired element region (not shown) on the first surface, a silicon oxide film 22 is formed, and then a first wiring layer 22 is formed.
An aluminum alloy (Al-3t) film as No. 3 is formed.

Thereafter, as shown in FIG. 7(b), this aluminum alloy film is patterned using a normal photolithography method and a reactive ion etching (RIE) method, and is then patterned as an interlayer insulating film 24 using a CVD method. A silicon oxide film is formed.

Then, as shown in FIG. 7(C), contact holes 25 are formed in this silicon oxide film 24 by ordinary photolithography and reactive ion etching, and the resist is stripped and removed by oxygen plasma. At this time, a natural oxide film 26 is formed on the surface of the first wiring layer 23 at the bottom of the contact hole 25.

The substrate with contact holes 25 formed in this manner was placed in a vacuum container, and water lf: flow rate was 500 cc7 ml.

Chlorine flow rate 50 cc/ff1in, pressure 50 n+To
rrm gas atmosphere and a 500W mercury lamp (
Etching was performed for 300 seconds without irradiating light with a wavelength of 254°313.365 nm (FIG. 7(d)).

Through this etching, the aluminum alloy film constituting the first wiring layer 23 is etched at an etching rate of 10 people/1n, and the silicon oxide is etched at an etching rate of 70 people/ml. In this way, the natural oxide film is removed by etching.

Then, as shown in FIG. 7(e), the substrate after surface etching is transferred to a CVD apparatus without exposing it to an oxidizing atmosphere, the substrate temperature is set to 350°C, and tungsten hexafluoride (
WF6) Flow rate: 110 cc/min, silane flow rate: 10
cc/a+in, pressure 10III Tor", deposition rate 0
A tungsten film 27 is buried in the contact hole by 52 μIIZ. Then, if necessary, this tungsten film 2
A second wiring layer 28 is formed by depositing an aluminum alloy film or the like on the upper layer so as to be in contact with the wiring layer 7 and patterning it.

In this way, it is possible to form a multilayer interconnection layer that is uniform and has low contact resistance without abnormal growth.

In the above example, the case where an aluminum alloy was used as the first wiring layer was explained, but even when polycrystalline silicon is used, good contact resistance can be obtained by performing surface etching under the same conditions. It is possible. In this case, during surface etching, the polycrystalline silicon film constituting the first wiring layer 23 is etched at an etching rate of 30 A7sin, and the silicon oxide is etched at an etching rate of 70 A7sin.
Etching is performed at an etching speed of /min. In this case, good contact resistance can be obtained by subsequently forming a tungsten film through hydrogen plasma treatment.

Although aluminum and polycrystalline silicon were used as the first wiring layer, materials to be processed include tungsten-titanium alloys, metals such as molybdenum, tungsten, titanium, copper, molybdenum silicide, tungsten silicide, titanium silicide, etc. Metal silicide, metal nitride such as tungsten nitride or titanium nitride, or amorphous silicon may be used, and furthermore, group III semiconductor OE, G such as silicon or germanium may be used.
MV group compound semiconductors such as aAs and InP may also be used.

It is also applicable to cases where two or more types of conductors are exposed at the same time.

Furthermore, tungsten was used as the second conductor layer, but
Any conductive layer may be used, such as polycrystalline silicon thin film, amorphous silicon thin film, metal thin film, alloy NM! , metal silicide 7'JH1 metal nitride/l! ! A film or the like may also be used. moreover,
The forming method is not limited to the CVD method, and may also be applied to a sputtering method.

Furthermore, any gas containing halogen atoms may be used as long as it generates active species that can etch the natural oxide film on the surface of the object to be processed by photoexcitation.

Other modifications can be made without departing from the gist.

〔Effect of the invention〕

As explained above, according to the method of the present invention, prior to forming the second conductor layer so as to contact the surface of the substrate or the conductor layer such as the first wiring layer, while irradiating light, Since the surface on which the second conductor layer is formed is exposed to a mixed gas atmosphere of hydrogen gas and a gas containing at least one type of halogen atom, it is possible to lower the contact resistance.

[Brief explanation of the drawing]

1(a) to 1(f) are diagrams showing the process of forming a wiring layer in the first embodiment of the present invention, and FIG. 2 is a conceptual diagram of an apparatus for the surface etching process in the first embodiment. , FIG. 3 is a diagram showing the relationship between the hydrogen flow rate, the amount of residual chlorine, and the etching rate of silicon oxide in the same surface etching process, and FIG. 4 is a diagram showing the relationship between the substrate temperature and etching rate in the same surface etching process. FIG. 5 is a conceptual diagram of an apparatus for microwave-excited hydrogen plasma processing according to the fourth embodiment, and FIGS. 6(a) to 6(C) illustrate the manufacturing process of a semiconductor device according to the fifth embodiment of the present invention. Figures 7(a) to 7
FIG. 8E is a diagram showing a manufacturing process of a semiconductor device according to a sixth embodiment of the present invention, and FIG. 8 is a diagram showing an example of a wiring structure. 1... Silicon substrate, 2... Element isolation insulating film, 3.
... Diffusion layer, 4... Silicon oxide film, 5... Contact hole, 6... Natural oxide film, 7... Tungsten film, 11... Silicon substrate, 12... Element isolation insulating film , 13... Diffusion layer, 16... Natural oxide film, 17...
・Tungsten film, 21...Silicon substrate, 22...
・Silicon oxide film, 23... Aluminum alloy film, 2
4... Silicon oxide film, 25... Interlayer connection hole, 26
...Natural oxide film, 27...Tungsten film, 28.
...Second wiring layer, 111...Semiconductor substrate, 112.
...Insulating layer, 113...First wiring layer, 114...
Insulating film, 115... Connection hole, 118... Tungsten film, 11... Second wiring layer. 144- Light (Direction 2) +++ Figure 2 Figure 5 Figure 6 Figure 6 Figure 7 Figure 8

Claims (3)

[Claims] (1) In a method for manufacturing a semiconductor device including a step of forming a second conductor layer in contact with the substrate surface or a conductor layer such as a first wiring layer, prior to forming the second conductor layer, , a surface treatment step of exposing the substrate or the surface on which a conductive layer such as the first wiring layer is formed in a mixed gas atmosphere containing hydrogen gas and a gas containing at least one type of halogen atom while irradiating with light. A method for manufacturing a semiconductor device, characterized in that: (2) The method for manufacturing a semiconductor device according to claim (1), wherein the second wiring layer forming step is a CVD step. (3) In the surface treatment step, the mixed gas atmosphere contains atoms or molecules that become a photosensitizer that causes a photosensitization reaction and increases the concentration of active species. (1) A method for manufacturing a semiconductor device according to the above.