JPH04254993A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To greatly reduce peak current at the time of data transfer and to prevent malfunction in peripheral circuits due to noise generated with the peak current. CONSTITUTION:In the semiconductor memory which is formed by connecting in parallel a plural number of data transfer transistors between a bit line and a data register, transfer transistor group 5 in an upper side including a plural number of data transfer transistors 9-12 as data transfer means and the data transfer transistor group 4 in the upper side including the data transfer transistors 13-16 as a sub data transfer transistor group are provided. In order that the data transfer by these sub data transfer transistor groups may not be performed within the same time zone, a data transfer time control is performed via a data transfer control means including control parts 6, 7 and discriminating control part 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a data transfer function between a memory cell and a data register, such as a dual-port memory.

0002

2. Description of the Related Art Conventional semiconductor memories, such as dual-port memories, which require data transfer between memory cells and data registers, have a sensing system as shown in FIG. Amplifier group 1
and the data register group 2, a plurality of N channels M
It is configured with a transfer transistor group 3 including OS transistors 17, 18, ..., 19, 20, and each N-channel MOS for transfer included in the transfer transistor group 3.
A data transfer start signal Φ1 is applied to the gate of the transistor.
is input and the data transfer start signal Φ1 becomes High, each N-channel MOS transistor included in the transfer transistor group 3 is activated, data transfer is performed, and all the data included in the data register group 2 is Generally, register data is rewritten at the same time.

0003

[Problems to be Solved by the Invention] In the conventional semiconductor memory described above, when the transfer transistor group 3 is activated and the data on the bit line is transferred to the data register, the data in all the data registers is transferred simultaneously. Therefore, if the data in all data registers changes from Low to High or from High to Low, the peak current at that point will become extremely large, and the accompanying noise will cause damage to the surroundings. The drawback is that malfunctions occur in the circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that suppresses the peak current value during data transfer, eliminates noise caused by this, and prevents malfunctions in peripheral circuits.

[0005]

[Means for Solving the Problems] A semiconductor memory of the present invention is a semiconductor memory formed by connecting a plurality of data transfer transistors in parallel as data transfer means between a bit line and a data register. The data transfer means includes a plurality of sub data transfer transistor groups formed by dividing the plurality of data transfer transistors into a plurality of sub transistor groups, and data transfer by the sub data transfer transistor groups. The data transfer control unit is configured to include data transfer control means for controlling data transfer time so that data transfers are not performed in the same time zone.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a sense amplifier group 1, a data register group 2, a transfer transistor group 3 including a lower transfer transistor group 4 and an upper transfer transistor group 5, and a control section. 6 and 7, and a determination circuit section 8. Note that the lower side transfer transistor group 4 includes a plurality of data transfer N-channel MOS transistors 13, 14, . . . , 15, 16, and the upper side transfer transistor group 5 includes the same includes a plurality of N-channel MOS transistors 9, 10, . . . , 11, 12 for data transfer.

As is clear from FIG. 1, the important difference between the present invention and the conventional example is that the transfer transistor group 3 is divided into a lower transfer transistor group 4 and an upper transfer transistor group 5. Gate signals Φ3 and Φ4 input to the gates of N-channel MOS transistors for data transfer included in each are individually supplied from corresponding control units 7 and 6, respectively.

First, during a data transfer cycle, it is determined whether the first required data register belongs to the lower side or the upper side after data transfer via the address signal Ai input to the determination circuit section 8. The judgment is made in the judgment circuit section 8. Based on this determination result, the determination circuit section 8
A determination signal Φ2 is outputted from the control section 6 and sent to the control sections 6 and 7. In response to this determination signal Φ2, control units 6 and 7 generate gate signals Φ4 and Φ3, respectively.
is generated. On the other hand, a data transfer start signal Φ1 is also input to the control units 6 and 7. When the judgment signal Φ2 outputted from the judgment circuit section 8 is Low, it means that the data register that is required first belongs to the lower side, and therefore, the data transfer start signal Φ1 is activated in one shot. When it becomes High, the gate signal Φ3 outputted from the control unit 7 becomes High in one shot under the control of this data transfer start signal Φ1, and the corresponding transistor group 4 for lower side transfer is activated, and the gate signal Φ3 for lower side transfer is activated. N-channel MOS included in transistor group 4
The transistors 13 to 16 are all activated, and predetermined data transfer is performed via the lower transfer transistor group 4. After that, the gate signal Φ3 corresponding to the lower side
When becomes Low, next, the gate signal Φ4 corresponding to the upper side becomes High in one shot, the corresponding upper side transfer transistor group 5 is activated, and the N-channel type included in the upper side transfer transistor group 5 All of the MOS transistors 9 to 12 are activated, and predetermined data transfer is performed via the upper-side transfer transistor group 5.

What is shown in FIGS. 2(a) and 2(b) is
FIG. 2A is a waveform diagram showing the data transfer start signal Φ1, the gate signal Φ3 corresponding to the lower side, and the gate signal Φ4 corresponding to the upper side in the embodiment, and FIG. 2(a) shows that the determination signal Φ2 is A waveform diagram in the case of Low is shown.

On the other hand, when the determination signal Φ2 is High, it means that the data register that is needed first belongs to the upper side. Therefore, the data transfer start signal Φ1 goes High in one shot. Then, under the control of this data transfer start signal Φ1, the gate signal Φ4 output from the control unit 6 becomes High in one shot.
Then, the corresponding upper-side transfer transistor group 5 is activated, all N-channel MOS transistors 9 to 12 included in the upper-side transfer transistor group 5 become operational, and through the upper-side transfer transistor group 5, Predetermined data transfer is performed. Then, after that, when the gate signal Φ4 corresponding to the upper side becomes Low, the gate signal Φ3 corresponding to the lower side becomes Hi in one shot.
gh, the corresponding lower transfer transistor group 4 is activated, all N-channel MOS transistors 13 to 16 included in the lower transfer transistor group 4 become operational, and the , a predetermined data transfer is performed.

0012

As explained above, the present invention divides a data transfer transistor group into a plurality of sub-data transfer transistor groups, and divides the data transfer transistor group into a plurality of sub-data transfer transistor groups. N-channel MOS
By inputting the gate signals to the transistors via the data transfer start signal so that they do not overlap between the sub-data transfer transistor groups, it is possible to significantly reduce the peak current during data transfer. This has the effect of being able to prevent malfunctions in peripheral circuits due to noise caused by this peak current.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing an example of operation in this embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

1 Sense amplifier 2 Data register group 3 Transfer transistor group 4 Lower side transfer transistor group 5 Upper side transfer transistor group 6,7 Control section 8 Judgment circuit section

Claims (2)

[Claims] [Claim 1] Between the bit line and the data register,
In a semiconductor memory formed by connecting a plurality of data transfer transistors in parallel as a data transfer means, the data transfer means is formed by dividing the plurality of data transfer transistors into a plurality of sub-transistor groups. a plurality of sub data transfer transistor groups, and data transfer control means for controlling data transfer time so that the data transfers by the sub data transfer transistor groups are not performed in the same time zone. semiconductor memory. 2. The semiconductor memory according to claim 1, wherein said data transfer means is formed by dividing said plurality of data transfer transistors into two sub-transistor groups, upper and lower.