JPH04254766A - Envelope detection circuit - Google Patents

Abstract

PURPOSE:To eliminate the need of changing circuit parts in accordance with a change in an AC component contained in input signals by successively converting the input signals into digital signals and, only when the input signals largely change, converting the digital signals into analog signals. CONSTITUTION:When signals are inputted from a terminal 1, an A/D converter 10 performs A/D conversion in accordance with a clock signal 14 and outputs the converted digital signals from terminals D0-D5. The higher-rank four bits of the digital signals are inputted to the terminals A0-A3 of a comparator 12 and, at the same time, to the terminals D0-D3 of the first latch 11. Upon receiving the next clock, the latch 11 outputs data to the terminals B0-B3 of the comparator 12. Therefore, the comparator 12 compares the data of the terminals A0-A3 with the preceding data of the terminals B0-B3. When both data are different from each other, the higher-rank four bits of the digital signals are different, namely, the input signals largely change. In such case, the data of the second latch 16 are converted into analog signals by means of a D/A converter 17.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] This invention is applicable to, for example, FM waves, AM waves, etc.
The present invention relates to an envelope detection circuit for electrical signals such as waves, digitally modulated waves, or phase modulated waves.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional envelope detection circuit disclosed in, for example, Japanese Unexamined Patent Publication No. 2-156164. In the figure, 1 is a signal input terminal into which a signal to be enveloped is to be detected, and 2 is a signal input terminal 1.
3 is a full-wave rectifier circuit that full-wave rectifies the output signal of the small-signal amplifier 2; 4 is a smoothing capacitor that smoothes the full-wave rectified signal; 5 is a smoothed signal. A first V-I converter converts a signal from voltage to current; 6 is a coupling capacitor that passes only the alternating current component of the signal smoothed by the smoothing capacitor 4; and 7 converts the alternating current component that has passed through the coupling capacitor 6 from voltage to current. A second V-I converter. The second V-I converter 7 is configured to convert the current into a current having a sign opposite to that of the first V-I converter 5. 8 is an I that performs current-voltage conversion of the sum of the output currents of the first VI converter 5 and the second VI converter 7.
-V converter. The output of the IV converter 8 is an envelope detection signal, which is output from an envelope detection signal output terminal 9.

Next, the operation of the conventional envelope detection circuit shown in FIG. 4 will be explained with reference to the waveform diagram shown in FIG. In FIG. 5, (a) is the input signal waveform, (b)
is a full-wave rectified waveform, (c) is the first VI conversion current waveform,
(d) shows the second VI converted current waveform, and (e) shows the current sum signal. First, a signal whose envelope is to be detected as shown in FIG. 5A is inputted to the signal input terminal 1 from an external device (not shown). This input signal is amplified by the small signal amplifier 2, and then full-wave rectified by the full-wave rectifier circuit 3, resulting in the signal shown in FIG. 5(b). The alternating current component of this full-wave rectified signal is smoothed by the smoothing capacitor 4, and further converted into a current by the first VI converter 5, resulting in the signal shown in FIG. 5(c).

On the other hand, the signal smoothed by the smoothing capacitor 4 is also input to the coupling capacitor 6, and only the alternating current component is extracted. This AC component is input to the second VI converter 7, where it is converted into a current and becomes the signal shown in FIG. 5(d). At this time, as described above, the first V-I converter 5 and the second V-I converter 7 convert the currents to have opposite signs, so as shown in FIGS. 5(c) and 5(d). The alternating current components of the signals are out of phase with each other. Subsequently, I-V
The converter 8 includes the first VI converter 5 shown in FIG. 5(c).
A current signal indicating the sum of the output of the V-I converter 7 and the output of the second VI converter 7 shown in FIG. 5(d) is input. This sum signal becomes the signal shown in FIG. 5(e) because the alternating current components cancel each other out. Furthermore, this sum signal is sent to the I-V converter 8
The signal is converted into a voltage signal by the envelope detection signal output terminal 9 and output as an envelope detection signal. Note that the capacitances of the smoothing capacitor 4 and the coupling capacitor 6 are selected depending on the AC component, and the conversion rate and input/output level change rate of each VI converter are set to match.

[0005]

[Problems to be Solved by the Invention] Since the conventional envelope detection circuit is configured as described above, the capacitance of the smoothing capacitor 4 and the coupling capacitor 6 is adjusted depending on the AC component contained in the input signal to be envelope-detected. There was a problem in that it was necessary to select the desired value, and it was also necessary to match the conversion rates and input/output level change rates of the first VI converter 5 and the second VI converter 7.

The present invention has been made to solve the above-mentioned problems, and even if the AC component contained in the input signal to be envelope-detected changes, the components within the envelope detection circuit are not changed. The purpose of this invention is to obtain an envelope detection circuit that only requires changing the operating conditions.

[0007]

[Means for Solving the Problems] An envelope detection circuit according to the present invention includes an A/D converter that sequentially converts an input signal to be envelope-detected into a digital signal, and a memory and output of the upper n bits of the digital signal. a comparator that compares the upper n bits of the digital signal with the previous n-bit digital value stored in the first latch and outputs a comparison result signal; and a comparator that outputs a comparison result signal, and all bits of the digital signal. a second latch that stores and outputs the stored digital value and changes the stored digital value only when the data compared by the comparator is different according to the comparison result signal; and the digital value output from the second latch. It is equipped with a D/A converter that converts the signal into an analog signal.

[0008]

[Operation] In this invention, the input signal is sequentially converted into a digital signal, the current and previous digital values of the upper n bits are compared, and only when the difference has changed by more than the alternating current component included in the input signal. By changing the envelope detection signal, the AC component contained in the input signal is erased while keeping the DC component intact.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and 1 and 9 are the same as those described above. 10 converts the input signal from the signal input terminal 1 into a digital value;
For example, it is a 6-bit A/D converter, and has an input terminal IN for input signals, an input terminal S for clock signals, and output terminals D0 to D5 for outputting digital signals. 1
1 in response to a clock signal or timing signal,
The upper 4 bits of the digital signal output from the A/D converter 10 are stored and sent to the output terminals Q0 to Q.
It is the first latch that outputs from Q3, and the output terminals Q0 to Q
3, it has input terminals D0 to D3, an input terminal T for a timing signal, and an input terminal R for a reset signal. 1
2 compares the upper 4 bits of the digital signal output from the A/D converter 10 with the previous 4-bit digital value output from the first latch 11, and compares the comparison result signals S1 and S2. Signal terminal (>) and (<
), and the comparison result signal terminal (>)
In addition to and (<), input terminals A0 to A3 and B0 to B3
have. Reference numeral 13 denotes an OR gate that takes the logical sum of the comparison result signals S1 and S2.

Reference numeral 14 denotes a clock signal input terminal to which a clock signal is inputted, which is used for determining the conversion timing of the A/D converter 10 and the latch and data output timing of the first latch 11, and 15 is a clock signal input terminal. This is an AND gate that performs the logical product of the signal and the output signal of the OR gate 13. 16 is a second latch that stores all 6 bits of the digital signal output from the A/D converter 10 and outputs this digital value from output terminals Q0 to Q5; , input terminal D0
~D5, has an input terminal T for a timing signal and an input terminal R for a reset signal. The output signal of the AND gate 15 is input to the input terminal T of the second latch 16, and the second latch 16 changes the stored digital value at this timing. 17 is a D/A converter that converts the digital value output from the second latch 16 into an analog signal, and the digital value input terminal D0
~D5, and an analog signal output terminal OUT. 18 is a reset signal input terminal to which a reset signal for initializing the data stored in the first latch 11 and the second latch 16 is input. Note that in FIG. 1, an operating power supply and a power supply connection circuit necessary for circuit operation are omitted.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be explained with reference to the waveform diagram in FIG. 2 and the timing chart in FIG. 3. First, a reset signal generated from an external device (not shown) is transmitted to the first latch 11 and the second latch 1 via the reset signal input terminal 18.
6, the first latch 11 and the second latch 16 are thereby reset, and all stored data is erased. In addition, a clock signal generated from an external device (not shown) is sent to the input terminal S of the A/D converter 10, the input terminal T of the first latch 11, and one of the AND gates 15 via the clock signal input terminal 14. Each is input to the input terminal. This clock signal has an appropriate frequency selected depending on the input signal to be envelope-detected.

Now, an input signal as shown in FIG. 2(a) is input to the input terminal IN of the A/D converter 10 via the signal input terminal 1.
shall be entered. The A/D converter 10 converts the input signal A when the clock signal changes from L level to H level (time t1, time t2,...) as shown in FIG.
/D conversion and output the converted digital signal to terminal D.
Output from 0 to D5. The upper 4 bits (data 1) of the digital signal A/D converted at time t1 are input to input terminals A0 to A3 of the comparator 12, and
It is also input to the input terminals D0 to D3 of the first latch 11.

After time t1, at time 2 when the clock signal, which once changed from H level to L level, changes from L level to H level, A/D converter 10 converts the input signal into a digital signal again, and converts the input signal into a digital signal. The upper 4 bits of the digital signal (data 2) are input to the input terminals A0~ of the comparator 12.
A3 and input terminals D0 to D3 of the first latch 11. Here, since A/D conversion takes some time, the data input to the input terminals D0 to D3 of the first latch 11 changes from data 1 to data 2 with a slight delay from time t2. Therefore, at time t2, the first latch 11
Since the data being input to the input terminals D0 to D3 is data 1, the first latch 11 inputs data 1 from the output terminals Q0 to Q3 in response to the change of the clock signal to the H level at time t2. Input terminals B0 to B of comparator 12
Output to 3. Therefore, the comparator 12 has input terminals A0 to
Data 2 input to A3 is compared with data 1 input to input terminals B0 to B3.

When these data are different, the upper 4 bits of the digital signals A/D-converted by the A/D converter 10 are different at times t1 and t2 (that is, when the input signals are compared (when the target is changing significantly). At this time, the comparator 12 outputs an H level comparison result signal S1 from the comparison result signal terminal (>) or (<).
, S2, and thereby the OR gate 13 outputs an H level signal. Furthermore, since the clock signal is already at H level, the output of the AND gate 15 changes to H level. Therefore, the second latch 16, to which the output signal of the AND gate 15 is input from the input terminal T, receives the data input to the input terminals D0 to D5, that is, at time t.
The digital signal A/D converted into data 2 (that is, the upper 4 bits are the same as data 2) is stored and output from output terminals Q0 to Q5. This digital signal is D/A
The signal is converted into an analog signal by the converter 17, and output as an envelope detection signal from the output terminal OUT.

On the other hand, when data 1 and data 2 compared by the comparator 12 are the same, the times t1 and t
2. When the upper four bits of the digital signal A/D converted by the A/D converter 10 are the same (that is, when the input signal has only a relatively small change). At this time, the comparison result signal terminals (>) and (<
), the H level comparison result signals S1 and S2 are not output, and the output signal of the OR gate 13 becomes L level. Therefore, the output signal of the AND gate 15 becomes L level, the data stored in the second latch 16 does not change, and the envelope detection signal output from the D/A converter 17 also does not change.

[0016] Thereafter, the same process is repeated. At this time, if the lower two bits of the A/D converter 10 are set to correspond to the amount of change in the alternating current component of the input signal, the alternating current component is ignored and the envelope detection signal output terminal 9 outputs the signal as shown in FIG.
The envelope detection signal shown in (b) will be output.

In the above embodiment, the A/D converter 10 is
The upper 4 bits of these bits are compared by the comparator 12, but depending on the accuracy and resolution of the envelope detection signal and the magnitude of the AC component of the input signal,
The number of bits of the /D converter 10 and the number of bits compared by the comparator 12 may be changed. In addition, although the envelope detection signal is an analog signal converted by the D/A converter 17, it is input to a computer etc. as a digital signal before being D/A converted, and another signal that can be controlled by this computer is input. The data may be output to a D/A converter, or may be displayed in a graph after waveform processing.

[0018]

As described above, according to the present invention, there is provided an A/D converter that sequentially converts an input signal into a digital signal, and a first A/D converter that stores and outputs the upper n bits of the digital signal.
a comparator that compares the upper n bits of the digital signal with the previous n-bit digital value stored in the first latch and outputs a comparison result signal;
a second latch that stores and outputs all bits of the digital signal and changes the stored digital value according to the comparison result signal; and a D/R that converts the digital value output from the second latch into an analog signal. A converter, which sequentially converts the input signal into a digital signal, and converts the input signal into a digital signal.
The current and previous digital values of the bit are compared, and the envelope detection signal is changed only when the difference between them is greater than the AC component included in the input signal, allowing the DC component included in the input signal to remain unchanged. Since the AC component is erased while maintaining the input signal, even if the AC component included in the input signal changes, the frequency of the clock signal or the number of bits to be compared can be changed without changing the components in the envelope detection circuit. This has the effect of providing an envelope detection circuit that requires only one.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of an embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of an embodiment of the present invention.

FIG. 4 is a configuration diagram showing a conventional envelope detection circuit.

FIG. 5 is a waveform diagram showing each signal in a conventional envelope detection circuit.

[Explanation of symbols]

10 A/D converter 11 First latch 12 Comparator 16 Second latch 17 D/A converter S1, S2 Comparison result signal

Claims (1)

[Claims] 1. An A/D converter that sequentially converts an input signal to be envelope-detected into a digital signal, a first latch that stores and outputs the upper n bits of the digital signal, and a first latch that stores and outputs the upper n bits of the digital signal. a comparator that compares n bits with the previous n-bit digital value stored in the first latch and outputs a comparison result signal; and a comparator that stores and outputs all bits of the digital signal and compares a second latch that changes the stored digital value only when the data compared by the comparator is different according to the result signal; and a second latch that converts the digital value output from the second latch into an analog signal. An envelope detection circuit equipped with a D/A converter.