JPH0425146A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0425146A JPH0425146A JP2130629A JP13062990A JPH0425146A JP H0425146 A JPH0425146 A JP H0425146A JP 2130629 A JP2130629 A JP 2130629A JP 13062990 A JP13062990 A JP 13062990A JP H0425146 A JPH0425146 A JP H0425146A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resistor
- power supply
- external device
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 238000012360 testing method Methods 0.000 abstract description 14
- 230000001133 acceleration Effects 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 235000004789 Rosa xanthina Nutrition 0.000 description 1
- 241000109329 Rosa xanthina Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路に関し、特に、外部装置を
用いなくても、加速試験時に必要な高温状態を得られる
ようにしたものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductor integrated circuits, and in particular, to a semiconductor integrated circuit that enables a high temperature state required during accelerated testing to be obtained without using an external device.
通常、半導体集積回路は、初期不良を発見するために、
高温状態で素子を動作させる加速試験が行われている。Normally, in order to discover initial defects in semiconductor integrated circuits,
Accelerated tests are being conducted to operate the device at high temperatures.
そして、従来、そのような加速試験番こおける半導体集
積回路の加熱には、オープン等の外部装置を利用してい
た。Conventionally, an external device such as an open circuit has been used to heat the semiconductor integrated circuit during such accelerated testing.
しかしながら、オープン等の外部装置を利用して高温状
態を得る従来の技術では、そのような外部装置が必要で
あるとともに、ＩＣチップの移動等の手間が増えて試験
に要する時間が長くなるので、コスト低減の妨げとなっ
ていた。However, with the conventional technique of obtaining a high temperature state using an external device such as an open circuit, such an external device is required, and the time required for testing increases due to the increased effort such as moving the IC chip. This was an impediment to cost reduction.
この発明は、このような従来の技術が有する未解決の課
題に着目してなされたものであり、外部装置を利用する
ことなく加速試験における高温状態を得ることができる
半導体集積回路を提供することを目的としている。The present invention has been made by focusing on the unresolved problems of the conventional technology, and an object of the present invention is to provide a semiconductor integrated circuit that can obtain a high temperature state in an accelerated test without using an external device. It is an object.
〔課題を解決するだめの手段］
上記目的を達成するために、本発明の半導体集積回路は
、回路が構成されたチップ内に又はこのチップに近接し
て発熱体を設けた。[Means for Solving the Problems] In order to achieve the above object, the semiconductor integrated circuit of the present invention has a heating element provided within the chip on which the circuit is configured or in the vicinity of the chip.
〔作用］
本発明にあっては、発熱体の発熱によって集積回路が加
熱されるから、加速試験に必要な温度を外部装置を利用
しなくても得られる。[Function] In the present invention, since the integrated circuit is heated by the heat generated by the heating element, the temperature required for accelerated testing can be obtained without using an external device.
〔実施例］ 以下、この発明の実施例を図面の簡単な説明する。〔Example] Embodiments of the present invention will be briefly described below with reference to the drawings.
第１図は本発明の第１実施例を示す図であり、ＩＣチッ
プ１の実装状態を示す平面図である。FIG. 1 is a diagram showing a first embodiment of the present invention, and is a plan view showing a state in which an IC chip 1 is mounted.
即ち、ＩＣチップ１は、図示しないパッケージ内の絶縁
体からなる基板２上に装着されるとともに、その周辺部
に複数のポンディングパッド３が設けられている。That is, the IC chip 1 is mounted on a substrate 2 made of an insulator in a package (not shown), and a plurality of bonding pads 3 are provided on the periphery thereof.
そして、基板２上には、端部がＩＣチップ１を取り囲む
ように複数の導体４が配線されていて、ＩＣチップ１の
ポンディングパッド３と導体４の端部とが、ワイヤ５を
介して接続されている。A plurality of conductors 4 are wired on the substrate 2 so that their ends surround the IC chip 1, and the bonding pads 3 of the IC chip 1 and the ends of the conductors 4 are connected via wires 5. It is connected.
つまり、ＩＣチップ１は、ワイヤボンディングによって
基板２上に実装されている。That is, the IC chip 1 is mounted on the substrate 2 by wire bonding.
なお、導体４の他端側は、パッケージの外側に突出し且
つ図示しない端子に接続される複数のピンに個別に導通
している。The other end of the conductor 4 is individually electrically connected to a plurality of pins that protrude outside the package and are connected to terminals (not shown).
従って、ＩＣチップ１への電源の供給や、ＩＣチップ１
内の論理回路等と外部装置との間のデータの送受信等は
、パッケージ外側に突出した図示しないピン、導体４．
ワイヤ５及びボンディングバンド３を介して行われる。Therefore, the supply of power to the IC chip 1 and the
Transmission and reception of data between logic circuits inside the package and external devices is carried out using pins and conductors (not shown) that protrude outside the package.
This is done via the wire 5 and the bonding band 3.
さらに、本実施例では、ＩＣチップ１内に、任意のボン
ディングバラＦ’３ａ及び３ｂ間を接続する発熱体とし
ての抵抗体６を設けている。Furthermore, in this embodiment, a resistor 6 is provided in the IC chip 1 as a heat generating element that connects arbitrary bonding roses F'3a and 3b.
ボンディングバンド３ａ及び３ｂは、ワイヤ５ａ、５ｂ
、導体４ａ、４ｂ及びパッケージ外側に突出した図示し
ないピン等を介して、電圧可変の外部電源７に接続可能
となっている。Bonding bands 3a and 3b are wires 5a and 5b.
It is possible to connect to an external power source 7 with a variable voltage via conductors 4a, 4b and pins (not shown) protruding to the outside of the package.
そして、ＩＣチップ１の加速試験を行う際には、抵抗体
６と外部電源７とを接続状態とし、外部電源７の電圧を
適宜上げて抵抗体６に電流を流して抵抗体６を発熱させ
、ＩＣチップ１の温度を」−昇させる。When performing an accelerated test on the IC chip 1, the resistor 6 and the external power supply 7 are connected, and the voltage of the external power supply 7 is increased appropriately to flow a current through the resistor 6 to cause the resistor 6 to generate heat. , the temperature of the IC chip 1 is raised.
このように、本実施例にあっては、ＩＣチップ１内に抵
抗体６を設けるとともに、その抵抗体６を外部電源７に
接続可能としたため、オーブン等の外部装置を用いなく
ても、ＩＣチップ１の温度を上昇させることができる。In this way, in this embodiment, the resistor 6 is provided inside the IC chip 1, and the resistor 6 can be connected to the external power supply 7, so that the IC chip can be connected without using an external device such as an oven. The temperature of the chip 1 can be increased.
このため、オーブン等のような外部装置が不要となるし
、加速試験を行う際の手間が少なくなるから、試験に要
する時間が短くなり、コストの低減が図られる。Therefore, an external device such as an oven or the like is not required, and the effort required to perform the accelerated test is reduced, so the time required for the test is shortened, and costs are reduced.
なお、ＩＣチップ１の通常使用時には、外部電源７の電
圧を零とするか、或いは、抵抗体６を外部電源７から切
り離せば、抵抗体６は発熱しないから集積回路の機能に
悪影響は与えない。In addition, during normal use of the IC chip 1, if the voltage of the external power supply 7 is set to zero or the resistor 6 is disconnected from the external power supply 7, the resistor 6 will not generate heat and will not adversely affect the function of the integrated circuit. .
第２図は本発明の第２実施例を示す図であり、第１図と
同様に、ＩＣチップ１の実装状態を示す平面図である。FIG. 2 is a diagram showing a second embodiment of the present invention, and similar to FIG. 1, it is a plan view showing the mounting state of the IC chip 1.
なお、第１図と同等の構成には、同じ符号を付すととも
に、第１図に示したポンディングパッド３、導体４及び
ワイヤ５は省略している。Components equivalent to those in FIG. 1 are given the same reference numerals, and the bonding pads 3, conductors 4, and wires 5 shown in FIG. 1 are omitted.
即ち、本実施例は、ＩＣチップ１と別体のチップ８にボ
ンディング３ａ、３ｂ及び抵抗体６を形成し、そのチッ
プ８を、ＩＣチップ１に近接して基板２上に実装したこ
とを除いては、上記第１実施例と同様の構成である。That is, in this embodiment, the bonding 3a, 3b and the resistor 6 are formed on a chip 8 separate from the IC chip 1, and the chip 8 is mounted on the substrate 2 in close proximity to the IC chip 1. The configuration is similar to that of the first embodiment described above.
このような構成であっても、抵抗体６の発熱によってＩ
Ｃチップ１が加熱されるから、上記第１実施例と同等の
効果が得られる。Even with this configuration, I
Since the C-chip 1 is heated, the same effect as in the first embodiment can be obtained.
なお、上記各実施例では、発熱体として抵抗体６を用い
た場合について説明したが、これに限定されるものでは
なく、他の素子であってもよい。In addition, although the above-mentioned each Example demonstrated the case where the resistor 6 was used as a heat generating body, it is not limited to this and other elements may be used.
特に、ペルチェ素子を利用した場合には、加速試験時に
は発熱体として使用し、通常使用時には吸熱体として使
用すれば、上記実施例の効果とともに、ＩＣチップ１の
冷却効果も得られる。In particular, when a Peltier element is used, if it is used as a heat generating element during accelerated testing and as a heat absorbing element during normal use, the effect of cooling the IC chip 1 can be obtained in addition to the effects of the above embodiments.
また、上記各実施例では、発熱体として抵抗体６を一つ
のＩＣチップ１に一つ設＆Ｊた場合について説明したが
、これに限定されるものではなく、二つ以上設けてもよ
い。Further, in each of the above embodiments, a case has been described in which one resistor 6 is provided as a heating element on one IC chip 1, but the present invention is not limited to this, and two or more resistors 6 may be provided.
［発明の効果〕
以上説明したように、本発明によれば、チップ内に又は
チップに近接して発熱体を設けたため、オーブン等の外
部装置を用いなくても集積回路を加熱することができる
から、加速試験に要する手間が少なくなり、コストの低
減が図られるという効果がある。[Effects of the Invention] As explained above, according to the present invention, since the heating element is provided within the chip or close to the chip, the integrated circuit can be heated without using an external device such as an oven. This has the effect of reducing the effort required for accelerated testing and reducing costs.
第１図は本発明の第１実施例の構成を示す平面図、第２
図は本発明の第２実施例の構成を示す平面図である。
１・・・ＩＣチップ、２・・・基板、３．３ａ、３ｂ・
・・ホンディングパッド、４．４ａ、４ｂ・・・導体、
５゜５ａ、５ｂ・・・ワイヤ、６・・・抵抗体（発熱体
）、７・・・外部電源、８・・・チップFIG. 1 is a plan view showing the configuration of the first embodiment of the present invention, and FIG.
The figure is a plan view showing the configuration of a second embodiment of the present invention. 1... IC chip, 2... Substrate, 3.3a, 3b.
...Honding pad, 4.4a, 4b...Conductor,
5゜5a, 5b...wire, 6...resistor (heating element), 7...external power supply, 8...chip
Claims (1)
接して発熱体を設けたことを特徴とする半導体集積回路
。(1) A semiconductor integrated circuit characterized in that a heating element is provided within or adjacent to a chip on which a circuit is constructed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2130629A JPH0425146A (en) | 1990-05-21 | 1990-05-21 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2130629A JPH0425146A (en) | 1990-05-21 | 1990-05-21 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0425146A true JPH0425146A (en) | 1992-01-28 |
Family
ID=15038818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2130629A Pending JPH0425146A (en) | 1990-05-21 | 1990-05-21 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0425146A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5255383A (en) * | 1975-10-31 | 1977-05-06 | Hitachi Ltd | Semiconductor integrated circuit |
| JPS636856A (en) * | 1986-06-26 | 1988-01-12 | Nec Corp | Manufacture of semiconductor device |
| JPS6310537A (en) * | 1986-07-01 | 1988-01-18 | Nec Corp | Semiconductor device |
-
1990
- 1990-05-21 JP JP2130629A patent/JPH0425146A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5255383A (en) * | 1975-10-31 | 1977-05-06 | Hitachi Ltd | Semiconductor integrated circuit |
| JPS636856A (en) * | 1986-06-26 | 1988-01-12 | Nec Corp | Manufacture of semiconductor device |
| JPS6310537A (en) * | 1986-07-01 | 1988-01-18 | Nec Corp | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100277563B1 (en) | Inspection device of semiconductor device and inspection method thereof | |
| US4223337A (en) | Semiconductor integrated circuit with electrode pad suited for a characteristic testing | |
| JPH04273451A (en) | Semiconductor device | |
| JP2014169964A (en) | Method of manufacturing semiconductor device | |
| US6015723A (en) | Lead frame bonding distribution methods | |
| JPH06132454A (en) | Method of wiring between package output end and hybrid element | |
| JPH0425146A (en) | Semiconductor integrated circuit | |
| KR20010030217A (en) | Multichip module packaging process for known good die burn-in | |
| JPH065677A (en) | Semiconductor device | |
| JPH112655A (en) | High temperature testing device of semiconductor | |
| JP3093216B2 (en) | Semiconductor device and inspection method thereof | |
| JPS62219942A (en) | Semiconductor integrated circuit in state of wafer | |
| KR20010110157A (en) | Monitoring resistor element and measuring method of relative preciseness of resistor elements | |
| JPH0989981A (en) | Chip carrier | |
| JP2786047B2 (en) | Resin-sealed semiconductor device | |
| JPH08213497A (en) | Semiconductor device and its manufacture | |
| JPS5941305B2 (en) | semiconductor equipment | |
| JPH04333251A (en) | Semiconductor wafer | |
| JPH04174532A (en) | Semiconductor integrated circuit | |
| JPH02245678A (en) | Integrated circuit device | |
| JPH0595076A (en) | Semiconductor device | |
| JPS62221126A (en) | Testing method for semiconductor device | |
| JP2972473B2 (en) | Semiconductor device | |
| JP2970206B2 (en) | Semiconductor device | |
| JPS62265731A (en) | Lead frame |