JPH0425029A - Lateral transistor - Google Patents
Lateral transistorInfo
- Publication number
- JPH0425029A JPH0425029A JP12768290A JP12768290A JPH0425029A JP H0425029 A JPH0425029 A JP H0425029A JP 12768290 A JP12768290 A JP 12768290A JP 12768290 A JP12768290 A JP 12768290A JP H0425029 A JPH0425029 A JP H0425029A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- collector
- layer
- emitter
- electrode wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 18
- 239000003574 free electron Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 102100027306 Carotenoid-cleaving dioxygenase, mitochondrial Human genes 0.000 description 1
- 101000937734 Homo sapiens Carotenoid-cleaving dioxygenase, mitochondrial Proteins 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、バイポーラモノリシック集積回路等に適用
されるラテラルトランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lateral transistor applied to bipolar monolithic integrated circuits and the like.
第７図及び第８図は従来のラテラルＰＮＰ トランジス
タの平面図及び切断正面図であり、第８図は第７図のＸ
−Ｘ′における断面に相当しており、それらの図面に示
すように、Ｐ型半導体基板１の表面にＮ 型の埋込層２
が形成され、基板１の上面にＮ型エピタキシャル層３が
形成され、このときオートドーピングによって埋込層２
の表面の浮き上がりが生じる。7 and 8 are a plan view and a cutaway front view of a conventional lateral PNP transistor, and FIG. 8 is a
-
is formed, and an N-type epitaxial layer 3 is formed on the upper surface of the substrate 1. At this time, a buried layer 2 is formed by autodoping.
Lifting of the surface occurs.
そして、エピタキシャル層３に所定領域を囲むようにＰ
型の素子分離領域４が形成され、素子分離領域４で囲ま
れたエピタキシャル層３の所定領域の表面左寄りに、第
１拡散層としてのＮ＋型のベース拡散層５が形成される
と共に、この所定領域の表面のほぼ中央部に第２拡散層
としてのＰ＋型のエミッタ拡散層６が形成され、このエ
ミッタ拡散層６を囲むように、所定領域の表面に第３拡
散層としてのＰ＋型のコレクタ拡散層７が形成され、ラ
テラルＰＮＰ構造が形成されている。Then, P is applied to the epitaxial layer 3 so as to surround a predetermined region.
A type element isolation region 4 is formed, and an N+ type base diffusion layer 5 as a first diffusion layer is formed on the left side of the surface of a predetermined region of the epitaxial layer 3 surrounded by the element isolation region 4. A P+ type emitter diffusion layer 6 as a second diffusion layer is formed approximately in the center of the surface of the region, and a P+ type collector as a third diffusion layer is formed on the surface of the predetermined region so as to surround this emitter diffusion layer 6. A diffusion layer 7 is formed to form a lateral PNP structure.
このとき、コレクタ拡散層７は平面的に見て四角形に形
成され、このコレクタ拡散層７の左側の−辺がベース拡
散層５とエミッタ拡散層６との間に位置している。At this time, the collector diffusion layer 7 is formed into a rectangular shape when viewed from above, and the left side of the collector diffusion layer 7 is located between the base diffusion layer 5 and the emitter diffusion layer 6.
さらに、エピタキシャル層３の上面全面に絶縁酸化膜８
が形成され、この酸化膜８のベース拡散層５上、エミッ
タ拡散層６上及びコレクタ拡散層７の左側の一辺上に、
それぞれコンタクトホール９１０．１１が形成され、絶
縁酸化膜８上にアルミニウムからなるベース、エミッタ
、コレクタ用の各電極配線層１．２，１．３．１４が形
成され、各コンタクトホール９〜］１それぞれを介して
各電極配線層１２〜１．４それぞれかベース、エミッタ
、コレクタの各拡散層５〜７に接触している。Furthermore, an insulating oxide film 8 is formed on the entire upper surface of the epitaxial layer 3.
is formed on the base diffusion layer 5 of this oxide film 8, on the emitter diffusion layer 6, and on the left side of the collector diffusion layer 7.
Contact holes 910.11 are formed respectively, and electrode wiring layers 1.2, 1.3.14 for the base, emitter, and collector made of aluminum are formed on the insulating oxide film 8, and each contact hole 910.11 is formed. Each of the electrode wiring layers 12 to 1.4 is in contact with each of the base, emitter, and collector diffusion layers 5 to 7 via the respective electrode wiring layers 12 to 1.4.
そして、各電極配線層１−２〜１４は、他のデバイスと
の接続等のために第７図に示すように長く形成されるた
め、特にエミッタ用電極配線層１３はコレクタ拡散層７
の右側の一辺の上方を横切り、エミッタ用電極配線層千
３の下方にコレクタ拡散層７が位置した構造となってい
る。Since each of the electrode wiring layers 1-2 to 14 is formed long as shown in FIG. 7 for connection with other devices, etc., the emitter electrode wiring layer 13 is particularly connected to the collector diffusion layer 7.
It has a structure in which a collector diffusion layer 7 is located below the emitter electrode wiring layer 13, crossing over one right side of the emitter electrode wiring layer 13.
ところで、上述したようなラテラルＰ Ｎ Ｐ ｌ−ラ
ンジスタを、第９図及び第１０図に示すようにバイアス
した場合の電圧−電流特性について説明する。By the way, the voltage-current characteristics when the above-described lateral P N P I-transistor is biased as shown in FIGS. 9 and 10 will be described.
いま、第９図に示すように、バイアス電源１５によりエ
ミッタを基準としてコレクタにｒｌＥの電圧を印加した
逆バイアスの場合、コレクタに流れるコレクタ電流を■
、印加電圧をＶとすると、このときのＶ−Ｉ特性は第１
１図中の（Ａ）のようになり、電圧Ｖが逆方向耐圧ＢＶ
以上になればＥＣＯ
電流Ｉが徐々に増加し、一方策１０図に示すようにコレ
クタを基準としてエミッタに正の電圧を印加した順バイ
アスの場合、Ｖ−１特性は第１１図中の（Ｂ）のように
なり、電圧Ｖがコレクタブレークダウン電圧ＢＶ
、（＞ＢＶ ）以上に上ＣＥＯＥＣＯ
昇すれば電流Ｉが急激に増加する。Now, as shown in FIG. 9, in the case of reverse bias where the bias power supply 15 applies a voltage rlE to the collector with the emitter as a reference, the collector current flowing to the collector is
, when the applied voltage is V, the V-I characteristic at this time is the first
As shown in (A) in Figure 1, the voltage V is reverse breakdown voltage BV.
If the ECO current I becomes higher than that, the ECO current I will gradually increase.On the other hand, in the case of forward bias where a positive voltage is applied to the emitter with the collector as a reference as shown in Figure 10, the V-1 characteristic will change as shown in (B) in Figure 11. ), and the voltage V is the collector breakdown voltage BV
, (>BV) or more, the current I increases rapidly.
このとき、第１１図から明らかなように、逆方向耐圧Ｂ
Ｖ はコレクタブレークダウン電圧ＢＣＯ
■ に比べて極端に小さく、以下にその原因にＥＯ
ついて第１２図及び第１３図を参照して説明する。At this time, as is clear from FIG.
V is extremely small compared to the collector breakdown voltage BCO2, and the cause of this will be explained below with reference to FIGS. 12 and 13.
たたし、第１２図、第１３図において、１６は正孔、］
７は電子、］８は自由電子であり、Ｗ。In Figures 12 and 13, 16 is a hole,]
7 is an electron, ]8 is a free electron, and W.
は実効的なエミッタ・コレクタ間隔、即ちベース幅を示
す。represents the effective emitter-collector spacing, that is, the base width.
まず、第１０図に示すような逆バイアスを行った場合に
ついて説明すると、順バイアス状態では第１．３図に示
すように、エミッタ拡散層６に、コレクタ拡散層７及び
基板１を基準として電源１５によりエミッタ用電極配線
層１３を介して正の電圧が印加されており、エミッタ拡
散層６に印加する電圧■を上昇させると、エミッタ拡散
層６とコレクタ拡散層７との間のＮ型のエピタキシャル
層３の表面イ」近に自由電子１８が分布し、電圧Ｖがコ
レクタブレークダウン電圧ＢＶ に達するまＥＯ
では自由電子］８が分布した状態が保持され、コレクタ
電流■はほとんど流れない。First, to explain the case where a reverse bias is applied as shown in FIG. 10, in a forward bias state, as shown in FIG. 15, a positive voltage is applied through the emitter electrode wiring layer 13, and when the voltage (2) applied to the emitter diffusion layer 6 is increased, the N-type voltage between the emitter diffusion layer 6 and the collector diffusion layer 7 is increased. Free electrons 18 are distributed near the surface of the epitaxial layer 3, and until the voltage V reaches the collector breakdown voltage BV, the state in which the free electrons 8 are distributed is maintained at EO, and almost no collector current flows.
そして、エミッタ拡散層６に印加する電圧■がコレクタ
ブレークダウン電圧ＢＶ に達すると、ＥＯ
降伏現象が生じ、第１１図中の（Ｂ）の如く、コレクタ
電流Ｉか急激に増大し、このような降伏か生じるコレク
タブレークダウン電圧ＢＶ はべＥＯ
−ス幅Ｗ 、Ｎ型のエピタキシャル層３の不純物す
濃度等によって決定されるが、一般には３５〜６０
［Ｖコ程度となる。Then, when the voltage ■ applied to the emitter diffusion layer 6 reaches the collector breakdown voltage BV, an EO breakdown phenomenon occurs, and as shown in (B) in FIG. 11, the collector current I increases rapidly. The collector breakdown voltage BV at which breakdown occurs is determined by the base width W, the impurity concentration of the N-type epitaxial layer 3, etc., but is generally 35 to 60.
[It will be about V.
一方、第９図に示すような逆バイアスを行った場合、第
１２図に示すように、コレクタ拡散層７に、エミツタ拡
散層６□エミツタ用電極配線層１−３及び基板１を基準
として正の電圧が印加されており、コレクタ拡散層７に
印加する電圧Ｖを上昇させると、この電圧Ｖが逆方向耐
圧ＢＶ に達ＣＯ
するまでは、エミッタ拡散層６とコレクタ拡散層７との
間のＮ型のエピタキシャル層３の表面付近に空乏層が形
成されるが、コレクタ拡散層７とエミッタ拡散層６との
間には電流は流れない。On the other hand, when a reverse bias is applied as shown in FIG. 9, the collector diffusion layer 7 is biased with respect to the emitter diffusion layer 6 □ the emitter electrode wiring layer 1-3 and the substrate 1, as shown in FIG. When the voltage V applied to the collector diffusion layer 7 is increased, the voltage between the emitter diffusion layer 6 and the collector diffusion layer 7 increases until this voltage V reaches the reverse breakdown voltage BV CO . Although a depletion layer is formed near the surface of the N-type epitaxial layer 3, no current flows between the collector diffusion layer 7 and the emitter diffusion layer 6.
そして、コレクタ拡散層７に印加する電圧が逆方向耐圧
ＢＶ をこえると、空乏層の陽イオンＣＯ
化したドナー原子から電子１−７が追い出され、これに
よって正孔１−６が空乏層に残り、Ｎ型のエピタキシャ
ル層３の表面にＰ型領域が形成され、Ｐ＋型のエミッタ
拡散層６及びコレクタ拡散層７が、形成されたＰ型領域
によって接続され、両波散層６，７間で電流が流れ、一
般にこのときのＰ型領域が反転層或いはチャネルと呼ば
れる。Then, when the voltage applied to the collector diffusion layer 7 exceeds the reverse breakdown voltage BV, electrons 1-7 are expelled from the donor atoms that have become cations CO in the depletion layer, and holes 1-6 remain in the depletion layer. , a P-type region is formed on the surface of the N-type epitaxial layer 3, and the P+-type emitter diffusion layer 6 and collector diffusion layer 7 are connected by the formed P-type region, and between the two wave scattering layers 6 and 7. A current flows, and the P-type region at this time is generally called an inversion layer or channel.
従来のラテラルＰＮＰ ）ランジスタの場合、逆バイア
ス状態において、空乏層によってエミッタ。In the case of a conventional lateral PNP) transistor, the emitter is depleted by a depletion layer in reverse bias conditions.
コレクタ拡散層６，７間が接続されるため、逆方向耐圧
ＢＶ が極端に低くなり、特に高電圧でＣＯ
使用する集積回路を構成する場合に、逆方向耐圧ＢＶ
がコレクタブレークダウン電圧ＢＶｃＥ。Since the collector diffusion layers 6 and 7 are connected, the reverse breakdown voltage BV becomes extremely low.
is the collector breakdown voltage BVcE.
ＣＯ
程度まで確保されないと集積回路の動作範囲が著しく制
約されるという問題点があった。There is a problem in that unless the level of CO 2 is secured, the operating range of the integrated circuit will be severely restricted.
この発明は、上記したような問題点を解消するためにな
されたもので、逆方向耐圧をコレクタブレークダウン電
圧程度まで上昇させて動作範囲を広げ得るようにするこ
とを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to increase the reverse breakdown voltage to about the collector breakdown voltage, thereby widening the operating range.
この発明に係るラテラルトランジスタは、半導体基板の
表面に形成された一方の導電型の第１拡散層と、前記基
板の表面に形成された他方の導電型の第２拡散層と、前
記第２拡散層を囲むように前記基板の表面に形成された
前記他方の導電型の第３拡散層と、前記第２拡散層に接
触し前記第３拡散層の上方を横切るように前記基板上方
に形成された配線層とを備えたラテラルトランジスタに
おいて、前記第３拡散層の前記配線層の下方に位置した
部分を除去したことを特徴としている。The lateral transistor according to the present invention includes a first diffusion layer of one conductivity type formed on the surface of a semiconductor substrate, a second diffusion layer of the other conductivity type formed on the surface of the substrate, and the second diffusion layer of the other conductivity type formed on the surface of the substrate. a third diffusion layer of the other conductivity type formed on the surface of the substrate so as to surround the third diffusion layer; and a third diffusion layer of the other conductivity type formed above the substrate so as to contact the second diffusion layer and cross above the third diffusion layer. The lateral transistor is characterized in that a portion of the third diffusion layer located below the wiring layer is removed.
この発明においては、第３拡散層の配線層の下方に位置
した部分を除去したため、第２拡散層を基準として第３
拡散層の電位を上昇させることによって配線層の下方に
反転層が形成されても、この反転層によって第２．第３
拡散層が接続されることがなく、従来に比べて逆方向耐
圧が大幅に向上する。In this invention, since the portion of the third diffusion layer located below the wiring layer is removed, the third diffusion layer is
Even if an inversion layer is formed below the wiring layer by increasing the potential of the diffusion layer, the second. Third
Since the diffusion layer is not connected, the reverse breakdown voltage is significantly improved compared to the conventional method.
第１図はこの発明のラテラルトランジスタの〜実施例の
平面図であり、第２図は第１図のＹＹ′線における切断
正面図を示す。FIG. 1 is a plan view of an embodiment of a lateral transistor of the present invention, and FIG. 2 is a front view cut along the line YY' in FIG.
第１図及び第２図において、第７図及び第８図と相違す
るのは、コレクタ拡散層７を、その右側の一辺の中央部
を切除して平面的にほぼコ字状にし、エミッタ用電極配
線層１３の下方のコレクタ拡散層７を除去したことであ
る。The difference between FIGS. 1 and 2 from FIGS. 7 and 8 is that the collector diffusion layer 7 is cut out at the center of one side on the right side, making it approximately U-shaped in plan view, and is used as an emitter. This is because the collector diffusion layer 7 below the electrode wiring layer 13 is removed.
このような構成において、第９図に示すような逆バイア
スを行うと、エミッタ用電極配線層１−３が、コレクタ
拡散層７よりも低電位となり、コレクタ拡散層７に印加
する電圧が上昇されて逆方向耐圧ＢＶ に達すると
、第３図に示すように、ＣＯ
エミッタ用電極配線層１３の下方のエピタキシャル層３
の表面に反転層が形成されるが、従来と異なり、第３図
中の破線の位置のコレクタ拡散層７が存在しないため、
従来のようにコレクタ拡散層７からエミッタ拡散層６及
びエミッタ用電極配線層］３への電流紅路がなく、コレ
クタ電流Ｉが流れることはない。ここで、前述した第１
２図と同様に、第３図中の１６は正孔、１７は電子であ
り、第４図においても同じである。In such a configuration, when a reverse bias as shown in FIG. 9 is applied, the emitter electrode wiring layer 1-3 has a lower potential than the collector diffusion layer 7, and the voltage applied to the collector diffusion layer 7 increases. When the reverse breakdown voltage BV is reached, as shown in FIG.
An inversion layer is formed on the surface of the layer, but unlike the conventional case, the collector diffusion layer 7 at the position indicated by the broken line in FIG. 3 does not exist.
There is no current path from the collector diffusion layer 7 to the emitter diffusion layer 6 and the emitter electrode wiring layer 3 as in the conventional case, and the collector current I does not flow. Here, the first
2, 16 in FIG. 3 is a hole, 17 is an electron, and the same is true in FIG. 4.
ところで、逆バイアス時における第１図中のＺＺ′線に
おける切断側面図は、第４図に示すようになり、エミッ
タ用電極配線層１３の下方の反転層からコレクタ拡散層
７まで距離りだけ離れているため、エミッタ用電極配線
層１３の下方の反転層によってエミッタ拡散層６とコレ
クタ拡散層７の前、後の各辺とが接続されることはなく
、前述したようにコレクタ電流が流れることはない。By the way, a side view cut along the ZZ' line in FIG. 1 at the time of reverse bias is as shown in FIG. Therefore, the front and rear sides of the emitter diffusion layer 6 and the collector diffusion layer 7 are not connected by the inversion layer below the emitter electrode wiring layer 13, and the collector current does not flow as described above. There isn't.
ただしこのとき、コレクタ電流が流れないように距離り
を設定する必要がある。However, at this time, it is necessary to set the distance so that collector current does not flow.
このように、エミッタ拡散層６を基準としてコレクタ拡
散層７の電位を上昇させることによってエミッタ配線層
１３の下方に反転層が形成されても、エミッタ用電極配
線層］３の下方にはコレクタ拡散層７が除去されて存在
しないため、従来のように反転層によってエミッタ拡散
層６とコレクタ拡散層７が接続されることを防止でき、
コレクタ、エミッタ間の逆方向耐圧ＢＶ が極端に
低ＣＯ
くなることがなく、ＢＶ を飛躍的に大きくずＣＯ
ることか可能となり、動作範囲を広くとることができる
。In this way, even if an inversion layer is formed below the emitter wiring layer 13 by increasing the potential of the collector diffusion layer 7 with respect to the emitter diffusion layer 6, there is no collector diffusion layer below the emitter electrode wiring layer 3. Since the layer 7 is removed and does not exist, it is possible to prevent the emitter diffusion layer 6 and the collector diffusion layer 7 from being connected by an inversion layer as in the conventional case.
The reverse withstand voltage BV between the collector and the emitter does not become extremely low, and it is possible to reduce the BV without dramatically increasing the CO, and the operating range can be widened.
なお、他の実施例として、第５図に示すように、ベース
用電極配線層１２及びコレクタ用電極配線層１４を接続
し、ダイオードとして使用してもよい。In addition, as another example, as shown in FIG. 5, the base electrode wiring layer 12 and the collector electrode wiring layer 14 may be connected and used as a diode.
さらに異なる他の実施例として、第６図に示すように、
素子分離領域４とエミッタ拡散層６との間のリーク電流
を下げるために、コレクタ拡散層６を囲むように、四角
形のＮ 型のベース拡散層］９をエピタキシャル層３に
形成してもよい。As a further different embodiment, as shown in FIG.
In order to reduce leakage current between the element isolation region 4 and the emitter diffusion layer 6, a rectangular N type base diffusion layer 9 may be formed in the epitaxial layer 3 so as to surround the collector diffusion layer 6.
また、第６図に示す構成において、ベース用電極配線層
１２とコレクタ用電極配線層１４とを接続し、ダイオー
ドとして使用してもよい。Moreover, in the structure shown in FIG. 6, the base electrode wiring layer 12 and the collector electrode wiring layer 14 may be connected and used as a diode.
さらに、エミッタ用電極配線層１３は、第１図。Furthermore, the emitter electrode wiring layer 13 is shown in FIG.
第５図或いは第６図に示すように右方に引出すたけに限
らず、前方又は後方に引出すようにしてもよく、前方に
引出した場合は、コレクタ拡散層７の前側の一辺の一部
を切除し、後方に引出した場合は、コレクタ拡散層７の
後側の一辺の一部を切除すればよい。As shown in FIG. 5 or 6, it is not limited to just pulling it out to the right, but it may also be pulled out forward or backward. When it is pulled out forward, a part of one front side of the collector diffusion layer 7 is pulled out. When the collector diffusion layer 7 is cut out and pulled out to the rear, a part of one rear side of the collector diffusion layer 7 may be cut out.
また、上記各実施例は、Ｐ Ｎ Ｐ ｌ−ランジスタの
場合について説明したが、ラテラル形のＮＰＮ トラン
ジスタを形成する場合においてもこの発明を同様に適用
することができる。Furthermore, although the above embodiments have been described with reference to the case of a PNP I-transistor, the present invention can be similarly applied to the case of forming a lateral type NPN transistor.
以上のように、この発明のラテラルトランジスタによれ
ば、第３拡散層の配線層の下方に位置した部分を除去し
たため、第２拡散層を基準として第３拡散層の電位を」
１昇させることによって配線層の下方に反転層が形成さ
れても、この反転層によって第２．第３拡散層が接続さ
れることを防止でき、従来に比べて逆方向耐圧を大幅に
向上することが可能となり、動作範囲の拡張を図ること
ができ、高耐圧のバイポーラモノリシック集積回路の形
成において特に有効である。As described above, according to the lateral transistor of the present invention, since the portion of the third diffusion layer located below the wiring layer is removed, the potential of the third diffusion layer is changed with respect to the second diffusion layer.
Even if an inversion layer is formed below the wiring layer by raising the wiring layer by one layer, this inversion layer causes the second. It is possible to prevent the third diffusion layer from being connected, and it is possible to significantly improve the reverse breakdown voltage compared to the conventional method, making it possible to expand the operating range and making it possible to form high breakdown voltage bipolar monolithic integrated circuits. Particularly effective.
第１図はこの発明のラテラルトランジスタの平面図、第
２図は第１図のＹ−Ｙ′線における切断止面図、第３図
は第１図の動作説明用の一部の切断正面図、第４図は第
１図のｚ−ｚ’線における動作説明用の切断側面図、第
５図及び第６図はそれぞれこの発明の他の実施例の平面
図、第７図は従来のラテラルトランジスタの平面図、第
８図は第７図のｘ−ｘ’線における切断正面図、第９図
］ ２
及び第１０図はそれぞれ第７図の動作説明用の模擬回路
の結線図、第１１図は第７図のＶ−Ｉ特性図、第１２図
及び第１３図はそれぞれ第７図の動作説明用の一部の切
断正面図である。
図において、１は半導体基板、５，１９はベース拡散層
、６はエミッタ拡散層、７はコレクタ拡散層、１．３は
エミッタ用電極配線層である。
なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a plan view of the lateral transistor of the present invention, FIG. 2 is a cutaway top view taken along the Y-Y' line in FIG. 1, and FIG. 3 is a partially cutaway front view for explaining the operation of FIG. , FIG. 4 is a cutaway side view taken along line zz' in FIG. 1 to explain the operation, FIGS. 5 and 6 are plan views of other embodiments of the present invention, and FIG. FIG. 8 is a plan view of the transistor; FIG. 8 is a cutaway front view along line xx' in FIG. 7; FIG. 9 is a connection diagram of a simulated circuit for explaining the operation of FIG. 7; The figure is a VI characteristic diagram of FIG. 7, and FIGS. 12 and 13 are partially cutaway front views for explaining the operation of FIG. 7, respectively. In the figure, 1 is a semiconductor substrate, 5 and 19 are base diffusion layers, 6 is an emitter diffusion layer, 7 is a collector diffusion layer, and 1.3 is an emitter electrode wiring layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
１拡散層と、前記基板の表面に形成された他方の導電型
の第２拡散層と、前記第２拡散層を囲むように前記基板
の表面に形成された前記他方の導電型の第３拡散層と、
前記第２拡散層に接触し前記第３拡散層の上方を横切る
ように前記基板上方に形成された配線層とを備えたラテ
ラルトランジスタにおいて、 前記第３拡散層の前記配線層の下方に位置した部分を除
去したことを特徴とするラテラルトランジスタ。(1) A first diffusion layer of one conductivity type formed on the surface of a semiconductor substrate, a second diffusion layer of the other conductivity type formed on the surface of the substrate, and a second diffusion layer surrounding the second diffusion layer. a third diffusion layer of the other conductivity type formed on the surface of the substrate;
and a wiring layer formed above the substrate in contact with the second diffusion layer and crossing above the third diffusion layer, wherein the wiring layer is located below the wiring layer of the third diffusion layer. A lateral transistor characterized by having a portion removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2127682A JP2665820B2 (en) | 1990-05-16 | 1990-05-16 | Lateral transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2127682A JP2665820B2 (en) | 1990-05-16 | 1990-05-16 | Lateral transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0425029A true JPH0425029A (en) | 1992-01-28 |
| JP2665820B2 JP2665820B2 (en) | 1997-10-22 |
Family
ID=14966104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2127682A Expired - Lifetime JP2665820B2 (en) | 1990-05-16 | 1990-05-16 | Lateral transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2665820B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55105359A (en) * | 1979-02-07 | 1980-08-12 | Nec Corp | Semiconductor device |
-
1990
- 1990-05-16 JP JP2127682A patent/JP2665820B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55105359A (en) * | 1979-02-07 | 1980-08-12 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2665820B2 (en) | 1997-10-22 |
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