【発明の詳細な説明】[Detailed description of the invention]
本発明は、積層セラミツクコンデンサの積層構
造に関するものである。
従来、積層セラミツクコンデンサの積層構造
は、グリーンシート法の場合、例えばドクターブ
レード製膜によりグリーンセラミツク膜を作製し
該グリーンセラミツク膜に内部電極となを電極ペ
ーストを印刷し、対向電極を形成するように複数
枚積層し、同時にその両外側に、保護の役割をな
すグリーンセラミツク膜（内部電極ペーストの印
刷されないもの）が積層された構造である。スク
リーン印刷法の場合も構造上は同でセラミツク膜
がスクリーン印刷で形成される点が異なるだけで
ある。いづれにしろこうした積層構造の場合、セ
ラミツク組成物の原料成分のうちで蒸発しやすい
成分があると、これらの成分が焼成工程で表面か
ら蒸発し、積層セラミツクコンデンサチツプの表
面に近い部分のセラミツク組成物の組成比がチツ
プ内部と異なつたものとなり、チツプの表面に近
い位置にある内部電極ではさまれたセラミツク層
の容量、及び絶縁抵抗が低下するだけでなく、こ
れらのセラミツク層で絶縁破壊を起し易くなり信
頼性の低い積層セラミツクコンデンサとなつてし
まう欠点があつた。
本発明はこれら欠点を除去するため焼成中の積
層セラミツクコンデンサチツプ表面に近い位置に
ある部分のセラミツク組成物の原料成分の蒸発を
抑制し、信頼性の高い積層セラミツクコンデンサ
を提供するものである。
本発明は従来の積層セラミツクコンデンサの内
部電極の構造においてコンデンサ内の複数の内部
電極のうちの両外側に位置するそれぞれの内部電
極のさらに外側のコンデンサ表面により近い位置
に該内部電極と同一の外部電極に接続する１以上
の内部電極が形成されている構造を特徴としてい
る。すなわち第２図において示すようにセラミツ
ク組成物３中に一方の外部電極に（図では省略し
てある。）接続している内部電極２と同様に他方
の外部電極に接続している内部電極２が交互に積
層されている。従来の積層セラミツクコンデンサ
の内部電極構造に対して、これらの内部電極のう
ちの両外側に位置するそれぞれの内部電極のさら
に外側のコンデンサ表面により近い位置に前記内
部電極と同一外部電極に接続する１以上の内部電
極１が形成された構造である。
以下実施例に従つて詳細に説明する。Pb
（Fe1/2・Nb1/2）0.67（Fe2/3W1/3）0.33O3で示される
複
合ペロブスカイト系誘電体材料を予焼、ボールミ
ル粉砕したのち、ドクターブレード法により30μ
ｍのグリーンセラミツクシートを作製した。該グ
リーンセラミツクシートにスクリーン印刷法で内
部電極ペースト（Ag−Pd系）を印刷し、それを
61枚積層した。次にその上下に、印刷したグリー
ンセラミツク膜を内部電極の形成にならないよう
各５枚づつ積層し、さらに印刷しないグリーンセ
ラミツク膜を上下各５枚積層し、これを熱プレス
機で熱圧着し、所定の形状に切断したのち、脱バ
インダーおよび焼成及び外部電極形成を行なつ
た。得られた積層セラミツクコンデンサチツプの
容量、絶縁抵抗を測定するとともに内部電極では
さまれた各セラミツク層の容量、絶縁抵抗も測定
した。その結果を表および第１図に示す。比較の
為に内部電極層の上下に各10枚の印刷しないグリ
ーンセラミツク膜を積層した従来の積層構造の積
層セラミツクコンデンサも同時に作製して、その
特性を測定した。
The present invention relates to a laminated structure of a laminated ceramic capacitor. Conventionally, the laminated structure of a laminated ceramic capacitor has been constructed using the green sheet method, for example, by creating a green ceramic film by doctor blade film forming, and printing internal electrodes and electrode paste on the green ceramic film to form counter electrodes. It has a structure in which multiple layers are laminated, and at the same time, green ceramic films (without internal electrode paste printed on them) that play a protective role are laminated on both outer sides. In the case of screen printing, the structure is the same, except that the ceramic film is formed by screen printing. In any case, in the case of such a laminated structure, if there are components that are easily evaporated among the raw materials of the ceramic composition, these components will evaporate from the surface during the firing process, and the ceramic composition of the portion near the surface of the laminated ceramic capacitor chip will change. The composition ratio of the ceramic material becomes different from that inside the chip, which not only reduces the capacitance and insulation resistance of the ceramic layers sandwiched between the internal electrodes located near the surface of the chip, but also causes dielectric breakdown in these ceramic layers. This has the disadvantage that multilayer ceramic capacitors have low reliability because they are easily damaged. In order to eliminate these drawbacks, the present invention suppresses the evaporation of the raw material components of the ceramic composition near the surface of the multilayer ceramic capacitor chip during firing, thereby providing a highly reliable multilayer ceramic capacitor. In the structure of the internal electrodes of a conventional multilayer ceramic capacitor, the present invention provides a structure in which each of the internal electrodes located on both sides of a plurality of internal electrodes in the capacitor is placed at a position closer to the surface of the capacitor on the outer side of the internal electrode. It is characterized by a structure in which one or more internal electrodes connected to the electrodes are formed. That is, as shown in FIG. 2, there are internal electrodes 2 connected to one external electrode (not shown in the figure) in the ceramic composition 3, and internal electrodes 2 connected to the other external electrode in the same way. are stacked alternately. In contrast to the internal electrode structure of a conventional multilayer ceramic capacitor, there is a structure in which each internal electrode located on both sides of these internal electrodes is connected to the same external electrode as the internal electrode at a position closer to the outer surface of the capacitor. This is the structure in which the internal electrodes 1 described above are formed. A detailed explanation will be given below based on examples. Pb
(Fe 1/2・Nb 1/2 ) 0.67 (Fe 2/3 W 1/3 ) 0.33 A composite perovskite dielectric material represented by O 3 was prefired, ball milled, and then pulverized to 30μ by the doctor blade method.
A green ceramic sheet of m was prepared. An internal electrode paste (Ag-Pd system) was printed on the green ceramic sheet using a screen printing method, and then
61 sheets were laminated. Next, five printed green ceramic films are laminated on top and bottom of the film so as not to form internal electrodes, and five non-printed green ceramic films are laminated on top and bottom, and these are bonded under heat using a heat press machine. After cutting into a predetermined shape, binder removal, firing, and external electrode formation were performed. The capacitance and insulation resistance of the obtained multilayer ceramic capacitor chip were measured, as well as the capacitance and insulation resistance of each ceramic layer sandwiched between internal electrodes. The results are shown in the table and FIG. For comparison, a conventional laminated ceramic capacitor with a conventional laminated structure in which 10 unprinted green ceramic films were laminated on the top and bottom of the internal electrode layer was also fabricated at the same time, and its characteristics were measured.
【表】
また第１図は積層セラミツクコンデンサにおい
て、内部電極ではさまれた各セラミツク層に対し
て一方のコンデンサ表面から順番に番号をつけこ
れと各セラミツク層・容量抵抗積の関係を示した
ものである。
表、第１図から明らかなように、本発明による
積層構造をもつコンデンサでは、従来のものに比
べ内部電極にはさまれた各セラミツク層の容量と
絶縁抵抗の積が表面に近い部分でも低下せず、ま
たチツプ全体の容量と絶縁抵抗の積も従来品に比
し高い値を示している。
以上述べたごとく本発明によれば積層セラミツ
クコンデンサの特性を向上させることが出来、信
頼性の高い積層セラミツクコンデンサの提供が可
能となつた。[Table] Figure 1 shows the relationship between each ceramic layer sandwiched between internal electrodes in a multilayer ceramic capacitor, numbered sequentially from the surface of one capacitor, and the capacitance-resistance product of each ceramic layer. It is. As is clear from the table and Figure 1, in the capacitor with the laminated structure according to the present invention, the product of capacitance and insulation resistance of each ceramic layer sandwiched between the internal electrodes is lower than that of the conventional capacitor, even in areas close to the surface. Moreover, the product of capacitance and insulation resistance of the entire chip is higher than that of conventional products. As described above, according to the present invention, the characteristics of a multilayer ceramic capacitor can be improved, and a highly reliable multilayer ceramic capacitor can be provided.
【図面の簡単な説明】[Brief explanation of drawings]
第１図は本発明品と従来品の積層セラミツクコ
ンデンサチツプ中の内部電極ではさまれた各セラ
ミツク層の位置とその部分の抵抗容量積の関係を
示す図である。第２図は、本発明の積層構造を示
す模式的断面図であり、１，２，２′は内部電極
であり、３はセラミツク組成物部分である。
FIG. 1 is a diagram showing the relationship between the position of each ceramic layer sandwiched between internal electrodes in a laminated ceramic capacitor chip of the present invention and a conventional product and the resistance-capacitance product of that portion. FIG. 2 is a schematic cross-sectional view showing the laminated structure of the present invention, in which 1, 2, and 2' are internal electrodes, and 3 is a ceramic composition portion.