JPH0424669B2 - - Google Patents
Info
- Publication number
- JPH0424669B2 JPH0424669B2 JP56044412A JP4441281A JPH0424669B2 JP H0424669 B2 JPH0424669 B2 JP H0424669B2 JP 56044412 A JP56044412 A JP 56044412A JP 4441281 A JP4441281 A JP 4441281A JP H0424669 B2 JPH0424669 B2 JP H0424669B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- bld
- voltage
- resistor
- dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Current Or Voltage (AREA)
- Tests Of Electric Status Of Batteries (AREA)
Description
【発明の詳細な説明】
本発明は半導体ICに内蔵された電池寿命検出
回路（以下BLD回路という）の設定電圧の決定
方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for determining a set voltage of a battery life detection circuit (hereinafter referred to as a BLD circuit) built into a semiconductor IC.
従来のBLD回路の設定電圧決定方法は、第１
図に示す如く、点線で囲つた外付け抵抗RBLDを幾
種類か用意し、ハンダ付けなどで接続し、外部か
ら設定していた。この方法だと、抵抗が外付けで
あるために場所をとり、集積度の低下が問題とな
る。また外付け抵抗を幾種類も用意しなければな
らない不便さがあつた。第１図の回路の動作は、
通常の状態ではTr1，Tr2，R1，R2，Tr3でTr4の
ゲート電位を設定し、Tr4のソース，ドレイン間
の抵抗を小さくし、Tr6をオンして、アウトには
ローの出力が出る。電池の電圧が低下するとTr4
のソース，ドレイン間の抵抗が上がり、RBLDを通
してのローの電位がTr6のゲートに加わり、Tr6
がオフになり、Tr5がオンして、アウトにはハイ
の出力が出るという動作になる。 The conventional BLD circuit setting voltage determination method is
As shown in the figure, several types of external resistors RBLD , which are surrounded by dotted lines, were prepared, connected by soldering, etc., and set from the outside. With this method, since the resistor is externally attached, it takes up a lot of space and there is a problem of a reduction in the degree of integration. There is also the inconvenience of having to prepare several types of external resistors. The operation of the circuit in Figure 1 is as follows:
Under normal conditions, Tr 1 , Tr 2 , R 1 , R 2 , and Tr 3 set the gate potential of Tr 4 , reduce the resistance between the source and drain of Tr 4 , turn on Tr 6 , and turn it out. produces a low output. When the battery voltage drops, Tr 4
The resistance between the source and drain of Tr 6 increases, the low potential through R BLD is applied to the gate of Tr 6 , and Tr 6
is turned off, Tr 5 is turned on, and a high output is output at the output.
本発明は、かかる欠点を除去したもので、その
目的は、内蔵したBLD回路に外部からボンデイ
ングによつて３端子にハイの状態を加えたままに
しておき、その影響が出ない状態にしておいて、
分周回路からのハイ，ローの状態を、他の３端子
から加え、その組み合わせにより、８状態の設定
電圧を作ろうというものである。 The present invention eliminates this drawback.The purpose of the present invention is to maintain a high state on three terminals of the built-in BLD circuit by external bonding, so that the effect is not exerted. There,
The idea is to add the high and low states from the frequency divider circuit to the other three terminals, and create 8-state set voltages by combining them.
以下、実施例に基いて本発明を詳しく説明す
る。 Hereinafter, the present invention will be explained in detail based on Examples.
第２図は本発明のBLD回路であり、１はBLD
入力ゲート、２はBLD抵抗分割回路、３は基準
電圧発生回路、４は比較回路である。BLD入力
ゲートは第３図の構成になつており、BLD抵抗
分割回路は第４図の構成になつている。第３図第
４図の働きは以下に示す。第１図の３の基準電圧
発生回路は第６図に示し、第１図の４の比較回路
は第７図に示す。第６図に於いてTr1，Tr2のβ
は同一でVTHに差があり、Tr3，Tr4はβもVTHも
同一である。 Figure 2 shows the BLD circuit of the present invention, and 1 is the BLD circuit of the present invention.
2 is a BLD resistance divider circuit, 3 is a reference voltage generation circuit, and 4 is a comparison circuit. The BLD input gate has the configuration shown in FIG. 3, and the BLD resistor divider circuit has the configuration shown in FIG. 4. The functions of Figures 3 and 4 are shown below. The reference voltage generation circuit 3 in FIG. 1 is shown in FIG. 6, and the comparison circuit 4 in FIG. 1 is shown in FIG. In Figure 6, β of Tr 1 and Tr 2
are the same and there is a difference in V TH , and Tr 3 and Tr 4 have the same β and V TH .
今、Tr1のVTHをVTH1，βをβ1，Tr2のVTHを
VTH2，Tr3のVTHをVTH3，βをβ2とすると、飽和
状態の電流の式より、第６図のID1，ID2は次の様
になる。 Now, V TH of Tr 1 is V TH1 , β is β 1 , V TH of Tr 2 is
When V TH2 and V TH of Tr 3 are V TH3 and β are β 2 , I D1 and I D2 in FIG. 6 are as follows from the equation of the current in the saturated state.
ID1＝１／２β1（VDD−VTH1）2 …… ID1＝１／２β2（V1−VTH3）2 …… ID2＝１／２β1（VDD−Vst−VTH2）2 …… ID2＝１／２β2（V1−VTH3）2′ …… ，から VTH1＝VDD−√2 1（V1−VTH3） ，から VTH2＝VDD−Vst−√2 1（V1−VTH3） ∴VTH1−VTH2＝Vst 従つてVstはVTH1とVTH2の差になり一定となる。 I D1 = 1/2β 1 (V DD −V TH1 ) 2 ... I D1 = 1/2β 2 (V 1 −V TH3 ) 2 ... I D2 = 1/2β 1 (V DD −Vst−V TH2 ) 2 ... I D2 = 1/2β 2 (V 1 −V TH3 ) 2 ′ ... , from V TH1 = V DD −√ 2 1 (V 1 −V TH3 ), from V TH2 = V DD −Vst−√ 2 1 (V 1 −V TH3 ) ∴V TH1 −V TH2 =Vst Therefore, Vst is the difference between V TH1 and V TH2 and remains constant.
第７図に於ては、オペアンプのコンパレータで
あり、Vc＞Vstの時は、Tr2がオンになり、Tr3
のゲートにローの電位がかかり、Tr3はオンにな
りTr5のゲートにハイがかかり、BLDアウトには
ローが出てくる。逆に、Vc＜Vstの時は、Tr4が
オンになり、Tr5のゲートにローがかかり、Tr5
がオンして、BLDアウトはハイの状態になり、
BLD状態を検出する。 In Figure 7, it is an operational amplifier comparator, and when Vc > Vst, Tr 2 is turned on and Tr 3 is turned on.
A low potential is applied to the gate of Tr 3, Tr 3 is turned on, a high voltage is applied to the gate of Tr 5 , and a low voltage is output from BLD out. Conversely, when Vc<Vst, Tr 4 turns on, low is applied to the gate of Tr 5 , and Tr 5
turns on, BLD out goes high,
Detect BLD condition.
次に第２図の動作を具体的に説明すると、図中
のＡ点をローになるようにしておくと、C1，C2，
C3端子をボンデイングによつてハイの状態にし
ておいても、C′1，C′2，C′3には、C1，C2，C3の
影響があらわれない。そこで点線で囲つた部分の
端子ａ，ｂ，ｃに分周回路から、第５図のタイミ
ングチヤートに示されている信号を加えることに
よつて、第３図のBLD入力ゲートの働きで、８
通りの状態を作り出すことができる。その８通り
の状態は、外部の記憶装置によつて記憶される。
８状態は第４図のBLD抵抗分割回路に加えられ
るとTGと書かれている、トランスミツシヨンゲ
ートがオン、オフして８通りの抵抗状態により、
８通りの電圧が発生する。８通りの電圧の中の最
良の電圧を選択した後は、その電圧を発生した
ａ，ｂ，ｃの各状態（ハイかロー）を、ボンデイ
ングワイヤを切ることにより、C1，C2、C3によ
つて作り出す。そこで第１図のＡ点をハイの状態
にすることによつて、今度は、ａ，ｂ，ｃの状態
には無関係に、C1，C2、C3の設定状態によつて
BLD回路が動作することになる。C1、C2，C3に
は１回のボンデイングが必要なだけで、ボンデイ
ングパツドの劣化は防止できる。 Next, to specifically explain the operation in Figure 2, if point A in the figure is set to low, C 1 , C 2 ,
Even if the C 3 terminal is kept in a high state by bonding, the influence of C 1 , C 2 , and C 3 does not appear on C′ 1 , C′ 2 , and C′ 3 . Therefore, by applying the signals shown in the timing chart in Fig. 5 from the frequency divider circuit to the terminals a, b, and c in the area surrounded by dotted lines, the BLD input gate in Fig.
Can create street conditions. The eight states are stored in an external storage device.
When the 8 states are added to the BLD resistor divider circuit in Figure 4, the transmission gate, labeled TG, turns on and off, resulting in 8 resistance states.
Eight different voltages are generated. After selecting the best voltage among the eight voltages, each state (high or low) of a, b, and c that generated that voltage can be changed to C 1 , C 2 , and C by cutting the bonding wire. Produced by 3 . Therefore, by setting point A in Figure 1 to a high state, this time, regardless of the states of a, b, and c, the setting states of C 1 , C 2 , and C 3
The BLD circuit will now operate. Only one bonding process is required for C 1 , C 2 , and C 3 and deterioration of the bonding pads can be prevented.
第２図の回路では、C1，C2，C3をハイにしな
ければ、C1，C2，C3の端子が定まらないが、他
の方法ではC1，C2，C3にボンデイングしないで
ローにしておき、電圧検出後にボンデイングする
方法も考えられる。ボンデイングワイヤにより接
続された状態が、分割抵抗の分割点を特定した状
態である。この様な構成にすることにより、従来
機械的に抵抗の電気的接続を変更して設定電圧を
決定していたものが、電気的に抵抗の接続が変更
されることにより、電圧の設定が容易になる。ま
た、複数回抵抗が接続されることによりパツドの
表面が汚染されていたのも、この回路によれば防
止される。 In the circuit shown in Figure 2, the terminals of C 1 , C 2 , and C 3 cannot be determined unless C 1 , C 2 , and C 3 are set high, but with other methods, bonding to C 1 , C 2 , and C 3 is not possible. Another method that can be considered is to leave the voltage low and then perform bonding after detecting the voltage. The state in which the parts are connected by the bonding wire is the state in which the dividing point of the dividing resistor is specified. With this configuration, the setting voltage was determined by mechanically changing the electrical connection of the resistor, but now it is easier to set the voltage by changing the electrical connection of the resistor. become. This circuit also prevents contamination of the surface of the pad due to multiple connections of the resistor.
本発明は時計に限らず、電卓等の電池を使用す
る機器全般に応用できる。 The present invention is applicable not only to watches but also to all devices that use batteries, such as calculators.
本発明は、外付け抵抗はなく、第２図、第３
図、第４図、第６図、第７図をすべて完全内蔵
し、自分自身で最良の設定電圧を作り出すという
すぐれた動作を有するものである。 In the present invention, there is no external resistor, and FIGS.
4, 6, and 7 are all completely built-in, and it has an excellent operation in that it can create the best set voltage by itself.
第１図は、従来のBLD回路の設定電圧決定回
路、第２図は本発明のBLD回路の設定電圧決定
回路、第３図はBLD入力ゲートの回路、第４図
はBLD抵抗分割回路、第５図は分周回路からの
信号のタイミングチヤート、第６図は基準電圧発
生回路、第７図は比較回路である。
FIG. 1 shows a setting voltage determining circuit for a conventional BLD circuit, FIG. 2 shows a setting voltage determining circuit for a BLD circuit of the present invention, FIG. 3 shows a BLD input gate circuit, and FIG. 4 shows a BLD resistance divider circuit. FIG. 5 is a timing chart of signals from the frequency dividing circuit, FIG. 6 is a reference voltage generation circuit, and FIG. 7 is a comparison circuit.
Claims (1)
する分割抵抗、制御信号に基づき前記分割抵抗の
前記分割点を順次選択する選択する選択回路、前
記選択回路により選択された前記分割点の内１つ
を特定する特定手段、特定された前記分割点の電
圧を被検出電圧とする電圧検出回路を有すること
を特徴する電池電圧検出回路。1 A dividing resistor having a plurality of dividing points to which a battery voltage is applied, a selecting circuit that sequentially selects the dividing points of the dividing resistor based on a control signal, and one of the dividing points selected by the selecting circuit. 1. A battery voltage detection circuit comprising a voltage detection circuit that uses a voltage at the specified division point as a voltage to be detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56044412A JPS57158565A (en) | 1981-03-26 | 1981-03-26 | Battery life detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56044412A JPS57158565A (en) | 1981-03-26 | 1981-03-26 | Battery life detecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57158565A JPS57158565A (en) | 1982-09-30 |
| JPH0424669B2 true JPH0424669B2 (en) | 1992-04-27 |
Family
ID=12690787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56044412A Granted JPS57158565A (en) | 1981-03-26 | 1981-03-26 | Battery life detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57158565A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0762808B2 (en) * | 1985-06-10 | 1995-07-05 | カシオ計算機株式会社 | Trimming device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5191762A (en) * | 1975-10-15 | 1976-08-11 | ||
| JPS53133068A (en) * | 1977-04-26 | 1978-11-20 | Seiko Epson Corp | Voltage detecting circuit |
| JPS56140281A (en) * | 1980-04-01 | 1981-11-02 | Citizen Watch Co Ltd | Electronic timepiece |
-
1981
- 1981-03-26 JP JP56044412A patent/JPS57158565A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5191762A (en) * | 1975-10-15 | 1976-08-11 | ||
| JPS53133068A (en) * | 1977-04-26 | 1978-11-20 | Seiko Epson Corp | Voltage detecting circuit |
| JPS56140281A (en) * | 1980-04-01 | 1981-11-02 | Citizen Watch Co Ltd | Electronic timepiece |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57158565A (en) | 1982-09-30 |
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