JPH04245655A - Lead for mounting semiconductor chip - Google Patents

Abstract

PURPOSE:To provide a lead for mounting a semiconductor chip in the COG, TAB system and particularly to curtail the width (or length) of a lead forming substrate. CONSTITUTION:In regard to many leads 12 to 15 connected to a pad of a semiconductor chip, the inner leads 12a to 15a are connected with the outer leads 12b to 15b. A part of inner lead 14a is connected to a semiconductor chip passing the area under the semiconductor chip. The outer lead 12b communicating with the inner lead 12a and an outer lead 14b of the inner lead 14a connected to the semiconductor chip not passing the area under the semiconductor chip are arranged in the same side of the semiconductor chip.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to leads for mounting semiconductor chips on wiring boards in a face-down manner, particularly COG
(Chip on Glass) Connection and TAB (
This relates to leads in Tape Automated Bonding (Tape Automated Bonding) connections.

0002

[Prior Art] Figure 3 shows an insulating film or transparent substrate (glass substrate) for face-down connection of semiconductor chips.
FIG. 3 is a schematic plan view showing a conventional lead formed in FIG. The semiconductor chip 1 has pads (bumps) 2 formed on all four sides of the lower surface, and a large number of leads 2 connected to the semiconductor chip 1. A large number of leads 3 with the tips of inner leads 3a connected to the pads 2 are connected to the semiconductor chip 1.
is the outer lead 3 that communicates with the inner lead 3a.
b extends radially in all directions of the semiconductor chip 1.

FIG. 4 is a plan view of a COG-connected semiconductor chip, with a lead group 4a connected to the upper pad of the semiconductor chip 1, a lead group 4b connected to the right pad of the semiconductor chip 1, and a lead group 4b connected to the right pad of the semiconductor chip 1. The transparent substrate 5 on which the lead group 4c connected to the lower pad and the lead group 4d connected to the left side pad of the semiconductor chip 1 are formed needs to be much larger than the semiconductor chip 1.

FIG. 5 is a plan view showing a conventional lead mounting an IC chip for driving a liquid crystal display panel. In FIG. 5(a), the semiconductor chip 1 has pads formed on all four sides of its lower surface, and the semiconductor chip 1 connected to the liquid crystal display panel and its control circuit has the outer leads of the lead group 4a connected to the semiconductor chip 1. The outer leads of the lead groups 4b, 4c, and 4d are aligned below the semiconductor chip 1.

In FIG. 5(b), the semiconductor chip 1 has pads formed on three sides (top, right, and left) of the bottom surface, and the semiconductor chip 1 connected to the liquid crystal display panel and its control circuit is The outer leads of the lead group 4a are aligned above the semiconductor chip 1, and the lead groups 4b and 4 are aligned above the semiconductor chip 1.
Each outer lead of d is aligned below the semiconductor chip 1.

In FIG. 5(c), the semiconductor chip 1 has pads formed on two sides (upper and lower) of its lower surface, and the semiconductor chip 1 connected to the liquid crystal display panel and its control circuit has a lead group 4a. The outer leads of part 4a' of the lead group 4a' are aligned above the semiconductor chip 1.
Outer lead of other part 4a'' and lead group 4c
The outer leads of are aligned below the semiconductor chip 1.

[0007]

[Problem to be solved by the invention] As explained above,
The conventional leads 2 extend on all sides of the semiconductor chip 1, and the four sides of the semiconductor chip 1 require a much wider lead formation area than the semiconductor chip 1. Therefore, when the semiconductor chip 1 is a driving IC mounted on a liquid crystal display panel, the liquid crystal display panel requires an area for mounting the semiconductor chip 1 and is enlarged. However, in a liquid crystal display panel, it is not desirable to increase the size of the panel other than the display surface, and it is necessary to make the mounting area of the semiconductor chip 1 as narrow as possible.

[0008] As a solution to the above-mentioned problems, it is possible to develop a custom IC chip in which the leads are multilayered or the positions of the pads are optimized. However, multi-layered leads increase costs due to the increase in manufacturing steps, and the chip price of custom IC chips produced in small quantities increases.

[0009]

[Means for Solving the Problems] According to FIG. 1 showing an embodiment of the lead of the present invention, a large number of inner leads 12a to 15a, 22a are connected to pads of a semiconductor chip.
~27a is each outer lead 12b~1
Inner leads 5b, 22b to 27b are connected to the pads on one side of the semiconductor chip without passing under the semiconductor chip. It is characterized in that outer leads 12b, 22b, and 23b communicating with inner leads 12a, 22a, and 23a that pass through the semiconductor chip and connect to pads on the other side of the semiconductor chip are aligned on the same side of the semiconductor chip.

0010

According to the above means, for a semiconductor chip in which pads are formed on the four sides of the lower surface, the inner leads of the leads can be arranged on one to three sides of the semiconductor chip. Therefore, the width (or length) of a substrate with leads formed thereon can be made smaller than that of a conventional substrate in which inner leads are arranged on all four sides of a semiconductor chip.

[0011]

Embodiment FIG. 1 is a schematic plan view showing an embodiment of the present invention, and FIG. 2 is a schematic plan view showing another embodiment of the present invention.

In FIG. 1A, in order to mount a semiconductor chip having pads formed on all sides of the lower surface, the leads formed on the transparent substrate 11 are connected to the leads 12 connected to the pads on the upper side of the lower surface of the chip. It is divided into a lead 13 connected to a pad on the right side of the lower surface of the chip, a lead 14 connected to a pad on the lower side of the lower surface of the chip, and a lead 15 connected to a pad on the left side of the lower surface of the chip.

The plurality of leads 12 consist of an inner lead 12a whose tip is connected to a pad of the semiconductor chip, and an outer lead 12b extending in communication with the inner lead 12a. The inner leads 12a pass under the semiconductor chip when it is mounted, and the outer leads 12b are aligned below the semiconductor chip. Generally, bump electrodes with a height of several tens of micrometers are used for electrical connection (mounting) between the tips of the inner leads 12a and the semiconductor chip. Therefore, the gap created by the bump electrode is used to insulate the inner lead 12a from the lower surface of the semiconductor chip.

The plurality of leads 14 are inner leads 14.
Outer lead 14b communicates with a, and outer lead 14b is connected to the lower part of the semiconductor chip.
Align alternately with 2b. The plurality of leads 13 have an inner lead 13a connected to an outer lead 13b,
Outer lead 13b is aligned below the semiconductor chip and to the right of outer leads 12b and 14b. Outer leads 15b of the plurality of leads 15 communicate with inner leads 15a, and outer leads 15b are aligned below the semiconductor chip and to the left of outer leads 12b and 14b.

In the tape carrier shown in FIG. 1(b),
In order to mount a semiconductor chip with pads formed on all sides of the lower surface, the leads formed on the insulating film 21 such as polyimide are connected to the leads 22 and 23 connected to the pads on the upper side of the lower surface of the chip, and the leads 22 and 23 connected to the pads on the upper side of the lower surface of the chip, and the leads 22 and 23 connected to the pads on the upper side of the lower surface of the chip, and A lead 24 connects to the pad on the lower side, leads 25 and 26 connect to the pad on the lower side of the lower surface of the chip, and a lead 27 connects to the pad on the left side of the lower surface of the chip.

Each of the plurality of leads 22 and 23 includes inner leads 22a and 23a whose tips are connected to pads formed on the upper side of the lower surface of the semiconductor chip, and inner leads 22a and 23a whose tips are connected to pads formed on the upper side of the lower surface of the semiconductor chip.
It consists of outer leads 22b and 23b communicating with 2a or 23a and extending to the right or left of the semiconductor chip. The inner leads 22a and 23a pass under the semiconductor chip when it is mounted. Generally, bump electrodes with a height of several tens of micrometers are used for electrical connection (mounting) between the tips of the inner leads 22a and 23a and the semiconductor chip. Therefore, the inner leads 22a, 2
The gap created by the bump electrodes is used to insulate the semiconductor chip 3a from the lower surface of the semiconductor chip.

The plurality of leads 25 are inner leads 25.
The outer lead 25b is connected to the outer lead 2 on the right side of the semiconductor chip.
Align alternately with 2b. The plurality of leads 26 have inner leads 26a and outer leads 26b communicating with each other,
The outer leads 26b are aligned alternately with the outer leads 23b on the left side of the semiconductor chip. The plurality of leads 24 include an inner lead 24a and an outer lead 24b.
are in communication, and the outer lead 24b is aligned to the right of the semiconductor chip and above the outer leads 22b and 25b. The plurality of leads 27 have an inner lead 27a connected to an outer lead 27b, and the outer lead 27
b is the left side of the semiconductor chip, outer lead 23b, 2
Align above 6b.

The insulating film 21 has each lead 22 to 2.
A device hole 28 in which the tips of the inner leads 22a to 27a of No. 7 are exposed, and a pair of bonding holes 29 in which the connecting portions of the outer leads 22b to 27b of the leads 22 to 27 are exposed are provided.

Such leads 12 to 15 or 22 to
27 outer leads 12b ~ 15b, 22b ~ 2
7b connects to the semiconductor chip from three sides. Therefore,
The width W of the transparent substrate 11 or the insulating film 21 can be made much narrower than the conventional ones, for example, to about 3/5.

In the embodiment shown in FIG. 1, the inner leads 12a, 22a, 23a passing under the semiconductor chip are as follows:
When a semiconductor chip is mounted, a gap of several micrometers created by the bump electrodes prevents contact with the bottom surface of the semiconductor chip. To further ensure this non-contact, an insulating layer as shown in Figure 2 is effective. .

In FIG. 2(A), in which the same reference numerals are used for parts common to FIG. 1(A), a lead 12 is attached to a transparent substrate 11.
15 are formed, and the inner leads 12a have their tips connected to the semiconductor chip exposed and covered with an insulating layer 31. Each outer lead 12b to 14b of leads 12 to 14
are aligned below the semiconductor chip, and outer leads 15b of the leads 15 are aligned above the semiconductor chip. Therefore, the mounted semiconductor chip is attached to the outer lead 15b.
to the upper circuit through the outer lead 12b.
It will be connected to the lower circuit via ~14b. For example, an insulating layer 31 made of SiN or the like with a thickness of several μm.
Since the inner lead 12a is covered except for the tip portion connected to the semiconductor chip, the insulation between the inner lead 12a and the lower surface of the mounted semiconductor chip is excellent.

In FIG. 2B, in which the same reference numerals are used for parts common to FIG.
They are provided when forming the device hole 28 in the insulating film 21, and the four corners communicate with the insulating film 21. The leads 22 to 27 are the same as those shown in FIG. 1B, but the provision of the insulating layer 32 provides excellent insulation between the inner leads 22a and the lower surface of the mounted semiconductor chip.

[0023]

[Effects of the Invention] As explained above, according to the present invention, for a semiconductor chip in which pads are formed on the four sides of the lower surface, the inner leads of the leads can be arranged on one to three sides of the semiconductor chip. . Therefore, a substrate on which leads according to the present invention are formed has a smaller width (or length) dimension and is more compact than a conventional substrate in which inner leads are provided on the four sides of a semiconductor chip.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of a lead according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of a lead according to another embodiment of the present invention.

FIG. 3 is a schematic plan view of a conventional lead for connecting semiconductor chips.

FIG. 4 is a plan view of a COG-connected semiconductor chip.

FIG. 5 is a plan view showing a conventional lead on which a driving IC chip for a liquid crystal display panel is mounted.

[Explanation of symbols]

12-15, 22-27 are leads 12a-15a, 22a-27a are inner leads 12b-15b, 22b-27b are outer leads 21 are insulating films 31, 32 are insulating layers

Claims (5)

[Claims] Claim 1: A large number of inner leads (12a to 15a, 22a to 27) connected to pads of a semiconductor chip.
a) is each outer lead (12b to 15b, 2
2b to 27b), and inner leads (14a, 25a, 26a) that connect to pads on one side of the semiconductor chip without passing under the semiconductor chip; and outer leads (14b, 25b, 26b) that communicate with , inner leads (12a, 22a, 23a) passing under the semiconductor chip and connecting to pads on the other side of the semiconductor chip.
Outer leads (12b, 22b, 23b) that communicate with
A lead for mounting a semiconductor chip, wherein the leads are aligned on the same side of the semiconductor chip. Claim 2: The outer lead (12b to 15b
, 22b to 27b) are arranged separately on one to three sides of the semiconductor chip. 3. The outer lead (12b to 15b
, 22b to 27b) are arranged separately in two directions on one opposing side of the semiconductor chip. 4. The inner lead (12a, 22a, 23a) passing under the semiconductor chip has an insulating layer (31, 32) coated on the surface except for the connection portion at the tip. The lead for semiconductor chip mounting according to claim 1. 5. The lead for semiconductor chip mounting according to claim 2, wherein the insulating layer (32) is a part of an insulating film (21) in a tape carrier.