CN217825516U - Chip package and electronic device - Google Patents

Abstract

The application discloses chip package and electron device, this chip package includes: the circuit board comprises a circuit bottom plate, at least two first bonding pads in a long strip shape, at least two second bonding pads in a circular shape and a chip; at least two circular solder mask windowing areas are formed on one side face of the circuit base plate at intervals, at least two soldering tin bumps are arranged on the chip, and at least two first pads, at least two second pads and at least two soldering tin bumps are sequentially and correspondingly stacked on the at least two solder mask windowing areas so as to enable the chip to be connected with the circuit base plate; and the diameter of the windowing region of the solder mask layer is smaller than the length of the first bonding pad and larger than the width of the first bonding pad, and the diameter of the second bonding pad is larger than the width of the first bonding pad and not larger than the diameter of the windowing region of the solder mask layer. Through the mode, the chip packaging body can effectively reduce the level number of the circuit substrate and reduce the difficulty of the manufacturing process of the chip packaging body.

Description

Chip package and electronic device

Technical Field

The present disclosure relates to chip technologies, and particularly to a chip package and an electronic device.

Background

In System In Package (SiP) technology, multiple functional chips are usually integrated into one Package to realize a substantially complete function. The SiP design technology mainly includes Bonding Wires (WB), die Side By Side, die Stack, flip Chip mounting (Flip Chip, FC), double-sided device layout (Double Side Passive), and the like.

In the solder bump (a solder-bumped chip pad in flip chip mounting) structure manufactured by the conventional FC technology, bump pads (metal regions of solder bumps on a circuit substrate, namely, bump pads) are generally manufactured into a circular shape, and the minimum bump pitch (the distance between the center points of two bump pads) can be 180 micrometers (micrometers) according to the process level of the conventional circuit substrate factories and sealing and testing factories. However, according to the conventional design manner of the chip package, due to the limitation of the bump pad size (the size of the metal area of the bump pad on the circuit substrate), that is, the bump pad size is usually set to be the solder mask open size) +50um, and this will cause the bump space (the minimum distance between the inner edges of two bump pads) between every two adjacent bump pads to be too small, so that only the outermost bump pads on the FC chip in the chip package can be routed on the surface layer of the corresponding circuit substrate, and the inner bump pads can only be routed from the inner layer of the circuit substrate in the form of via holes, thereby increasing the number of layers of the circuit substrate, increasing the corresponding process difficulty, and increasing the processing cost of the product.

SUMMERY OF THE UTILITY MODEL

The application provides a chip packaging body and an electronic device, which are used for solving the problems that the minimum distance between the inner side edges of every two adjacent soldering tin bumps in the chip packaging body manufactured by the prior art is too small, so that the bump pad of the inner ring of an FC chip can only be led out from the inner layer of a circuit substrate in a via hole punching mode, the layer number of the circuit substrate is increased, the manufacturing process difficulty of the chip packaging body is increased, and the processing cost of a product is increased.

In order to solve the technical problem, the application adopts a technical scheme that: provided is a chip package, wherein the chip package includes: the circuit comprises a circuit base plate, a plurality of solder mask layer windows and a plurality of solder mask layer windows, wherein at least two circular solder mask layer windows are formed on one side surface of the circuit base plate at intervals; at least two first bonding pads in a long strip shape are respectively and correspondingly arranged on the windowing areas of the at least two solder mask layers; the diameter of the windowing region of the solder mask layer is smaller than the length of the first bonding pad and larger than the width of the first bonding pad; at least two second bonding pads which are circular are respectively and correspondingly arranged on the at least two first bonding pads; the diameter of the second bonding pad is larger than the width of the first bonding pad and is not larger than the diameter of the windowing area of the solder mask layer; the chip is provided with at least two soldering tin bumps which are respectively and correspondingly connected with at least two second bonding pads, so that the chip is connected with the circuit base plate through the second bonding pads, the first bonding pads and the windowing region of the solder mask layer.

The solder bump is circular, and the diameter of the second pad is not larger than that of the solder bump.

The solder bump is circular, and the diameter of the second pad is not smaller than that of the solder bump.

Wherein, the two opposite sides of the first pad in the width direction are arc-shaped.

Wherein the diameter of the second bonding pad is not less than 50 microns.

Wherein the minimum distance between every two adjacent solder mask windowing areas is not less than 80 microns.

Wherein the minimum distance between every two adjacent solder bumps is not less than 100 microns.

The chip packaging body further comprises at least two point glue layers, and the at least two point glue layers respectively and correspondingly cover the at least two solder mask windowing areas.

The chip packaging body further comprises an insulating layer, wherein the insulating layer is arranged on one side face of the circuit bottom plate and covers the chip, the window area of the solder mask layer, the first bonding pad and the second bonding pad.

In order to solve the above technical problem, the present application adopts another technical solution: there is provided an electronic device, wherein the electronic device comprises a chip package as defined in any one of the above.

The beneficial effect of this application is: unlike the case of the prior art, the chip package in the present application includes: the circuit board comprises a circuit bottom plate, at least two strip-shaped first bonding pads, at least two round second bonding pads and a chip; at least two circular solder mask windowing areas are formed on one side face of the circuit base plate at intervals, at least two soldering tin bumps are arranged on the chip, and at least two first pads, at least two second pads and at least two soldering tin bumps are sequentially and correspondingly stacked on the at least two solder mask windowing areas so that the chip is connected with the circuit base plate through the soldering tin bumps, the second pads, the first pads and the solder mask windowing areas; and the diameter of the windowing region of the solder mask layer is smaller than the length of the first bonding pad and larger than the width of the first bonding pad, and the diameter of the second bonding pad is larger than the width of the first bonding pad and not larger than the diameter of the windowing region of the solder mask layer. Therefore, the chip is connected with the circuit base plate by adopting the overlapped strip-shaped first bonding pad and the circular second bonding pad, the diameter of the second bonding pad is not more than that of the solder mask windowing area, the limitation of the manufacturing process that the size of the bonding pad in the chip packaging body is usually larger than that of the solder mask windowing area is effectively broken through, the minimum distance between every two adjacent second bonding pads is effectively increased, the wiring distance of every two adjacent bumps on the outer layer of the circuit base plate is also increased, each soldering tin bump of the chip in the chip packaging body can be wired on the outer layer of the circuit base plate without being wired on the inner layer of the circuit base plate in a via hole punching mode, the layer number of the circuit base plate can be effectively reduced, the manufacturing process difficulty of the chip packaging body is reduced, and the processing cost of corresponding products can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic diagram of a partial structure of a chip package in the prior art;

FIG. 2 is a schematic structural diagram of a chip package according to a first embodiment of the present application;

fig. 3 is a schematic structural diagram of an embodiment of an electronic device according to the present application.

Detailed Description

In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present application clearer, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

At present, as shown in fig. 1, fig. 1 is a partial structural schematic diagram of a chip package in the prior art. The chip package 10 specifically includes a circuit board 11, at least two pads 12 (shown specifically in the figure, bump pads corresponding to the pads, that is, bump pads), and a chip (not shown), where the chip has at least two pins, and each pin corresponds to a solder bump 13, that is, a UBM; ink windowing areas 111 for welding chip pins, namely, solder mask openings, are further formed on one side face of the circuit substrate 11 at intervals, the at least two pads 12 are respectively and correspondingly arranged on the at least two ink windowing areas 111, and the at least two solder bumps 13 can be respectively and correspondingly arranged on the at least two pads 12, so that the chip can be connected with the circuit substrate 11.

In the conventional manufacturing process of the chip package, taking the diameter of the common solder bump 13 as an example, it is known that, in the normal case, the solder mask open size is not less than 1.2UBM size, that is, the diameter of the ink window area 111 is not less than 1.2 times the diameter of the solder bump 13, so the diameter of the ink window area 111 is 1.2 × 80 μm =100 μm as a reference; further, the bump pad size may be set to be a filler mask open size +50 μm as a conventional rule, that is, the diameter of the pad 12 is the sum of the diameter of the ink windowing region 111 plus 50 μm, so the diameter of the pad 12 may be selected to be 150 μm.

It is understood that the value bump pitch of D1 in FIG. 1, i.e. the distance between the center points of two bonding pads 12, can be 180 μm according to the processing capability of the conventional circuit substrate factory, so that the value D1 in FIG. 1 can be selected to be 180 μm for reference; in fig. 1, the value of d1 is bump space, i.e., the minimum distance between the inner edges of the two pads 12, and d1= bump pitch-bump pad size, i.e., d1min =180-150=30 μm according to the design scheme of fig. 1.

However, according to the processing capability of the existing circuit substrate factory, the thinnest trace can be 15 μm, and the distance between the trace and the pad 12 needs to be kept to be not less than 15 μm, that is, the minimum distance between the inner side edges of two pads 12 needs to be at least 45 μm, so that the trace can be performed between every two adjacent pads 12, and obviously, the existing design manner of the pad 12 in fig. 1 does not meet this requirement.

Similarly, other components mounted on the circuit substrate 11 with too small a pitch between two adjacent pins have similar problems.

In order to increase the wiring distance of every two adjacent chip pins on the outer layer of the circuit bottom plate 11, the manufacturing process difficulty of the chip packaging body is reduced, and then the processing cost of corresponding products is reduced, the application provides a storage device.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip package according to a first embodiment of the present application. In the present embodiment, the chip package 20 includes: a circuit substrate 21, at least two first pads 22, at least two second pads 23 and a chip (not shown).

The chip package 20 is a high-density circuit board including a mounted or embedded chip, and the chip has at least two pins arranged at intervals, so that each pin can be soldered to a part or all of the pads on the circuit board 21, and the chip and the circuit board 21 are connected, and then each pin is routed on the outer layer and/or the inner layer of the circuit board 21 according to a pre-designed electrical logic, so as to implement a corresponding signal function. In other embodiments, the chip may be any other reasonable mounted or embedded component that needs to be mounted on the circuit substrate 21 and has a small distance between two adjacent leads, which is not limited in the present application.

Specifically, the circuit board 21 may be understood as a circuit substrate including one or more of any reasonable circuit board components such as a patterned copper-clad layer, a prepreg, a molding layer, a pad, and a package element, which can implement electrical connection between functional elements, so as to implement the circuit design logic of the chip package 20.

At least two solder mask windowing areas 211 used for welding chip pins are further formed on one side face of the circuit bottom plate 21 at intervals, and the solder mask windowing areas 211, namely the ink windowing areas 211, are circular.

Further, at least two first pads 22 are correspondingly disposed on at least two solder mask windowing regions 211, respectively, that is, each of the first pads 22 is correspondingly disposed on one of the solder mask windowing regions 211.

It can be understood that the number of the solder mask windowing regions 211 on one side of the circuit substrate 21 may be greater than the number of the first pads 22, or equal to the number of the first pads 22, and when the number of the solder mask windowing regions 211 is greater than the number of the first pads 22, the solder mask windowing regions 211 without the first pads 22 may also be used for pin soldering of other mounted or embedded components, which is not limited in the present application.

The first pad 22 is a strip, and the diameter of the solder mask opening region 211 is smaller than the length of the first pad 22 and larger than the width of the first pad 22, so that the chip package 20 can be manufactured by a conventional chip package 20 manufacturing process without breaking through the limit process level of the existing chip package 20 manufacturing plant.

Still further, the at least two second pads 23 are respectively and correspondingly disposed on the at least two first pads 22, that is, each of the second pads 23 is correspondingly disposed on one of the first pads 22.

The second pad 23 is circular, and the diameter of the second pad 23 is greater than the width of the first pad 22 and not greater than the diameter of the solder mask windowing region 211, so that the second pad 23 obtained by manufacturing can be guaranteed to have a smaller size as much as possible, and meanwhile, the stability of welding between the chip pin and the circuit board 21 of the first pad 22 can be enhanced through the second pad 23, so that the welding between the chip pin and the circuit board is tighter.

Furthermore, the chip has at least two pins disposed at intervals, and each of the pins is correspondingly provided with a solder bump 24, so that the chip can be connected to the circuit board 21 through the second pads 23, the first pads 22, and the solder mask windowing region 211 by correspondingly connecting the at least two solder bumps 24 to the at least two second pads 23, respectively.

In the above scheme, the chip is connected to the circuit board 21 by using the overlapped strip-shaped first pad 22 and the circular second pad 23, and the diameter of the second pad 23 is not greater than that of the solder mask windowing region 211, which effectively breaks through the limitation that the size of the pad in the chip package 20 is usually greater than that of the solder mask windowing region 211, thereby effectively increasing the minimum distance between every two adjacent second pads 23, and also increasing the routing distance of every two adjacent solder bumps 24 on the outer layer of the circuit board 21, and enabling each solder bump 24 of the chip in the chip package 20 to route on the outer layer of the circuit board 21 without routing on the inner layer of the circuit board 21 in a via hole manner, thereby effectively reducing the layer number of the circuit board 21, reducing the process difficulty of manufacturing the chip package 20, and further reducing the processing cost of corresponding products.

Alternatively, the solder bump 24 is circular and the diameter of the second pad 23 is not larger than the diameter of the solder mask opening region 211 and not smaller than the diameter of the solder bump 24.

Preferably, the solder bumps 24 are circular, and the diameter of the second pads 23 is greater than the width of the first pads 22 and is not greater than the diameter of the solder bumps 24, so that the second pads 23 obtained by manufacturing can be ensured to have a smaller size as much as possible, the wiring distance between every two adjacent solder bumps 24 on the outer layer of the circuit substrate 21 can be increased as much as possible, and the stability of the welding between the chip pins and the circuit substrate 21 can be enhanced by the second pads 23 for the first pads 22, so that the welding between the chip pins and the circuit substrate 21 is tighter.

Optionally, the first pad 22 is rectangular, or two opposite sides in the width direction thereof, that is, the short side of the first pad 22 is in an arc shape or a wave shape, which is any reasonable strip shape similar to a rectangle, and this application does not limit this.

Optionally, the diameter of the second bonding pad 23 is not less than 50 μm, so as to ensure that the second bonding pad 23 can correspondingly achieve its main function, and the integrity and normal usability of the second bonding pad 23 can be ensured while the soldering capability of the first bonding pad 22 and the circuit substrate 21 is increased.

Optionally, the minimum distance between every two adjacent solder mask windowing regions 211 is not less than 80 microns.

Alternatively, the minimum distance between the center points of every two adjacent first pads 22, i.e., the distance D2 shown in fig. 2, is not less than 180 micrometers.

Optionally, a minimum distance between each two adjacent solder bumps 24, that is, a distance d2 shown in fig. 2 is not less than 100 micrometers, so as to facilitate routing of the chip pins corresponding to each two adjacent solder bumps 24 on the outer layer of the circuit substrate 21.

It can be understood that the distance d2 is a distance reserved for outer layer routing of every two adjacent pins of the chip, and it can be known that, since the minimum requirement of one wire is 45 micrometers, the distance d2 can correspondingly meet the requirements of at least two wires.

In an embodiment, the chip package 20 further includes at least two dispensing layers (not shown), and the at least two dispensing layers respectively cover the at least two solder mask windowing regions 211, and are mutually matched with the chip and the circuit board 21 to cover each solder mask windowing region 211, the first pad 22, the second pad 23, and the solder bump 24, so as to protect them and avoid adverse effects such as short circuit and electrical leakage.

In an embodiment, the chip package 20 further includes an insulating layer (not shown), and the insulating layer is disposed on a side surface of the circuit substrate 21 and covers the chip, the solder mask windowing region 211, the first pad 22 and the second pad 23 to protect them and avoid adverse effects such as short circuit and electrical leakage. And a circuit board package may be further disposed on the insulating layer, which is not limited in this application.

For convenience of illustration, in a specific embodiment, under the condition of not changing the existing circuit board manufacturing process level, taking the size of the first pad 22 as 30 × 150um as an example, it can be known that, when the diameter of the solder bump 24 is 80 μm, and the diameter of the solder mask windowing region 211 is 100 μm, and in order to ensure that the second pad 23 can correspondingly realize its main function, the soldering capability between the first pad 22 and the circuit board 21 is increased, and the integrity and normal usability of the second pad 23 is ensured, and when the diameter of the second pad is 50um, the minimum distance D2 between the central points of every two adjacent first pads 22 can be 180 μm, and correspondingly, the distance between every two adjacent pins of the chip on the outer layer of the circuit board 21 is reserved, that is, the minimum distance D2=180um-80um =100um between the inner side edges of every two adjacent solder bumps 24 is also reserved.

It can be understood that, according to the processing capability of the existing circuit substrate factory, the thinnest wire can be 15um, the distance between the wire and the pad needs to be kept at 15um, and the distance between the wire and the pad needs to be kept at 15um, then the wire distance d2 capable of being provided is calculated as 100um, at least 2 wires can be arranged between every two adjacent chip pins, the problem that the wire outlet of the outermost pad of the circuit bottom plate 21 is difficult is directly solved, the wire outlet does not need to be carried out on the inner layer of the circuit bottom plate 21 in a via hole punching mode, and therefore the layer number of the circuit bottom plate 21 can be effectively reduced, the difficulty of the manufacturing process of the chip package 20 is reduced, and the processing cost of corresponding products is further reduced.

It can be seen that the minimum distance D2 between the center points of every two adjacent first pads 22 mentioned in this embodiment is stated according to the currently recommended value of 180um, which means that in the actual design, the distance D2 may also be larger than 180um, that is, by designing the appropriate size of the second pad 23, the number of allowed traces between two adjacent chip pins can be effectively increased, and the optimal solution is reached, so that the corresponding electrical design difficulty can be more effectively reduced, the number of design layers of the circuit board 21 is reduced, and the cost of the corresponding product can be reduced.

In addition, the present application further provides an electronic device, please refer to fig. 3, and fig. 3 is a schematic structural diagram of an embodiment of the electronic device according to the present application. The electronic device 31 includes a chip package 311, and the chip package 311 is the chip package 20 described above, which is not described herein again.

Unlike the case of the prior art, the chip package in the present application includes: the circuit board comprises a circuit bottom plate, at least two strip-shaped first bonding pads, at least two round second bonding pads and a chip; at least two circular solder mask windowing areas are formed on one side face of the circuit base plate at intervals, at least two soldering tin bumps are arranged on the chip, and at least two first soldering pads, at least two second soldering pads and at least two soldering tin bumps are sequentially arranged on the at least two solder mask windowing areas in a corresponding laminating mode so that the chip is connected with the circuit base plate through the soldering tin bumps, the second soldering pads, the first soldering pads and the solder mask windowing areas; and the diameter of the windowing region of the solder mask layer is smaller than the length of the first bonding pad and larger than the width of the first bonding pad, and the diameter of the second bonding pad is larger than the width of the first bonding pad and not larger than the diameter of the windowing region of the solder mask layer. Therefore, the chip is connected with the circuit base plate by adopting the overlapped strip-shaped first bonding pad and the circular second bonding pad, the diameter of the second bonding pad is not more than that of the solder mask windowing area, the limitation of the manufacturing process that the size of the bonding pad in the chip packaging body is usually larger than that of the solder mask windowing area is effectively broken through, the minimum distance between every two adjacent second bonding pads is effectively increased, the wiring distance of every two adjacent bumps on the outer layer of the circuit base plate is also increased, each soldering tin bump of the chip in the chip packaging body can be wired on the outer layer of the circuit base plate without being wired on the inner layer of the circuit base plate in a via hole punching mode, the layer number of the circuit base plate can be effectively reduced, the manufacturing process difficulty of the chip packaging body is reduced, and the processing cost of corresponding products can be reduced.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims (10)

1. A chip package, comprising:

the circuit comprises a circuit base plate, a plurality of solder mask layer windows and a plurality of solder mask layer windows, wherein at least two circular solder mask layer windows are formed on one side surface of the circuit base plate at intervals;

at least two strip-shaped first welding pads are correspondingly arranged on at least two windowing areas of the solder mask layer respectively; the diameter of the windowing area of the solder mask layer is smaller than the length of the first bonding pad and larger than the width of the first bonding pad;

at least two second bonding pads which are circular are respectively and correspondingly arranged on the at least two first bonding pads; the diameter of the second bonding pad is larger than the width of the first bonding pad and not larger than the diameter of a windowing area of the solder mask layer;

the chip, be equipped with two at least soldering tin lugs on the chip, two at least soldering tin lugs correspond respectively and connect two at least the second pad, so that the chip by the second pad, first pad and solder mask windowing region with circuit board is connected.

2. The chip package of claim 1,

the solder bump is circular, and the diameter of the second pad is not greater than the diameter of the solder bump.

3. The chip package of claim 1,

the solder bump is circular, and the diameter of the second pad is not smaller than that of the solder bump.

4. The chip package of claim 1,

the two opposite sides of the first bonding pad in the width direction are arc-shaped.

5. The chip package of claim 1,

the diameter of the second bonding pad is not less than 50 micrometers.

6. The chip package according to any one of claims 1 to 5,

the minimum distance between every two adjacent solder mask windowing areas is not less than 80 micrometers.

7. The chip package according to any one of claims 1 to 5,

the minimum distance between every two adjacent solder bumps is not less than 100 micrometers.

8. The chip package according to any one of claims 1-5,

the chip packaging body further comprises at least two dispensing layers, and the at least two dispensing layers respectively and correspondingly cover the at least two windowing regions of the solder mask layer.

9. The chip package according to any one of claims 1-5,

the chip packaging body further comprises an insulating layer, wherein the insulating layer is arranged on one side face of the circuit bottom plate and coats the chip, the window area of the solder mask layer, the first bonding pad and the second bonding pad.

10. An electronic device, characterized in that the electronic device comprises a chip package according to any one of claims 1-9.

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