CN103165563B - Package and method - Google Patents

Package and method Download PDF

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Publication number
CN103165563B
CN103165563B CN201110451247.1A CN201110451247A CN103165563B CN 103165563 B CN103165563 B CN 103165563B CN 201110451247 A CN201110451247 A CN 201110451247A CN 103165563 B CN103165563 B CN 103165563B
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China
Prior art keywords
fence
package
encapsulant
semiconductor package
carrier plate
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CN201110451247.1A
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Chinese (zh)
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CN103165563A (en
Inventor
钟匡能
钟兴隆
方颢儒
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矽品精密工业股份有限公司
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Priority to TW100146746A priority Critical patent/TWI474462B/en
Priority to TW100146746 priority
Application filed by 矽品精密工业股份有限公司 filed Critical 矽品精密工业股份有限公司
Publication of CN103165563A publication Critical patent/CN103165563A/en
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Publication of CN103165563B publication Critical patent/CN103165563B/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

一种半导体封装件及其制法,该半导体封装件通过于具有多个封装体的载板上设置挡架,令该挡架设于该些封装体之间,且以封装胶体包覆该些封装体并露出该挡架,又于该封装胶体上形成电性连接该挡架的屏蔽组件,借以提升电磁遮蔽的功效。 A semiconductor package and method, the semiconductor package to the carrier plate by a fence provided with a plurality of packages, enabling the blocking between the plurality of erected package body, and to encapsulating the encapsulant package and exposing the fence, and the formation of the shielding assembly is electrically connected to the fence, in order to enhance the electromagnetic shielding effect on the encapsulant.

Description

半导体封装件及其制法 Package and method

技术领域 FIELD

[0001] 本发明关于一种半导体封装件,尤指一种防电磁干扰的半导体封装件及其制法。 [0001] The present invention relates to a semiconductor package, especially an anti-EMI package and method.

背景技术 Background technique

[0002] 随着电子产品轻薄短小及系统整合的趋势,现今已发展出一种系统级封装(System in package ;SIP),将一个或多个芯片、被动组件等不同的电子组件整合在同一个封装件中,当整合的组件含有射频(Rad1 frequency, RF)组件或其它电磁组件,容易造成邻近其它电子组件的电磁干扰(Electromagnetic Interference简称EMI),且封装件中的电子组件积集度日益增加,使得各该电子组件之间的相对位置越来越靠近,所以各该电子组件之间的EMI问题更显重要。 [0002] As electronic products short, light and system integration trend, has now been developed a system-in-package (System in package; SIP), one or more chips, passive components, such as different electronic components integrated in the same the package, when the integrated component comprising a radio frequency (Rad1 frequency, RF) components or other electromagnetic components, likely to cause electromagnetic interference near other electronic components (electromagnetic interference referred to as the EMI), and the electronic component product set of the package member increasing so that the relative position between each of the electronic components closer and closer, so EMI problems between the electronic component is more important.

[0003] 第7701040号美国专利揭露一种防电磁干扰的半导体封装件,如图1所不,于一承载件10上形成具有屏蔽层11的多个基板12,且各该基板12上设有多个封装体,如射屏(RF)单元16a与基频(base band)单元16b,而各该基板12的侧边具有电性连接垫120以供结合焊锡凸块,又于该基板12的边缘、射屏单元16a及基频单元16b上镀覆另一屏蔽层13。 [0003] U.S. Patent No. 7,701,040 discloses a semiconductor package EMI shielding member, not shown in FIG 1, substrate 12 has a plurality of shield layer 11 on a carrier member 10, and is provided on each of the substrates 12 a plurality of packages, such as a reflective screen (RF) unit 16a and the base frequency (base band) unit 16b, and each of the sides of the substrate 12 having a pad 120 is electrically connected to solder bumps for binding, but also on the substrate 12, edge, the plating unit 16a and the output screen baseband unit 16b further shield layer 13. 最后,移除该承载件10,以获取多个个半导体封装件1。 Finally, the carrier 10 is removed, to obtain a plurality of semiconductor packages.

[0004] 然而,现有半导体封装件1中,该屏蔽层13不能形成于该电性连接垫120上,否则会造成短路,所以于该电性连接垫120上先形成光阻,待形成屏蔽层13之后,移除该光阻以外露电性连接垫120,致使工艺繁杂且增加工艺时间,导致制作成本提高。 [0004] However, the conventional semiconductor package 1, the shielding layer 13 is not formed on the conductive pads 120, which will cause a short circuit, so that in the electrical connection pads 120 formed in the first photoresist mask to be formed after the layer 13, the exposed photoresist is removed outside the electrically connecting pad 120, causing the process complicated and increases the process time, resulting in the production costs.

[0005] 然而,如何克服现有技术的种种问题,实为一重要课题。 [0005] However, how to overcome the problems of the prior art, it is a real important issue.

发明内容 SUMMARY

[0006] 为解决上述现有技术的种种问题,本发明提供一种半导体封装件,包括:载板;多个封装体,设于该载板上;挡架,设于该载板上,并位于该些封装体之间;封装胶体,形成于该载板上,以包覆该些封装体与该挡架,并令该挡架的部分表面外露于该封装胶体;以及屏蔽组件,电性连接该挡架。 [0006] In order to solve the above-described problems of the prior art, the present invention provides a semiconductor package, comprising: a carrier plate; a plurality of packages, provided on the carrier board; fence, provided on the carrier plate, and located between the plurality of packages; encapsulant, formed on the carrier board, encapsulating the package body and the fence, and to make part of the surface of the fence is exposed from the encapsulant; and a shield assembly electrically connected to the fence.

[0007] 本发明还提供一种半导体封装件的制法,包括:提供一载板;形成多个封装体于该载板上;设置挡架于该些封装体之间;形成封装胶体于该载板上,以包覆该些封装体与该挡架,并令该挡架的部分表面外露于该封装胶体;以及将一屏蔽组件电性连接该挡架。 [0007] The present invention further provides a manufacturing method of a semiconductor package, comprising: providing a carrier plate; a plurality of packages are formed in the carrier plate; fence disposed between the plurality of package body; formed on the encapsulant carrier board, encapsulating the package body and the fence, and to make part of the surface of the fence is exposed from the encapsulant; and a shield assembly electrically connected to the fence.

[0008] 前述的半导体封装件及其制法,该屏蔽组件可为以溅镀方式形成于该封装体上的金属层。 [0008] The aforementioned semiconductor package and method, the shielding assembly may be formed on the metal layer of the package by sputtering manner. 或者,该屏蔽组件可为金属盖,盖设于该封装体上。 Alternatively, the component may be a metal shield cover that is provided on the package body.

[0009] 前述的半导体封装件及其制法,形成该挡架的材质可为导电材,且该挡架可具有挡板,以借之立设于该载板上并位于各该封装体之间。 [0009] The aforementioned semiconductor package and method, in forming the fence may be made of a conductive material, and the fence may have a baffle, to take the upright on the carrier plate and is located in each of the package of between.

[0010]另外,前述的半导体封装件及其制法,该封装体可为半导体芯片或具有半导体芯片的封装结构。 [0010] Further, the above-described semiconductor package and fabrication method thereof, which may be a package having a semiconductor chip or a semiconductor chip packaging structure.

[0011] 由上可知,本发明半导体封装件及其制法,借由屏蔽组件形成于该封装胶体上,且借由该挡架与该屏蔽组件作为屏蔽结构,所以相比于现有技术,本发明的封装体周围均有屏蔽结构,因而可有效防止外界电磁波干扰该些封装体的内部电路。 [0011] From the above, a semiconductor package and method of the present invention, the shield assembly is formed by means on the encapsulant, and by means of the fence assembly with the shield as the shield structure, as compared to the prior art, around the package of the present invention have a shielding structure, which can effectively prevent external electromagnetic interference the internal circuit of the plurality of packages.

[0012] 此外,借由该挡架的设计及屏蔽组件形成于该封装胶体上,因而无需考量该载板的线路布设,所以相比于现有技术,本发明的工艺更简易,且工艺时间更短,因而可降低制作成本。 [0012] In addition, the fence is formed by means of the design and assembly of the shield on the encapsulant, there is no need to consider circuit layout of the carrier plate, as compared to the prior art, the process of the present invention is more simplified, and the process time shorter, thus reducing manufacturing cost.

附图说明 BRIEF DESCRIPTION

[0013] 图1用于显示第7701040号美国专利的半导体封装件的制法的剖面示意图; [0013] FIG. 1 shows a schematic cross section of a manufacturing method of U.S. Patent No. 7,701,040 a semiconductor package;

[0014] 图2A至图2D为本发明半导体封装件的剖面示意图;其中,图2C'及图2D'为图2C及图2D的其它实施例;以及 [0014] FIGS. 2A to a cross-sectional view of a semiconductor package of the present invention, FIG 2D; wherein FIG. 2C 'and 2D' for the other embodiments of FIGS. 2C and 2D; and

[0015]图3A至图3B为本发明半导体封装件的另一实施例的立体示意图。 [0015] FIGS. 3A-3B a perspective view of another embodiment of a semiconductor package of embodiments of the present invention.

[0016] 主要组件符号说明 [0016] Description of Symbols major components

[0017] 1,2,2' 半导体封装件 [0017] 2, 2 'of the semiconductor package

[0018] 10 承载件 [0018] The carrier member 10

[0019] 11、13 屏蔽层 [0019] The shielding layer 11, 13

[0020] 12 基板 [0020] The substrate 12

[0021] 120 电性连接垫 [0021] The conductive pad 120

[0022] 16a 射频单元 [0022] 16a radio unit

[0023] 16b 基频单元 [0023] 16b baseband unit

[0024] 20 载板 [0024] The carrier plate 20

[0025] 202 焊球 [0025] 202 solder balls

[0026] 22a 第一封装体 [0026] 22a of the first package body

[0027] 22b 第二封装体 [0027] 22b of the second package body

[0028] 220a, 220b 封装基板 [0028] 220a, 220b of the package substrate

[0029] 221a 第一芯片 [0029] 221a first chip

[0030] 221b 第二芯片 [0030] 221b second chip

[0031] 222a 焊线 [0031] 222a bond wire

[0032] 222b 焊锡凸块 [0032] 222b solder bumps

[0033] 223,27,27',37 封装胶体 [0033] 223,27,27 ', encapsulant 37

[0034] 26,36 挡架 [0034] 26,36 fence

[0035] 260, 360 挡板 [0035] 260, the shutter 360

[0036] 270 开口 [0036] 270 opening

[0037] 28,28' 屏蔽组件 [0037] 28, 28 'shield assembly

[0038] 32a, 32b, 32c 封装体。 [0038] 32a, 32b, 32c package.

具体实施方式 Detailed ways

[0039] 以下借由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。 [0039] described by the following embodiments of the present invention by certain specific embodiments, those skilled in the art may be disclosed in the present specification easily understand other advantages and effects of the present invention.

[0040] 须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,所以不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。 [0040] Information, the accompanying drawings of the present specification, the structure illustrated, the proportion and size, to match the content of the description are merely disclosed, for reading and understanding of those skilled in the art, the present invention is not intended to limit Limited conditions may be implemented, it is not technically meaningful with, any modified structure, the size of the proportional relationship changes or adjustments in the object without affecting the efficacy of the present invention can be produced and can be achieved, should still fall within the scope of the technical contents disclosed in the present invention can have covers. 同时,本说明书中所引用的如“上”、“侧”、“二”及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,也当视为本发明可实施的范畴。 Meanwhile, cited in this specification as "upper", "side", "two" and "a" and other terms, is only apparent to the convenience of description, not to limit the scope of the present invention may be practiced, the relative changed or adjusted relationship, no substantial changes in the technical content, the category may be also considered as embodiments of the present invention.

[0041] 以下即配合图2A至图2D详细说明本发明的半导体封装件2的制法。 [0041] Here i.e. with FIGS. 2A to 2D detailed description of the present invention, the semiconductor package 2 of the production method.

[0042] 如图2A所示,提供一载板20,且形成第一及第二封装体22a,22b于该载板20上,该第一及第二封装体22a,22b并以焊球202电性连接该载板20。 [0042] As shown in FIG. 2A, a carrier plate 20, and forming first and second package body 22a, 22b on the carrier plate 20, the first and the second package body 22a, 22b and solder balls 202 electrically connected to the carrier plate 20. 应了解的是该载板20上可形成更多封装体,在本实施例中仅借图2A的封装体作例示说明。 It should be appreciated that the carrier plate may be formed more on the package body 20, in the present embodiment the package 2A, only the embodiment illustrated by FIG be described.

[0043] 于本实施例中,该载板20为线路板,而该些封装体为封装结构,可具有电性连接该载板20的封装基板220a,220b及设于该封装基板220a,220b上的第一与第二芯片221a, 221b,且该第一与第二芯片221a,221b可借由焊线222a或焊锡凸块222b电性连接该封装基板220a,220b,并以封装胶体223包覆该第一与第二芯片221a,221b、焊线222a与焊锡凸块222b。 [0043] In the present embodiment, the carrier plate 20 of the circuit board, and the plurality of packages to the package structure, may have electrically connected to the package substrate to the carrier plate 20 and 220a, 220b, and disposed on the package substrate 220a, 220b the first and second on-chip 221a, 221b, and the first and second chip 221a, 221b can be connected by means of a bonding wire 222a or 222b electrically the packaging substrate solder bumps 220a, 220b, and to package encapsulant 223 overlying the first and second chip 221a, 221b, 222a and solder bump bonding wire 222b. 于其它实施例中,该封装体可为半导体芯片。 In other embodiments, the package may be a semiconductor chip.

[0044] 此外,有关载板20与封装基板220a,220b的种类繁多,且为业界所熟知,所以不再赘述,特此述明。 [0044] In addition, the carrier plate 20 about the package substrate 220a, 220b are many types, and is well known in the industry, description thereof is omitted, hereby stating.

[0045] 再者,有关该封装体的内部结构因种类繁多,且为业界所熟知,所以并不限于上述,也可为其它实施例,特此述明。 [0045] Furthermore, about the internal structure of the package due to a wide range, and is well known in the industry, it is not limited to the above, other embodiments are also hereby stated.

[0046] 另外,该第一及第二封装体22a, 22b的实施例可为射屏(RF)模块,例如:无线局域网络(Wireless LAN, WLAN)、全球定位系统(Global Posit1ning System, GPS)、蓝芽(Bluetooth)或手持式视讯广播(Digital Video Broadcasting-Handheld, DVB-H)、调频(FM)等无线通讯模块。 [0046] Further, the first embodiment and the second package body 22a, 22b may be output screen (RF) module, for example: a wireless local area network (Wireless LAN, WLAN), a global positioning system (Global Posit1ning System, GPS) , Bluetooth (Bluetooth) or handheld video broadcasting (Digital Video broadcasting-handheld, DVB-H), frequency modulation (FM) wireless communication module.

[0047] 如图2B所示,设置挡架26于该第一与第二封装体22a,22b之间。 As shown in [0047] Figure 2B, the fence 26 is provided to the first and second package body 22a, between 22b.

[0048] 于本实施例中,形成该挡架26的材质为导电材,如铜、金、镍或铝等的金属,且该挡架26具有挡板260,以立设于该载板20上并位于该第一与第二封装体22a,22b之间,用以遮蔽该些封装体的侧壁,可避免该第一与第二封装体22a,22b的电磁相互干扰,使该第一与第二芯片221a,221b可保持应有的功效。 [0048] In the present embodiment, forming the fence 26 is made of a conductive material, such as copper, gold, nickel, or aluminum, and the fence 26 with baffles 260 to upright on the carrier plate 20 and located on the first and second package body 22a, 22b between, for shielding sidewalls of the package, can avoid the first and second package body 22a, 22b of the electromagnetic interference with each other, so that the first and the second chip 221a, 221b can be maintained due effect.

[0049] 如图2C所示,形成封装胶体27于该载板20上,以包覆该挡架26与该第一与第二封装体22a,22b,且令该挡架26的部分表面外露于该封装胶体27。 [0049] As shown in FIG. 2C, encapsulant 27 is formed on the carrier plate 20, the fence 26 to cover the first and second package body 22a, 22b, and enabling the fence surface 26 of the exposed portion the encapsulant 27.

[0050] 于本实施例中,以模压工艺(Inject1n Molding)形成该封装胶体27,且借由该封装胶体27可保护该些封装体避免遭受环境污染、氧化或破坏。 [0050] In the present embodiment, the molding process to (Inject1n Molding) forming the encapsulant 27, the encapsulant 27 and the plurality of packages can be protected by means avoid the risk of environmental contamination, or oxidative damage.

[0051] 此外,该封装胶体27可借由例如雷射钻孔形成开口270以外露该挡架26,如图2C所示;也可如图2C'所示,使该封装胶体27'与该挡架26的顶面齐平,以令该挡架26外露于该封装胶体27'。 [0051] In addition, the encapsulant 27 may be formed by means of laser drilling, for example, other than the opening 270 to expose the fence 26, as shown in FIG. 2C; Fig. 2C may be 'shown that the encapsulant 27' with the fence 26 flush with the top surface, in order to make the fence 26 is exposed from the encapsulant 27 '.

[0052] 如图2D所示,接续图2C的工艺,将一屏蔽组件28电性连接该挡架26。 [0052] shown in Figure 2D, the process subsequent to Figure 2C, a shield assembly 28 will be electrically connected to the fence 26.

[0053] 于本实施例中,该屏蔽组件28为利用派镀(sputtering deposit1n)的方式形成于该封装胶体27上的屏蔽层,且该部分屏蔽层形成于该开口270中以连接该挡架26的外露部分。 [0053] In the present embodiment, the shield assembly 28 is formed on the shield layer 27 on the encapsulant sent using plating (sputtering deposit1n) manner, and the portion of the shielding layer 270 is formed in the opening to connect the fence the exposed portion 26. 又形成该屏蔽组件28的材质为导电材,如金属或导电胶,但不以此为限。 And the material forming the shielding assembly 28 is a conductive material, such as metal or conductive plastic, but is not limited thereto.

[0054] 于另一实施例中,如图2D'所示,提供一金属盖作为屏蔽组件28',以盖设于该封装胶体27'上(如图中的箭头方向),并电性连接该挡架26的顶面外露部分。 [0054] In another embodiment, 'as shown, providing a metal cap as a shield assembly 28' 2D, the lid is provided to 'the encapsulant 27 (as shown by the arrow direction), and electrically connected the fence top surface 26 of the exposed portion.

[0055] 本发明的半导体封装件2,2'的制法,借由该挡架26与该屏蔽组件28,28'相互连接以形成双重屏蔽结构,使第一与第二封装体22a,22b的周围均有屏蔽结构,不仅有效防止该第一与第二封装体22a,22b之间的电磁波相互干扰,且有效防止外界电磁波干扰该第一与第二封装体22a,22b的内部电路。 [0055] The semiconductor package of the present invention, 2,2 'production method, the fence 26 by means of the shielding assembly 28, 28' are interconnected to form a double shield structure, the first and the second package body 22a, 22b around the shield structure are not only effective to prevent the first and second package body 22a, 22b interfere with each other between the electromagnetic wave, and an internal circuit to effectively prevent external electromagnetic interference of the first and second package body 22a, 22b of.

[0056] 此外,借由形成屏蔽组件28,28'于该封装胶体27,27'上,所以无需考量该载板20的线路布设,也就是该屏蔽组件28,28'不会造成短路,不仅使工艺更简易,且缩短工艺时间,因而有效降低制作成本。 [0056] Further, by forming the shielding assembly 28, 28 'formed on the encapsulant 27, 27', and there is no need to consider circuit layout of the carrier plate 20, i.e. the shielding assembly 28, 28 'will not cause a short circuit, only making the process easier, and to shorten the process time, and thus reduce production costs.

[0057] 请参阅图3A至图3B,其为本发明半导体封装件的制法的另一实施例。 [0057] Please refer to FIGS. 3A to 3B, the present invention which another semiconductor package manufacturing method of the embodiment. 本实施例与上述实施例的差异在于封装体的数量与该封装胶体的顶面高度,其它相关工艺均相同,所以不再赘述相同工艺,仅说明相异处。 The above-described embodiment in that the difference between the present embodiment, the number of package top surface height of the encapsulant, and other related processes are identical, the same process is omitted, it differs from merely illustrative.

[0058] 如图3A所示,于该载板20上设置三组封装体32a,32b, 32c,且该挡架36的挡板360依该些封装体32a,32b, 32c的位置作设计。 [0058] As shown in FIG. 3A, three sets of package body 32a on the carrier plate 20, 32b, 32c, and the fence 360 ​​of the baffle 36 for the position of the design by the plurality of packages 32a, 32b, 32c of.

[0059] 如图3B所示,形成封装胶体37于该载板20上,以包覆该挡架36与该些封装体32a, 32b, 32c,且该封装胶体37的顶面低于该挡架36的顶面,以外露该挡架36的顶面。 As shown in [0059] FIG. 3B, encapsulant 37 is formed on the carrier plate 20 to encapsulate the fence 36 with the plurality of package body 32a, 32b, 32c, and the top surface of the encapsulant 37 is below the stop the top surface of the frame 36, to expose the top surface 36 of the fence. 后续工艺请参考图2D的工艺。 Please refer to FIG. 2D subsequent processing process.

[0060] 综上所述,本发明的半导体封装件及其制法中,借由形成屏蔽组件于该封装胶体上,且借由该挡架与该屏蔽组件作为屏蔽结构,不仅防止该些封装体之间的电磁波相互干扰,且有效防止外界电磁波干扰该些封装体的内部电路。 [0060] In summary, package and method of the present invention, by means of the shield assembly is formed on the encapsulant, and by means of the fence assembly with the shield as the shield structure, only to prevent the plurality of package electromagnetic interference between the body, and prevent external electromagnetic interference the internal circuit of the plurality of packages.

[0061] 此外,借由该挡架取代镀覆工艺及屏蔽组件形成于该封装胶体上,因而无须考量该载板的线路布设,所以使本发明的工艺更简易,且可缩短工艺时间,因而有效达到降低制作成本的目的。 [0061] Further, by means of the fence-substituted plating process, and the shielding assembly is formed on the encapsulant, thus laid without consideration of the carrier circuit board, so that the process of the invention is easier, and the process time can be shortened, thus effectively achieve lower production costs.

[0062] 上述该些实施例仅例示性说明本发明的功效,而非用于限制本发明,任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述该些实施例进行修饰与改变。 [0062] Under the above-described embodiment the plurality of exemplary embodiments only illustrate the efficacy of the present invention and are not intended to limit the present invention, anyone skilled in the art may be made without departing from the spirit and scope of the invention, the plurality of embodiments described above modification and change. 此外,在上述该些实施例中的组件的数量仅为例示性说明,也非用于限制本发明。 Further, in the above embodiment the number of components in the plurality of embodiments described are exemplary only, nor intended to limit the present invention. 因此本发明的权利保护范围,应如权利要求书所列。 Thus the scope of the present invention as claimed, as listed in a claim should book.

Claims (11)

1.一种半导体封装件,包括: 载板; 多个封装体,设于该载板上; 挡架,设于该载板上,该挡架具有挡板,以立设于该载板上并位于该些封装体之间; 封装胶体,形成于该载板上,以包覆该些封装体与该挡架,并令该挡架的部分表面外露于该封装胶体;以及屏蔽组件,电性连接该挡架。 1. A semiconductor package, comprising: a carrier plate; a plurality of packages, provided on the carrier board; fence, provided on the carrier plate, the baffle having a fence to the upright on the carrier plate and located between the plurality of packages; encapsulant, formed on the carrier board, encapsulating the package body and the fence, and to make part of the surface of the fence is exposed from the encapsulant; and a shield assembly, electrical connected to the fence.
2.根据权利要求1所述的半导体封装件,其特征在于,该屏蔽组件为形成于该封装胶体上的导电层。 2. The semiconductor package according to claim 1, wherein the shielding assembly is a conductive layer formed on the encapsulant.
3.根据权利要求1所述的半导体封装件,其特征在于,该屏蔽组件为金属盖,盖设于该封装胶体上。 3. The semiconductor package according to claim 1, wherein the component is a metal shield cover that is provided on the encapsulant.
4.根据权利要求1所述的半导体封装件,其特征在于,形成该挡架的材质为导电材。 The semiconductor package of claim 1, wherein forming the fence is made of a conductive material.
5.根据权利要求1所述的半导体封装件,其特征在于,该封装体为半导体芯片或具有半导体芯片的封装结构。 5. The semiconductor package according to claim 1, characterized in that, the package having a semiconductor chip or a semiconductor chip packaging structure.
6.一种半导体封装件的制法,包括: 提供一载板; 形成多个封装体于该载板上; 设置挡架于该些封装体之间; 形成封装胶体于该载板上,以包覆该些封装体与该挡架,并令该挡架的部分表面外露于该封装胶体;以及将屏蔽组件电性连接该挡架。 A manufacturing method of a semiconductor package, comprising: providing a carrier plate; a plurality of packages are formed in the carrier plate; fence disposed between the plurality of package body; encapsulant is formed on the carrier plate, in order to encapsulating the package body and the fence, and to make part of the surface of the fence is exposed from the encapsulant; and shield assembly electrically connected to the fence.
7.根据权利要求6所述的半导体封装件的制法,其特征在于,该屏蔽组件为以溅镀方式形成于该封装胶体上的导电层。 Method according to claim 6 of the semiconductor package as claimed in claim, wherein the shield assembly is formed by sputtering on the conductive layer on the encapsulant.
8.根据权利要求6所述的半导体封装件的制法,其特征在于,该屏蔽组件为金属盖,以盖设于该封装胶体上。 Method according to claim 6, said semiconductor package, wherein the component is a metal shield cover to cover disposed on the encapsulant.
9.根据权利要求6所述的半导体封装件的制法,其特征在于,该挡架具有挡板,以立设于该载板上并位于各该封装体之间。 Method according to claim 6, said semiconductor package, characterized in that the fence has a shutter, a standing plate disposed in the carrier and located between each of the package.
10.根据权利要求6所述的半导体封装件的制法,其特征在于,形成该挡架的材质为导电材。 10. The production method of claim 6 of the semiconductor package of claim, wherein forming the fence is made of a conductive material.
11.根据权利要求6所述的半导体封装件的制法,其特征在于,该封装体为半导体芯片或具有半导体芯片的封装结构。 Method according to claim 6, said semiconductor package, wherein the package having a semiconductor chip or a semiconductor chip packaging structure.
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