JPH04245433A - Simulation method of etching process - Google Patents

Simulation method of etching process

Info

Publication number
JPH04245433A
JPH04245433A JP1043391A JP1043391A JPH04245433A JP H04245433 A JPH04245433 A JP H04245433A JP 1043391 A JP1043391 A JP 1043391A JP 1043391 A JP1043391 A JP 1043391A JP H04245433 A JPH04245433 A JP H04245433A
Authority
JP
Japan
Prior art keywords
etching
substance
point
intersection
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1043391A
Other languages
Japanese (ja)
Inventor
Hidetaka Ikeuchi
池内 英貴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1043391A priority Critical patent/JPH04245433A/en
Publication of JPH04245433A publication Critical patent/JPH04245433A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To simulate the etching operation of many layers by a method wherein an etching rate for other substances, to be etched, which have been exposed by deleting a point train is applied to the substances and a point train is moved by an etching rate which is peculiar to each substance. CONSTITUTION:An oxide film 2 is formed on a silicon substrate 1; a nitride film 3 is formed on the oxide film 2. When a developed resist 4 exists on its upper part, a point train 5 is formed around each substance. An etching operation is made to progress clockwise; the intersection P of a point train is detected at each time step. At a stage where the intersection of the point train 5 has been detected, the point train is cut into pieces; a substance to be etched on the lower layer is exposed. Regarding a face (a flag is given as a candidate of a point to be moved to a point train included in the face) which comes into contact with an etching substance, an etching operation is continued at an etching rate which is decided by each substance to be etched and the etching substance.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、多層エッチング工程に
おけるプロセスシミュレーション方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process simulation method in a multilayer etching process.

【0002】0002

【従来の技術】従来のエッチングシミュレーション方法
としては、単層のエッチングシミュレーションのみを行
なっていた。これは、例えば「プロシーディング・オブ
・ザ・アイイイイ(PROCEEDINGS  OF 
 THE  IEEE)」Vol.71,No.I,J
anuary,1983に記載の論文「アイシー・プロ
セス・モデリング・アンド・トポグラフィ・デサイン(
IC  Process  Modeling  an
d  Topography  Design)」に示
されている。このエッチングシミュレーションの方法は
、図4に示す様にシリコン基板1の上に被エッチング物
質として酸化膜2,窒化膜3,レジスト4をのせ、エッ
チング物質〔イオン沸酸等〕に接している領域に点列5
を設ける。この点列5は、図5(a)に示すように、三
つの点列5の間の二等分角Bより求まるエッチング方向
Aとエッチング時間とエッチング速度の積より求まるエ
ッチング距離を各点毎に求め、各点をその方向にエッチ
ング距離のみ移動させて新たな点列5を求めていた。
2. Description of the Related Art In the conventional etching simulation method, only a single layer etching simulation was performed. This is, for example, ``PROCEEDINGS OF
THE IEEE)” Vol. 71, No. I, J
Annual, 1983, the paper “Icy Process Modeling and Topography Design”
IC Process Modeling an
d Topography Design). In this etching simulation method, as shown in FIG. 4, an oxide film 2, a nitride film 3, and a resist 4 are placed on a silicon substrate 1 as the materials to be etched, and the regions in contact with the etching material (ionic hydrochloric acid, etc.) are Point sequence 5
will be established. As shown in FIG. 5(a), this point sequence 5 calculates the etching distance obtained from the product of the etching direction A obtained from the bisector angle B between the three point sequences 5, the etching time, and the etching rate for each point. A new point sequence 5 is obtained by moving each point by the etching distance in that direction.

【0003】この場合のフローチャートは、図6に示さ
れる。まず、ステップ11aでエッチング物質に接して
いる領域を、図5(b)のように右廻りで点列5(1,
2,…,i,N)で囲む。次にステップ12で露出して
いる点列5をベクトルVi とエッチング時間Δtとの
積であるベクトルRiだけ移動させる。さらに、この点
列がステップ21で他の被エッチング物質に入ったか否
かを判定し、これが入った場合にはステップ22で他の
エッチング物質に入った点列5を削除する。そしてステ
ップ18でエッチング時間の終了までこの作業をつづけ
る。
A flowchart in this case is shown in FIG. First, in step 11a, the area in contact with the etching substance is rotated clockwise as shown in FIG.
2,...,i,N). Next, in step 12, the exposed point sequence 5 is moved by a vector Ri, which is the product of the vector Vi and the etching time Δt. Furthermore, it is determined in step 21 whether or not this dot sequence has entered another etching target material, and if so, the dot sequence 5 that has entered another etching material is deleted in step 22. This operation is continued until the end of the etching time in step 18.

【0004】0004

【発明が解決しようとする課題】上述した従来のエッチ
ングシミュレーション方法では、単層のエッチングシミ
ュレーションしか行うことができず、そのエッチングシ
ミュレーション方法は単一の被エッチング物質を貫通し
、他の被エッチング物質あるいはシリコン基板に到達し
ても、異物質であることが判別できなかった。そのため
多層のエッチングシミュレーションを行なおうとすると
、同じエッチングレートでエッチングを続行してしまう
欠点がある。
[Problems to be Solved by the Invention] The conventional etching simulation method described above can only perform etching simulation of a single layer. Or even if it reached the silicon substrate, it could not be determined that it was a foreign substance. Therefore, when attempting to perform a multilayer etching simulation, there is a drawback that etching continues at the same etching rate.

【0005】本発明の目的は、このような問題を解決し
、多層のエッチングシミュレーションを行うことができ
るエッチングプロセスのシミュレーション方法を提供す
ることにある。
An object of the present invention is to provide an etching process simulation method that can solve these problems and perform multilayer etching simulation.

【0006】[0006]

【課題を解決するための手段】本発明のエッチングシミ
ュレーション方法の構成は、全ての被エッチング物質の
各々の周囲に点列を与えその被エッチング物質上部より
エッチングしていく段階で、隣接する他の被エッチング
物質にエッチングが到達したか否かを逐次、点列の交差
を検出することにより判断し、その交差した点列は削除
し、それ迄一連続であった点列を分断し複数の点列とし
、前記点列の削除によって露出した他の被エッチング物
質にはその物質のエッチングレートを適用して各物質固
有のエッチングレートにより点列を移動させるようにし
たことを特徴とする。
[Means for Solving the Problems] The structure of the etching simulation method of the present invention is such that in the step of providing a dot array around each of all the materials to be etched and etching from the top of the material to be etched, It is determined whether the etching has reached the material to be etched by sequentially detecting the intersections of the dot rows, the intersecting dot rows are deleted, and the previously continuous dot row is divided into multiple points. The method is characterized in that the etching rate of the substance exposed by the deletion of the dot sequence is applied to other substances to be etched, and the dot sequence is moved according to the etching rate unique to each substance.

【0007】[0007]

【実施例】図1は本発明の一実施例を説明するフローチ
ャートである。まず、ステップ11に示すように同一物
質層をそれぞれ右回りの点列で囲む。このうち露出して
いる点列について、ステップ12のように、図5(a)
と同様にしてエッチング方向Aに、エッチング時間Δt
とエッチング速度のベクトルVi との積より求まるエ
ッチング距離のベクトルRiを各点毎に求め(図2(a
))、各点を移動していく。このときステップ13,1
4で点列5のなす線分が交差しているか否かを判定し、
交差しているならば(ステップ15)、ステップ16で
その部分を分断して1つの点列とし、また、ステップ1
7で新たに発生した点列のうち左回りになっているもの
を削除する(図2(b)参照)。この結果他の層に影響
する部分の点列を除き、エッチングを続行することがで
きる。以上の工程をエッチング時間が終了するまで繰返
し行う(ステップ18)。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flowchart illustrating an embodiment of the present invention. First, as shown in step 11, each of the same material layers is surrounded by a clockwise series of points. For the exposed point sequence, as in step 12, as shown in FIG. 5(a)
Similarly, in the etching direction A, the etching time Δt
The vector Ri of the etching distance, which is found by the product of the vector Vi of the etching speed
)), move each point. At this time, step 13,1
4, determine whether the line segments formed by the point sequence 5 intersect,
If they intersect (step 15), then in step 16 that part is divided into one point sequence, and in step 1
7, among the newly generated point sequences, those that are counterclockwise are deleted (see FIG. 2(b)). As a result, etching can be continued except for the dot rows that affect other layers. The above steps are repeated until the etching time ends (step 18).

【0008】図3(a)〜(d)は本実施例を説明する
断面図である。まず、図3(a)に示す様に、シリコン
基板1の上に酸化膜(SiO2 )2を設置し、この酸
化膜2の上に窒化膜(Si3 N4 )3を設置し、そ
の上部に現像されたレジスト4がある場合を想定する。 次に図3(b)に示すように、各物質の周囲に点列5を
設ける。第5図に示す方法と同一の方法でエッチングを
進行させ各タイムステップΔt毎に点列の交差Pを検出
する。
FIGS. 3(a) to 3(d) are cross-sectional views for explaining this embodiment. First, as shown in FIG. 3(a), an oxide film (SiO2) 2 is placed on a silicon substrate 1, a nitride film (Si3N4) 3 is placed on this oxide film 2, and a developed film is placed on top of the nitride film (Si3N4). Assume that there is a resist 4 that is Next, as shown in FIG. 3(b), a dot array 5 is provided around each substance. Etching is performed in the same manner as shown in FIG. 5, and the intersection P of the dot sequence is detected at each time step Δt.

【0009】点列5の交差Pが検出された段階で、その
点列を分断させ、図3(c)に示す様に、下層の被エッ
チング物質を露出させ、図3(d)に示す様に、エッチ
ング物質に接触している面(この面に含まれる点列には
移動する点の候補としてフラグを与えておく)について
、各被エッチング物質とエッチング物質とから定まるエ
ッチングレートでエッチングを続行していく。以下、図
1に示したフローでエッチングを行なうことで、実際の
エッチングと同様な多層シミュレーションを実行するこ
とが可能となる。
When the intersection P of the dot array 5 is detected, the dot array is divided to expose the underlying material to be etched as shown in FIG. 3(c), and the etched material is etched as shown in FIG. Then, continue etching on the surface that is in contact with the etching material (a flag is given to the series of points included in this surface as candidates for moving points) at the etching rate determined by each etching material and the etching material. I will do it. Thereafter, by performing etching according to the flow shown in FIG. 1, it becomes possible to perform a multilayer simulation similar to actual etching.

【0010】0010

【発明の効果】以上説明したように本発明は、多層のエ
ッチングシミュレーションを行うことができるので、実
際に集積回路の微細加工をする状態と同一の設定をする
ことにより、最適なエッチング時間,エッチング物質の
選択を事前に決定することができるという効果がある。
[Effects of the Invention] As explained above, the present invention can perform multilayer etching simulation, so by setting the same settings as those used for actual microfabrication of integrated circuits, it is possible to optimize the etching time and etching process. This has the effect of allowing the selection of materials to be determined in advance.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例のエッチングシミュレーショ
ン工程を示すフローチャート、
FIG. 1 is a flowchart showing an etching simulation process according to an embodiment of the present invention;

【図2】(a),(b)は本実施例の工程における交点
Pの座標図および点列の削除を説明する模式的断面図、
FIGS. 2(a) and 2(b) are a coordinate diagram of an intersection point P and a schematic cross-sectional view illustrating the deletion of a point sequence in the process of this example;

【図3】(a)〜(d)は本実施例をエッチング工程順
に示す断面図、
FIGS. 3(a) to 3(d) are cross-sectional views showing this example in the order of etching steps;

【図4】従来のエッチングシミュレーション工程を示す
断面図、
FIG. 4 is a cross-sectional view showing a conventional etching simulation process;

【図5】図4のエッチングの方向を説明する座標図およ
びエッチング領域の模式図、
FIG. 5 is a coordinate diagram illustrating the direction of etching in FIG. 4 and a schematic diagram of an etching region;

【図6】従来のエッチングシミュレーション工程のフロ
ーチャート、
[Fig. 6] Flowchart of conventional etching simulation process,

【符号の説明】[Explanation of symbols]

1    シリコン基板 2    酸化膜 3    窒化膜 4    レジスト 5    点列 A    エッチング方向 B    二等分角 1 Silicon substrate 2 Oxide film 3 Nitride film 4 Resist 5 point sequence A Etching direction B Bisector angle

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  全ての被エッチング物質の各々の周囲
に点列を与えその被エッチング物質上部よりエッチング
していく段階で、隣接する他の被エッチング物質にエッ
チングが到達したか否かを逐次、点列の交差を検出する
ことにより判断し、その交差した点列は削除し、それ迄
一連続であった点列を分断し複数の点列とし、前記点列
の削除によって露出した他の被エッチング物質にはその
物質のエッチングレートを適用して各物質固有のエッチ
ングレートにより点列を移動させるようにしたことを特
徴とするエッチングプロセスのシミュレーション方法。
[Claim 1] In the step of providing a dot array around each of all the etching target materials and etching from the top of the etching target materials, it is sequentially determined whether or not the etching has reached other adjacent etching target materials. The judgment is made by detecting the intersection of point sequences, the intersecting point sequence is deleted, the previously continuous point sequence is divided into multiple point sequences, and other objects exposed by the deletion of the point sequence are A method for simulating an etching process, characterized in that an etching rate of the material is applied to the etching material, and a series of dots is moved according to the etching rate unique to each material.
【請求項2】  点列の交差は、点と点との間の一つの
線分を表現する直線式が、他の一線分を表現する直線式
との交点がどちらの線分上にあるかで判定する請求項1
記載のエッチングプロセスのシミュレーション方法。
[Claim 2] Intersection of a series of points is the intersection of a linear equation expressing one line segment between points with a linear equation expressing another line segment on which line segment. Claim 1 determined by
A simulation method of the described etching process.
JP1043391A 1991-01-31 1991-01-31 Simulation method of etching process Pending JPH04245433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1043391A JPH04245433A (en) 1991-01-31 1991-01-31 Simulation method of etching process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1043391A JPH04245433A (en) 1991-01-31 1991-01-31 Simulation method of etching process

Publications (1)

Publication Number Publication Date
JPH04245433A true JPH04245433A (en) 1992-09-02

Family

ID=11750025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1043391A Pending JPH04245433A (en) 1991-01-31 1991-01-31 Simulation method of etching process

Country Status (1)

Country Link
JP (1) JPH04245433A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9020210B2 (en) 2009-11-11 2015-04-28 Sony Corporation Image processing system, image processing apparatus, image processing method, and program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9020210B2 (en) 2009-11-11 2015-04-28 Sony Corporation Image processing system, image processing apparatus, image processing method, and program
US9547791B2 (en) 2009-11-11 2017-01-17 Sony Corporation Image processing system, image processing apparatus, image processing method, and program

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