JPH04243378A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To separate a synchronizing signal accurately without being affected by noise from a video signal with a deteriorated S/N by detecting a pedestal level and a SYNC chip level so as to calculate an intermediate level between both levels before passing through an LPF and setting the level as a threshold level. CONSTITUTION:A video signal inputted from an input terminal 2 is inputted to a comparator 3, a pedestal level detection circuit 4 and a SYNC chip level detection circuit 5 via an LPF 1. The circuits 4, 5 detect respectively a pedestal level and a SYNC chip level and inputs it to a threshold level setting circuit 6, in which a voltage level at an intermediate point of both levels is set as a threshold level. The threshold voltage is inputted to the comparator 3 as a comparison reference voltage and a signal corresponding to a period when the video signal is lower than the reference voltage is outputted to an output terminal 7 as a synchronizing signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous separation circuit built into a TV receiver or the like.

0002

[Prior Art] EDTV (Extended Difi)
In digital television receivers that have improved image quality, such as home-use VTRs,
In order to deal with signals containing jitter, such as the above, a clock synchronized with the horizontal synchronization signal is generated, and the signal is processed based on this clock. therefore,
In EDTV and the like, performance is greatly affected by how accurately the horizontal synchronization signal can be separated from the video signal.

[0003] The above-mentioned separation of synchronization signals is conventionally performed through a comparator 21, as shown in FIG. An input video signal is input to this comparator 21 through a video input terminal 22, and a threshold input terminal 2
3 is supplied with a threshold voltage fixed at a predetermined voltage value. As shown in FIG. 5(a), this threshold voltage is approximately halfway between the pedestal level P of the input video signal and the lowest sync tip level S' in the synchronization signal part Sh having a square wave shape. corresponding to the input period of the video signal that is lower than this threshold level.
The output synchronization signal shown in FIG. 4B is outputted through the synchronization signal output terminal 24 in FIG.

0004

[Problems to be Solved by the Invention] However, the S/N ratio of output signals from household VTRs, etc. is poor, and the conventional synchronization separation method described above is not suitable for TVs with advanced image quality such as EDTV.
In V, a problem arises in that synchronization separation characteristics sufficient to fully demonstrate its performance cannot be obtained. In other words, as shown in FIG. 6, the S/N of the video signal is poor and the sync signal part
If high-frequency noise is also superimposed on h, as shown in FIG. 7, the timing of slicing at the threshold value will shift due to the influence of the noise. For this reason, it is no longer possible to separate a synchronization signal that accurately corresponds to the synchronization signal section Sh.

On the other hand, in order to deal with the above-mentioned problems, it is conceivable to provide a low-pass filter (LPF) 32 before the comparator 31, as shown in FIG. However, with such a low-pass filter 32, noise is removed from a signal superimposed with high frequency noise as shown in FIG. 9, and at the same time, as shown in FIG. Distortion occurs in the waveform itself of the signal portion Sh. Conventionally, for waveforms with such distortion, it is not possible to set a threshold that accurately corresponds to the falling and rising edges of the original synchronizing signal section Sh. Separation has become impossible.

The present invention was devised in view of the above-mentioned conventional problems, and its purpose is to provide a synchronization signal that is compatible with input signals having a poor S/N ratio, such as the output from a home VTR. An object of the present invention is to provide a synchronization separation circuit capable of accurately extracting the synchronization timing of.

[0007]

[Means for Solving the Problems] Therefore, the synchronous separation circuit of the present invention generates a signal corresponding to the period between each intersection point where the falling and rising edges of an input signal forming a substantially square wave intersect a threshold level. In the synchronization separation circuit provided with the output comparator, a low-pass filter is provided on the input line to the comparator, and the pedestal level and sync tip level of the input signal after passing through this low-pass filter are respectively detected. a pedestal level detection means and a sync tip level detection means, and an arithmetic expression for calculating a substantially intermediate level between the pedestal level and the sync tip level of the input signal before passing through the low-pass filter from each detection level of both the detection means; The present invention is characterized in that it is provided with threshold setting means for performing calculation based on the calculation result and setting the calculation result as the threshold level of the comparator.

[0008]

[Operation] According to the above structure, an input signal having a substantially square wave is first passed through a low-pass filter and input to the comparator. Therefore, noise components are removed when the signal passes through the low-pass filter, and harmonic components are removed from the input signal, resulting in a distorted waveform that is input to the comparator. However, in the above configuration, from the pedestal level and the sync tip level in the waveform that has caused this distortion, the calculation is performed to obtain a substantially intermediate level between the pedestal level and the sync tip level of the input signal before passing through the low-pass filter. The formula is set in the threshold setting circuit.

In other words, if the series of synchronization signal parts in the input signal is regarded as a periodic function of a square wave that can be expanded into a Fourier series, the waveform from which harmonic components have been removed after passing through the low-pass filter is the part of the Fourier series. It corresponds to the sum function. Therefore, due to the nature of the partial sum function near the discontinuity point in the Fourier series, the waveform after passing through the low-pass filter also passes through each intermediate point between the falling and rising edges of the original sync signal section before passing, and , a predetermined relationship is maintained in the difference between the pedestal level and the sync tip level before and after passing through the low-pass filter. Based on this relationship, the threshold value for slicing the waveform after passing through the low-pass filter is set at timings that approximately match the falling and rising points of the synchronization signal before passing through the low-pass filter. It is possible to set an arithmetic expression to calculate from the pedestal level and the sync tip level in the waveform after passing through the low-pass filter.

Calculations based on the arithmetic expressions thus set are automatically performed in the threshold setting circuit, and the thresholds are set in the comparator based on the results. Even when a video signal with a poor /N ratio is input, it is possible to accurately separate the synchronization signal without being affected by noise.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

As shown in FIG. 1, the synchronization separation circuit of this embodiment is provided with a low-pass filter (LPF) 1, and a video signal is input to the low-pass filter 1 through a video signal input terminal 2. Ru. The low-pass filter 1 removes high-frequency noise in the video signal input thereto, and also applies band limitation to the video signal itself so that its high-frequency components are removed. The output signal from this low-pass filter 1 is input to a comparator 3, and is further input to a pedestal level detection circuit (pedestal level detection means) 4 and a sync tip level detection circuit (sync tip level detection means) 5. be done.

The pedestal level detection circuit 4 detects the pedestal level in the video signal waveform after passing through the low-pass filter 1, while the sync chip level detection circuit 5 detects the pedestal level in the sync signal portion of the video signal waveform. Sync tip level detection is performed. The pedestal level and sync tip level respectively detected by these circuits 4 and 5 are input to a threshold setting circuit (threshold setting means) 6, and in this circuit 6, calculation is performed based on the calculation formula described later. was carried out,
A threshold voltage is generated. This threshold voltage is input to the comparator 3 as a comparison reference voltage. In this comparator 3, the low pass filter 1
A period in which the voltage level is lower than the above-mentioned threshold voltage is extracted from the video signal inputted from the video signal, and a signal corresponding to this period is outputted to the synchronization signal output terminal 7 as a synchronization signal.

Next, the arithmetic expression set in the threshold setting circuit 6 will be explained.

[0015] This arithmetic expression is obtained by applying the properties of the Fourier series. In other words, as shown in FIG. 2, if the waveform signal in which the synchronization signal parts 8 in the video signal are connected is regarded as a periodic function of a square wave and is denoted as F(t), then this F(t
) can be expanded into a Fourier series, and its formula becomes. Here, in equation (1), when the value of k is truncated at a certain finite value N, the Fourier series has the following properties near the discontinuity point.

(A) At a discontinuous point, the Fourier series converges to the average value of the signal values on both sides. (B) The partial sum of the Fourier series shows a ripple shape,
The peak value of the ripple amplitude does not decrease with increasing N, and its magnitude is 18% of the height of the discontinuity (
Gibbs phenomenon).

On the other hand, in the synchronization separation circuit of this embodiment, noise components are removed by passing the video signal through the low-pass filter 1, but at the same time, harmonic components are removed from the input video signal. The resulting waveform is output. This is expressed as a partial sum function obtained by truncating the value of k at a certain finite value in Equation (1) above. Therefore, the waveform after passing through the first low-pass filter is:
It has the properties (A) and (B) above.

That is, as shown in FIG. 3, the signal 11 that has passed through the low-pass filter 1 has a square wave shape before passing through the low-pass filter 1 by removing harmonic components as described above. Although the waveform is distorted compared to the original synchronization signal section 10, due to the property (A) above, the intermediate points C and C of the falling and rising points, which are discontinuous points in the original synchronization signal section 10, are The waveform will pass through each of them. Therefore, the voltage level at these intermediate points C and C is set as the threshold value X, and the signal 1 after passing through the low-pass filter 1
By outputting a signal corresponding to the period between each intersection C and C where the falling and rising edges of 1 intersect with the threshold value X, the waveform after passing through the low-pass filter 1 can be Even in this case, it is possible to obtain a synchronization signal that accurately corresponds to the falling and rising edges of the original synchronization signal section 10.

According to the property (B), the above threshold value X is determined by the signal 11 after passing through the low-pass filter 1.
From this, it can be determined by the following calculation. That is, if the pedestal level in the signal 11 after passing through the low-pass filter 1 is P, the sync tip level is S, and the sync tip level in the original synchronization signal section 10 is S', then X=(P+S')/2. Since the relationship P-S=1.18(P-S') holds, the above threshold value X is
1.36P+S)/2.36...calculated using equation (2).

Therefore, the calculation based on the above equation (2) is performed in the threshold setting circuit 6, a voltage obtained from the calculation result is generated, and this is inputted to the comparator 3 as the threshold value X. As a result, comparator 3
From then on, based on the threshold value X, a synchronization signal that more accurately matches the timing of the falling and rising edges of the original synchronization signal section 10 is output to the synchronization signal output terminal 7.

As described above, in the above embodiment, the pedestal level P and the sync tip level S are detected for the signal which has passed through the low-pass filter 1, noise has been removed, and the waveform has been distorted. , both detection levels P and S
Therefore, the comparator 3 outputs a synchronization signal that more accurately matches the falling and rising edges of the original synchronization signal section 10 before passing through the low-pass filter 1. In other words,
Since the relationship based on the above properties (A) and (B) is maintained between the original synchronization signal part 10 and the waveform of the signal 11 after passing through the low-pass filter 1, the waveform of the signal 11 after passing through the low-pass filter 1 is maintained. By simple calculation based on the pedestal level P and the sync tip level S in the signal 11, a synchronization signal that accurately corresponds to the original synchronization signal section 10 is output without being affected by noise. As a result, for example, ED
By incorporating the above-mentioned synchronization separation circuit into TVs, which have advanced in image quality, S/
Accurate synchronization separation is performed even when a video signal with poor N is input, thereby making it possible to fully demonstrate the original performance of EDTV and obtain a good high-quality image.

[0022]

As described above, the synchronization separation circuit of the present invention includes a low-pass filter interposed in the input line to the comparator, and a pedestal level and sync chip of the input signal after passing through the low-pass filter. A pedestal level detection means and a sync tip level detection means each detect the level, and from each detection level of both detection means, approximately the intermediate level between the pedestal level and the sync tip level of the input signal before passing through the low-pass filter. This configuration includes threshold setting means for performing calculations based on arithmetic expressions for determining , and setting the calculation results as the threshold level of the comparator.

[0023] As a result, the signal after passing through the low-pass filter, in which noise has been removed and the waveform has been distorted, almost matches the falling and rising points of the synchronization signal section before passing through the low-pass filter. At this timing, a threshold value for slicing the waveform after passing through the low-pass filter is automatically set. As a result, even when a video signal with a poor S/N ratio is input, such as in a home VTR, it is possible to accurately separate the synchronization signal without being affected by noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a synchronization separation circuit in an embodiment of the present invention.

FIG. 2 is a schematic diagram of a waveform in which synchronization signal parts in a video signal are connected.

FIG. 3 is a schematic diagram showing a signal waveform after passing through a low-pass filter using a solid line to explain a threshold value set in a comparator in the synchronization separation circuit.

FIG. 4 is a block diagram showing the configuration of a conventional synchronous separation circuit.

FIG. 5 is a timing chart showing the relationship between the input video signal to the synchronization separation circuit and the synchronization signal separated from this signal.

FIG. 6 is an enlarged view of a synchronization signal portion in the input video signal.

7 is an enlarged schematic diagram of section D in FIG. 6. FIG.

FIG. 8 is a block diagram showing the configuration of another conventional synchronous separation circuit.

FIG. 9 is an enlarged view of a synchronization signal portion of an input signal to the synchronization separation circuit.

FIG. 10 is a schematic diagram of a waveform after passing through a low-pass filter in the synchronization separation circuit.

[Explanation of symbols]

1 Low-pass filter 3 Comparator 4 Pedestal level detection circuit (pedestal level detection means) 5 Sync tip level detection circuit (sync tip level detection means)

Claims (1)

[Claims] 1. A synchronization separation circuit provided with a comparator that outputs a signal corresponding to a period between each crossing point where a falling edge and a rising edge of an input signal forming a substantially square wave intersect a threshold level, respectively. a low-pass filter interposed in the input line to the comparator; a pedestal level detection means and a sync-tip level detection means for respectively detecting the pedestal level and sync-tip level of the input signal after passing through the low-pass filter; From each detection level of the detection means, a calculation is performed based on a calculation formula to obtain a substantially intermediate level between the pedestal level and the sync tip level of the input signal before passing through the low-pass filter,
A synchronous separation circuit comprising threshold setting means for setting the calculation result as a threshold level of the comparator.