JPH04242351A - Error pulse generating circuit - Google Patents

Abstract

PURPOSE:To generate an error pulse from an optional time slot in a frame format of a signal string by using a timing signal having no correlation with the signal string as a trigger. CONSTITUTION:A switch signal 80 sent via a switch 10 is converted into a trigger pulse 90 by a pulse conversion circuit 20, a data burst position signal 100 specifying a time slot at which an error pulse is to be generated is converted into an error bit location signal 110 at a pulse width conversion circuit 30 and enters respectively an output control signal generating circuit 40. The output control signal generating circuit 40 uses an output control signal 120 to control an output control circuit 50 to output an error bit location signal 110 just after the trigger pulse 90 as an error pulse 130.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error pulse generation circuit used in an error insertion circuit for burst-like data strings in digital data communications.

0002

[Prior Art] In a digital signal transmission system,
When installing a line, it is necessary to install communication equipment and test whether the line is connected properly after all transmission lines are connected. In addition, when performing line expansion work or disaster recovery work, it is necessary to similarly test whether the line is connected normally.

[0003] In order to check whether a line is operating normally, a method is often used in which a test signal is sent out and each receiving point determines whether the test signal is being transmitted normally. For example, in the case of a voice telephone line, if two terminals on opposite sides talk to each other using telephones, it can be determined whether the voice line is operating normally. In a digital signal transmission system, if the voice signal is digitized, it is possible to make a call using a telephone, but since the signal to be transmitted is digital, it is necessary to test whether the data is being transmitted normally in 1-bit units. Since it is completely unsuitable for detecting bit-by-bit error bits, it is necessary to test using a digital signal train as the test signal. Since the digital signal train used must determine the success or failure of the test signal at the receiving point alone, a signal train with a certain predetermined rule is sent out, and the receiving point inspects the received signal according to this rule. It is determined on a bit-by-bit basis whether the digital signal string is being transmitted normally.

[0004] In a digital signal transmission system, whether or not a digital signal train is being transmitted normally is determined bit by bit.If the error bit detection circuit or error display function at the receiving point fails, the error bit detection Even if there are error bits in the signal string, the line appears to be operating normally, which may make it impossible to determine whether there is a line failure at all.

[0005] In order to determine whether this error cannot be detected, it is sufficient to send an error bit to the signal train in a pseudo manner and test whether the error bit can be accurately detected at the receiving point. In order to do this, an error bit insertion circuit is built into the line test equipment, and a test is performed to send out error bits when the line is installed. This test verifies that the line is operating normally and that the error detection and display circuits are free from abnormalities. can.

[0006]

As described above, signal transmission tests on lines are performed by inserting error bits, but for this purpose a circuit for inserting error bits is required. Conventionally, a circuit that periodically generates error bits using a timer circuit or the like has been used, but because it is cyclical, it is not possible to insert errors at arbitrary timing.

Furthermore, in today's digital data communications, a large number of data channels are multiplexed using a time division multiplex communication system, and the channels applicable to the test are arranged in a burst pattern in the signal frame format. Therefore, when error bits are generated randomly, the error bits are not necessarily multiplexed onto the corresponding channel. If error bits are inserted randomly, channels other than the burst applicable to the test may already be in operation, so there is a possibility that errors will be sent to the lines that are in operation. If there is a circuit that generates error bits in any time slot in the signal frame format, error bits can be inserted freely.

[0008] To generate error bits arbitrarily, it is possible to use a push button switch or the like, and if an error pulse can be generated each time the switch is pressed, an error can be freely inserted at an arbitrary timing. However, since mechanical contacts such as switches cause chattering, there is a problem that the switch contacts cannot be used as error bit insertion signals as they are, and the operation from pressing to releasing is always one error insertion signal. A circuit is required to convert it into operation. Furthermore, since there is no correlation between the timing of pressing the pushbutton switch and the timing of the data in the digital data, it is necessary to convert the timing of the pushbutton switch into the timing of the data in the digital data.

[0009] Because of the above-mentioned problems, there has been no error pulse generation circuit that can artificially insert error bits into arbitrary time slots in a signal frame format.

0010

[Means for Solving the Problems] The error pulse generation circuit of the present invention includes a switch having a mechanical contact that may include chattering, and a signal generated by the switch that
and a second means for outputting a second pulse at a time slot position specified by inputting a signal specifying the position of an arbitrary time slot in the frame format of the digital data signal. and a third means for outputting a control signal from a first time when the first pulse is input to a second time when the second pulse that is first input after the first time disappears. means and
and fourth means for outputting the second pulse as an error pulse when the control signal is input.

[0011] The switch may be a push button switch.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Further, FIG. 2 is a time chart for explaining the operation of this embodiment, and 60 in the figure represents an example of a signal frame format in digital data communication. A large number of data channels 1 to n are accommodated in the signal frame format 60 using a time division multiplexing method. For example, when focusing on an arbitrary data channel 1, data channel 1 is stored in the signal frame format 60 as a burst like a burst 70. It is multiplexed and transmitted.

Next, the configuration of the embodiment shown in FIG. 1 will be explained. First, a push button type 1 circuit 2 contact switch 10
When the switch is on, it is high level, and when it is off, it is low level. It remains on only while the switch 10 is pressed. The signal when the switch 10 is pressed is the switch signal 80, and to explain the waveform shown in the time chart of FIG. There is. In order to avoid malfunctions due to this chattering and the influence of variations in the time from when the switch 10 is pressed to when it is released, the previous switch signal 80 is input to the pulse conversion circuit 20. The pulse conversion circuit 20 converts the switch signal 80 into a trigger pulse 90 and outputs it, and this trigger pulse 90 serves as a trigger for outputting an error pulse.

[0015] Furthermore, in order to specify the time slot in which error bits are multiplexed, the signal frame format 60
A data burst position signal 100 indicating the position of the data burst in the data burst is input to the pulse width conversion circuit 30, and the pulse width conversion circuit 30 outputs an error bit position signal 110 indicating the position at which error bits are multiplexed.

The trigger pulse 90 and error bit position signal 110 are input to an output control signal generation circuit 40, which outputs an output control signal 120. The output control signal 120 is in an on state and at a high level when output is permitted, and is in an off state and at a low level when output is not permitted.

The output control signal 120 and error bit position signal 110 are input to an output control circuit 50, and an error pulse 130 for error bit multiplexing is output.

The operation of this embodiment having the above configuration will be explained. In a normal state, since errors are not multiplexed, the output control signal 120 is in an OFF state. Here, the switch 10 is pressed to request multiplexing of error pulses, and the trigger pulse 90 is generated from the pulse conversion circuit 20 and inputted to the output control signal generation circuit 40. Immediately after the trigger pulse 90 is input to the output control signal generation circuit 40, the output control signal 1 is generated.
20 is in the on state.

When the output control signal 120 is turned on, the output control circuit 50 outputs the error bit position signal 110 as it is as an error pulse 130. Further, when the output control signal generation circuit 40 receives the error bit position signal 110 while the output control signal 120 is in the on state,
Immediately after the error bit position signal 110 passes, the output control signal 120 is turned off, and the output control circuit 50 no longer outputs the error pulse 130. That is, after the output control signal 120 turns on, the first error bit position signal 110 is output as an error pulse 130 through the output control circuit 50, and the output control signal 120 is turned off by this first error bit position signal 110. Therefore, the error bit position signal 110 after this point is no longer output from the output control circuit 50 as the error pulse 130.

As explained above, the push button switch 1
By operating 0 and inputting the trigger pulse 90,
The error pulse 130 can be output at any timing specified by the data burst position signal 100.

[0021]

Effects of the Invention As explained above, the present invention enables a specified arbitrary time slot in a signal frame format to be used every time a switch having a mechanical contact point where chattering is unavoidable, such as a push button switch, is operated. This has the effect of providing an error pulse generation circuit that generates error pulses.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG. 1;

[Explanation of symbols]

10 Switch 20 Pulse conversion circuit 30 Pulse width conversion circuit 40 Output control signal generation circuit 50 Output control circuit

Claims (2)

[Claims] 1. A switch having mechanical contacts that may include chattering; first means for converting a signal generated by the switch into a first pulse; and an arbitrary time slot in a frame format of a digital data signal. a second means for outputting a second pulse at a time slot position specified by inputting a signal specifying a position of the time slot; and a third means for outputting a control signal until a second time when the second pulse input first disappears after that, and outputting the second pulse as an error pulse when the control signal is input. An error pulse generation circuit characterized by comprising a fourth means. 2. The error pulse generating circuit according to claim 1, wherein the switch is a push button switch.