JPH04242307A - Amplifier circuit - Google Patents

Amplifier circuit

Info

Publication number
JPH04242307A
JPH04242307A JP3003578A JP357891A JPH04242307A JP H04242307 A JPH04242307 A JP H04242307A JP 3003578 A JP3003578 A JP 3003578A JP 357891 A JP357891 A JP 357891A JP H04242307 A JPH04242307 A JP H04242307A
Authority
JP
Japan
Prior art keywords
amplifier circuit
voltage source
feedback
input
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3003578A
Other languages
Japanese (ja)
Inventor
Motofumi Azetsuji
畔辻 基史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP3003578A priority Critical patent/JPH04242307A/en
Publication of JPH04242307A publication Critical patent/JPH04242307A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To eliminate a feedback terminal and an externally mounted capacitor for the amplifier circuit. CONSTITUTION:Load resistors 7, 8 of a differential amplifier 50 having an operating constant current source 13 is connected to a DC voltage source 17, a series connection comprising a PNP transistor (TR) 3 (4) for level shift, a diode 15 (16) and a resistor 9 (10) is connected to a base of a PNP TR 1 (2), and a resistor 11 determining an input impedance and an input terminal 23 are connected to a base of a PNP TR3. A 1st (2nd) output of a differential amplifier 50 is connected to a noninverting input of a negative feedback amplifier circuit 19 (20) having feedback resistors 27, 28 (29, 30) and one terminal of the feedback resistors 28, 30 is connected to a DC voltage source 18.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は増幅回路に関し、特に、
Balanced  Transformer−les
s(通常BTLといい以下この略号を使う)方式の増幅
回路に関する。
[Field of Industrial Application] The present invention relates to an amplifier circuit, and in particular,
Balanced Transformer-less
This invention relates to an amplifier circuit of the s (usually referred to as BTL, and this abbreviation will be used hereinafter) type.

【0002】0002

【従来の技術】いわゆるBTL方式の増幅回路とは、2
組の増幅器を用い、それぞれの増幅器の出力における信
号の位相が互に逆になる様に駆動し、その出力端子間に
負荷を接続することにより、単体増幅器の2倍の出力電
圧を負荷に供給できる様にし、負荷のインピータンスが
同じなら、単体増幅器の4倍の電力信号を取り出すこと
ができる様に構成した増幅器のことである。
[Prior Art] The so-called BTL type amplifier circuit is divided into two types.
By using a pair of amplifiers, driving the signals at the output of each amplifier so that the phases are opposite to each other, and connecting a load between the output terminals, an output voltage twice as high as that of a single amplifier is supplied to the load. This is an amplifier configured so that it can extract four times as much power signal as a single amplifier if the load impedance is the same.

【0003】このような従来のBTL方式増幅回路の一
例を示すと、図3の様な回路構成となっている。
An example of such a conventional BTL type amplifier circuit has a circuit configuration as shown in FIG.

【0004】図3において、この回路は、抵抗157,
158を介してエミッタ共通で定電流源163に接続さ
れたPNPトランジスタ151,152のコレクタに負
荷抵抗159,160を接続し、PNPトランジスタ1
51,152のコレクタを第1および第2の出力とする
差動増幅器150と、PNPトランジスタ153,15
4,155,156,およびダイオード169,170
,171,172,および定電流源162,164,1
65,166で構成されているレベルシフト回路と、差
動増幅器150の第1の出力を入力とし、帰還抵抗18
5,186を有する第1の負帰還増幅回路173と、第
2の出力を入力とし、帰還抵抗187,188を有する
第2の負帰還増幅回路174と、中点設定用定電流源1
67,168,およびコンデンサ183,184,およ
び端子181,182とで構成されている。
In FIG. 3, this circuit includes resistors 157,
Load resistors 159 and 160 are connected to the collectors of PNP transistors 151 and 152, whose emitters are commonly connected to a constant current source 163 via 158, and the PNP transistor 1
A differential amplifier 150 whose first and second outputs are the collectors of 51 and 152, and PNP transistors 153 and 15.
4,155,156, and diode 169,170
, 171, 172, and constant current sources 162, 164, 1
65, 166 and the first output of the differential amplifier 150 as input, and a feedback resistor 18.
5,186, a second negative feedback amplifier circuit 174 which takes the second output as input and has feedback resistors 187, 188, and a constant current source 1 for setting the midpoint.
67, 168, capacitors 183, 184, and terminals 181, 182.

【0005】この回路は、入力端子177に信号が入力
されると、直流的にレベルシフトされた信号は、差動増
幅器150に入力され、この差動増幅器150の出力に
はそれぞれ逆位相の信号が出力され、その第1および第
2の出力信号は、それぞれ第1および第2の負帰還増幅
回路173,174にて増幅され、出力端子179と出
力端子180とにもそれぞれ逆位相の信号が出力される
In this circuit, when a signal is input to the input terminal 177, the level-shifted signal is input to the differential amplifier 150, and the output of the differential amplifier 150 receives signals of opposite phases. is output, and the first and second output signals are amplified by first and second negative feedback amplifier circuits 173 and 174, respectively, and signals with opposite phases are also output to output terminal 179 and output terminal 180, respectively. Output.

【0006】従って、出力端子179および180との
間に接続された負荷抵抗175に、単位増幅器の4倍の
出力電圧を得ることができる。
[0006] Therefore, an output voltage four times that of the unit amplifier can be obtained at the load resistor 175 connected between the output terminals 179 and 180.

【0007】なお、定電流源167,168は、それぞ
れ第1,第2の負帰還増幅回路173,174の出力端
子179,180の中点設定用であり、コンデンサ18
3,184は、それぞれ第1,第2の負帰還増幅回路1
73,174に直流電圧利得をもたせないためのもので
ある。
The constant current sources 167 and 168 are for setting the midpoints of the output terminals 179 and 180 of the first and second negative feedback amplifier circuits 173 and 174, respectively, and
3 and 184 are the first and second negative feedback amplifier circuits 1, respectively.
This is to prevent DC voltage gain from occurring in 73 and 174.

【0008】出力端子179,180間に、負荷175
が接続される。
A load 175 is connected between the output terminals 179 and 180.
is connected.

【0009】[0009]

【発明が解決しようとする課題】このような従来のBT
L方式増幅回路の場合、信号入力を接地基準で行なうよ
うにするために、出力端子の中点設定を帰還抵抗に直流
電流を流すことによる電圧上昇を利用している。このた
め、負帰還増幅回路173,174の直流電圧利得を除
去するためのコンデンサ183,184が必要となる。 これは、IC化した時、負帰還増幅回路173,174
のそれぞれの帰還端子181,182及び外付コンデン
サン183,184が必要となるため、ICの小型化及
び外付部品を含めた低価格化を進めた上で障害となって
いた。
[Problem to be solved by the invention] Such a conventional BT
In the case of the L-type amplifier circuit, in order to perform signal input with a ground reference, the midpoint of the output terminal is set using a voltage increase caused by passing a direct current through a feedback resistor. Therefore, capacitors 183 and 184 are required to remove the DC voltage gain of negative feedback amplifier circuits 173 and 174. When integrated into an IC, the negative feedback amplifier circuits 173 and 174
Since feedback terminals 181, 182 and external capacitors 183, 184 are required, this has been an obstacle to miniaturization of ICs and cost reductions including external components.

【0010】本発明の目的は、前記障害を除去して、外
付コンデンサを使用せずに済むようにした増幅回路を提
供することにある。
[0010] An object of the present invention is to provide an amplifier circuit which eliminates the above-mentioned obstacles and eliminates the need for external capacitors.

【0011】[0011]

【課題を解決するための手段】本発明の構成は、入力回
路に差動増幅回路を備え、前記差動増幅回路の一対の出
力のうち一方,他方を入力とし、かつ負荷が接続される
一対の出力端子のうち一方,他方に出力を送る第1,第
2の負帰還増幅回路を備えた増幅回路において、前記差
動増幅回路の負荷抵抗を第1の定電圧源に接続し、前記
第1,第2の負帰還増幅回路の帰還抵抗の一端を第2の
定電圧源に接続したことを特徴とする。
[Means for Solving the Problems] The configuration of the present invention is such that an input circuit includes a differential amplifier circuit, one and the other of a pair of outputs of the differential amplifier circuit are used as inputs, and one pair of outputs to which a load is connected. In the amplifier circuit, the load resistance of the differential amplifier circuit is connected to a first constant voltage source, and the load resistance of the differential amplifier circuit is connected to a first constant voltage source, and 1. One end of the feedback resistor of the second negative feedback amplifier circuit is connected to the second constant voltage source.

【0012】0012

【実施例】図1は本発明の一実施例の増幅回路を示す回
路図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an amplifier circuit according to an embodiment of the present invention.

【0013】図1において、本実施例の増幅回路では、
動作用定電流源13を有する差動増幅器50の負荷抵抗
7および8に直流電圧源17が接続され、PNPトラン
ジスタ1,2のベースにレベルシフト用のPNPトラン
ジスタ3,4,ダイオード15,16,抵抗9,10の
直列体がそれぞれ接続され、PNPトランジスタ3のベ
ースには入力端子23と入力インピーダンスを決める抵
抗11とが接続されている。差動増幅器50の第1およ
び第2の出力は、それぞれ帰還抵抗27,28および2
9,30を有する負帰還増幅回路19,20の正相入力
に接続され、帰還抵抗28および30には、直流電圧源
18が接続されている。
In FIG. 1, in the amplifier circuit of this embodiment,
A DC voltage source 17 is connected to load resistors 7 and 8 of a differential amplifier 50 having a constant current source 13 for operation, and PNP transistors 3 and 4 for level shifting, diodes 15 and 16 are connected to the bases of PNP transistors 1 and 2. Resistors 9 and 10 are connected in series, and the base of the PNP transistor 3 is connected to an input terminal 23 and a resistor 11 that determines input impedance. The first and second outputs of the differential amplifier 50 are connected to feedback resistors 27, 28 and 2, respectively.
A direct current voltage source 18 is connected to the feedback resistors 28 and 30.

【0014】なお、直流電圧源17,18はIC内部で
つくることができる程度の電圧源で充分である。
Note that it is sufficient for the DC voltage sources 17 and 18 to be voltage sources that can be generated inside the IC.

【0015】尚、さらに定電流源12,13,14等が
設けられる。
Furthermore, constant current sources 12, 13, 14, etc. are further provided.

【0016】このBTL構成された増幅回路は、直流電
圧源17,18の設定を電圧源18については電源端子
22と接地端子24の中点電位になるように設定し、電
圧源17については電圧源18から抵抗8の電圧降下分
を引いた電圧に、つまりPNPトランジスタ1および2
のコレクタと電圧源18の直流電圧が等しくなるように
設定する。
In this BTL-configured amplifier circuit, the DC voltage sources 17 and 18 are set so that the voltage source 18 has a midpoint potential between the power supply terminal 22 and the ground terminal 24, and the voltage source 17 has a voltage source 18 minus the voltage drop across resistor 8, that is, PNP transistors 1 and 2.
The DC voltage of the collector of the voltage source 18 and the voltage source 18 are set to be equal.

【0017】またこの時、PNPトランジスタ1および
2のベース電位は、電圧源18より高く設定しておく。
At this time, the base potentials of the PNP transistors 1 and 2 are set higher than the voltage source 18.

【0018】入力端子23に入力された信号は、PNP
トランジスタ3およびダイオード15及び抵抗9により
もちあげられ、差動増幅器50に入力される。この差動
増幅器50により利得をあげられた第1および第2の出
力信号はそれぞれの第1および第2の負帰還増幅器19
,20に入力される。
The signal input to the input terminal 23 is PNP
The signal is lifted up by the transistor 3, diode 15, and resistor 9, and input to the differential amplifier 50. The first and second output signals whose gain has been increased by the differential amplifier 50 are sent to the respective first and second negative feedback amplifiers 19.
, 20.

【0019】この時、前記第1および第2の負帰還増幅
器19,20のそれぞれの正相および逆相入力端子は、
直流的に同電位である為、信号入力のみ増幅され、出力
端子25および26に出力され、負荷21の抵抗を接続
すれば、従来と同様に単体増幅器の4倍の電力が得られ
る。
At this time, the respective positive phase and negative phase input terminals of the first and second negative feedback amplifiers 19 and 20 are
Since they are at the same DC potential, only the signal input is amplified and output to the output terminals 25 and 26. If the resistor of the load 21 is connected, four times the power of a single amplifier can be obtained as in the conventional case.

【0020】負帰還増幅器の出力段および入力のレベル
シフト回路については、図3に示した従来回路のほぼ動
作が同じであるが、本実施例においては、差動増幅器の
負荷抵抗側及び第1,第2の負帰還増幅器19,20の
帰還入力側を電圧源でバイアスすることにより、入力端
子12からの信号入力は、従来と同様に接地基準で行な
え、かつ帰還端子および外付コンデンサの必要がなくな
る。
Regarding the output stage and input level shift circuit of the negative feedback amplifier, the operation is almost the same as that of the conventional circuit shown in FIG. By biasing the feedback input sides of the second negative feedback amplifiers 19 and 20 with a voltage source, the signal input from the input terminal 12 can be performed with the ground reference as in the conventional case, and the need for a feedback terminal and an external capacitor is eliminated. disappears.

【0021】図2は本発明の他の実施例の増幅回路を示
す回路図である。
FIG. 2 is a circuit diagram showing an amplifier circuit according to another embodiment of the present invention.

【0022】図2において、本実施例は、NPNトラン
ジスタを使用した実施例である。
In FIG. 2, this embodiment uses an NPN transistor.

【0023】本実施例では、負帰還増幅器66,67の
入力段であるNPNトランジスタで構成された差動増幅
器100,及び定電流源60および61を、直流電圧源
70に接続することにより、PNPトランジスタで構成
された前記一実施例と同様の効果が得られる。
In this embodiment, by connecting the differential amplifier 100 composed of NPN transistors, which is the input stage of the negative feedback amplifiers 66 and 67, and the constant current sources 60 and 61 to the DC voltage source 70, the PNP Effects similar to those of the above-mentioned embodiment configured with transistors can be obtained.

【0024】[0024]

【発明の効果】以上説明したように、本発明は、電圧利
得を決定する第1および第2の負帰還増幅器の帰還抵抗
の一端をそれぞれ基準電位となる直流電圧源に接続し、
かつ負帰還増幅器の前段となる差動増幅器の負荷抵抗側
を直流電圧源に接続することにより、特にIC化する際
帰還端子及び外付コンデンサを削減することができ、小
型化,低価格化が可能となるという効果を有する。
As explained above, the present invention connects one end of the feedback resistor of the first and second negative feedback amplifiers that determine the voltage gain to a DC voltage source serving as a reference potential,
In addition, by connecting the load resistance side of the differential amplifier, which is the front stage of the negative feedback amplifier, to a DC voltage source, it is possible to reduce the number of feedback terminals and external capacitors, especially when implementing an IC, resulting in smaller size and lower cost. This has the effect of making it possible.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例の増幅回路を示す回路図であ
る。
FIG. 1 is a circuit diagram showing an amplifier circuit according to an embodiment of the present invention.

【図2】本発明の他の実施例の増幅回路を示す回路図で
ある。
FIG. 2 is a circuit diagram showing an amplifier circuit according to another embodiment of the present invention.

【図3】従来のBTL方式の増幅回路を示す回路図であ
る。
FIG. 3 is a circuit diagram showing a conventional BTL type amplifier circuit.

【符号の説明】[Explanation of symbols]

1,2,3,4,53,54,151,152,153
,154,155,156    PNPトランジスタ
51,52    NPNトランジスタ5,6,7,8
,9,10,11,55,56,57,58,59,1
57,158,159,160,161    抵抗 183,184    コンデンサ 15,16,63,64,169,170,171,1
72    ダイオード 12,13,14,60,61,62,162,163
,164,165,166,167,168    定
電流源 17,18,65    定電圧源 19,20,66,67,173,174    負帰
還増幅回路 21,68,75    負荷 23,71,177    入力端子 22,69,70,176    電源端子25,26
,73,74,179,180    出力端子24,
72,78    接地端子 81,82    帰還端子
1, 2, 3, 4, 53, 54, 151, 152, 153
, 154, 155, 156 PNP transistor 51, 52 NPN transistor 5, 6, 7, 8
,9,10,11,55,56,57,58,59,1
57, 158, 159, 160, 161 Resistor 183, 184 Capacitor 15, 16, 63, 64, 169, 170, 171, 1
72 Diode 12, 13, 14, 60, 61, 62, 162, 163
, 164, 165, 166, 167, 168 Constant current source 17, 18, 65 Constant voltage source 19, 20, 66, 67, 173, 174 Negative feedback amplifier circuit 21, 68, 75 Load 23, 71, 177 Input terminal 22 , 69, 70, 176 Power terminal 25, 26
, 73, 74, 179, 180 output terminal 24,
72, 78 Ground terminal 81, 82 Feedback terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  入力回路に差動増幅回路を備え、前記
差動増幅回路の一対の出力のうち一方,他方を入力とし
、かつ負荷が接続される一対の出力端子のうち一方,他
方に出力を送る第1,第2の負帰還増幅回路を備えた増
幅回路において、前記差動増幅回路の負荷抵抗を第1の
定電圧源に接続し、前記第1,第2の負帰還増幅回路の
帰還抵抗の一端を第2の定電圧源に接続したことを特徴
とする増幅回路。
Claim 1: The input circuit includes a differential amplifier circuit, one of the pair of outputs of the differential amplifier circuit and the other is input, and the load is connected to one and the other of the pair of output terminals. In the amplifier circuit, the load resistance of the differential amplifier circuit is connected to a first constant voltage source, and the load resistance of the differential amplifier circuit is connected to a first constant voltage source. An amplifier circuit characterized in that one end of a feedback resistor is connected to a second constant voltage source.
JP3003578A 1991-01-17 1991-01-17 Amplifier circuit Pending JPH04242307A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3003578A JPH04242307A (en) 1991-01-17 1991-01-17 Amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3003578A JPH04242307A (en) 1991-01-17 1991-01-17 Amplifier circuit

Publications (1)

Publication Number Publication Date
JPH04242307A true JPH04242307A (en) 1992-08-31

Family

ID=11561340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3003578A Pending JPH04242307A (en) 1991-01-17 1991-01-17 Amplifier circuit

Country Status (1)

Country Link
JP (1) JPH04242307A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS568911A (en) * 1979-07-05 1981-01-29 Toko Inc Btl amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS568911A (en) * 1979-07-05 1981-01-29 Toko Inc Btl amplifier

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