JPH04239957A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To remove the inconstant elements in the controller by realizing the synchronizing relation between the controller whose operation is started or terminated by the access of the microprocessor unit and microprocessor unit. CONSTITUTION:In the controller whose operation is started or terminated by the access of the microprocessor unit, the clock signal CM for writing the operation of controller is not changed while the chip select signal CM outputted from the microprocessor unit is in active condition.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to semiconductor integrated circuit devices, and particularly to microprocessor units (hereinafter referred to as MPUs).
The present invention relates to a semiconductor integrated circuit device that realizes a synchronous relationship between a controller and an MPU that start or end operations upon access to a controller.

0002

[Prior Art] FIG. 3 shows, for example, the Mitsubishi Semiconductor Bipolar Digital IC<ALS, published on March 10, 1986.
This is a circuit diagram similar to that of the M74ACS16113P on page 2-93 of the TTL edition, which has a logic design based on timing requirements, and in the figure (1) is a counter with a load input terminal LOAD and a ripple carry output terminal RCO. , (2), (4), and (5) are D-type flip-flops (hereinafter referred to as D-F/F), (8) is an internally generated clock input signal FX of the counter (1), (9) is internally generated D-F/F(2
) clock input signal F2X, (10) is a chip select signal output from the MPU (not shown)

[Example 1] , (12) is the internally generated data input signal CMD of DF/F (4), and (13) is the clock input signal of DF/F (4) output from the MPU.

[Outside 2] , (14) is the counter (1)

[Outside 3] Signal (15) is the output signal of D-F/F (2),
-F/F (5) clock input signal, (17) is D-
The output signal of F/F (4) is the data input of D-F/F (5), and (18) is the output signal (command signal) of D-F/F (5). A clock input signal FX (8) is input to the clock input terminal T of the counter (1),
Ripple carry output terminal of counter (1)

[4] is connected to the data input terminal D of D-F/F (2). The output terminal Q of D-F/F (2) is the counter (1)
Load input terminal of

Connected to [Outer 5]. A clock input signal F2X(9) is supplied to the clock input terminal T of this DF/F(2). Also, the output terminal Q of D-F/F (2) is
It is connected to the clock input terminal T of F(5), and this D-F
/F(5) data input terminal D is D-F/F(4)
is connected to output terminal Q of. And D-F/F(4)
Data input signal CMD (12) is input to data input terminal D of
is supplied, and the clock input signal W is supplied to the clock input terminal T.
(13) is input.

Next, the operation will be explained with reference to the operation timing chart shown in FIG. The counter (1) starts counting by applying the FX signal (8), and the counter (1) starts counting.

[Example 6] When the F2X signal (9) is applied to D-F/F (2) at the timing when the signal (14) becomes active state “L”, D-F/F (2)

After receiving the signal (14), the CM' signal (15), which is the output signal of the DF/F (2), becomes "L". This signal is used as load input to counter (1).

[Outside 8] of the counter (11).

[Example 9] Set the signal (14) to "H". Upon receiving this signal, D-F
The CM' signal (15) of /F(2) becomes "H". On the other hand, the D-F/F (4), which uses the CMD signal (12) and the data input signal W (13) as a clock input, outputs a CMD' signal (17), and this CMD' signal (17) is used as a clock input. Read at the rising edge of CM' signal (15), C
Outputs the OM signal (18).

0004

Problem to be Solved by the Invention Since the conventional semiconductor integrated circuit device is configured as described above, the CM' signal (
If the rising edge of 15) and the change in the CMD' signal (17) do not meet the timing requirements, the COM signal (18) will become a logically uncertain pulse and will not output a normal waveform, causing controller operation. There were problems such as instability.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit device in which the synchronous relationship between the controller and the MPU can be realized using simple control signals.

[0006]

[Means for Solving the Problems] In a semiconductor integrated circuit device according to the present invention, in a controller that starts or ends an operation upon access from a microprocessor unit, a clock signal for writing the operation of the controller is transmitted to the microprocessor unit. The chip select signal output from the chip select signal does not change while it is in the active state.

[0007]

[Operation] In this invention, the F2X signal (9)
The AND signal of the and CS signal (10) is used as the pre-clock signal for operation control, the signal synchronized with this pre-clock is used as the data input, and the S2X signal (11), which has a different phase from the F2X signal (9), is used as the clock input. D-F/F(
3) Use the output signal as the clock signal for operation control.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of the present invention,
In the same figure, parts corresponding to those in FIG. 3 are designated by the same reference numerals.
A detailed explanation thereof will be omitted. In the figure, (3) is D-
F/F, (6) is an AND circuit, (7) is an inverter circuit, (11) is an S with a different phase from the F2X signal (9)
2X signal, (16) is the output signal C of D-F/F (3)
It is M. Data input terminal D of D-F/F (3) is D
-F/F (2) is connected to the output terminal of D-F/F (
3) The clock input terminal T is the inverter circuit (7)
The S2X signal (11) is supplied to the input side of this inverter circuit (7). Also D-F/
Output terminal Q of F (3) is the load input terminal of counter (1)

It is connected to the clock input terminal T of the D-F/F (5). Both input terminals of the AND circuit (6) are connected to the F2X signal (9),

A signal (10) is supplied, and the output terminal of the AND circuit (6) is connected to the clock input terminal T of the DF/F (2).

Next, the operation will be explained with reference to FIG. Compared to the conventional circuit, the clock input signal of D-F/F (2) is changed to the F2X signal (9).

[Outer 12] Since it is an AND signal of signal (10),

[Outside 13
] While the signal (10) is “L”, the clock input signal F2X’ (6) of D-F/F (2) is fixed to “L”,

[
External 14] D corresponding to CMD signal (12) read with signal (13)
Change in CMD' signal (17) from -F/F (4) and clock input signal F2X' (6) of D-F/F (2)
The timing conditions of are respected and stable CM'(15)
A signal can be obtained at the output side of DF/F (2). Furthermore, since the F2X signal (9) and the CS signal (10) are asynchronous, their AND signal may not satisfy the minimum clock pulse width of the DF/F (2). In this case D-
The CM' signal (15), which is the output signal of F/F (2), becomes unstable. Next, a CM signal (16) is obtained which is an output signal of the DF/F (3) which uses the unstable CM' signal (15) as a data input and the inverted signal of the S2X signal (11) as a clock input. This CM signal (16) satisfies the timing requirements and is the operating clock signal for the controller. By taking in the CMD' signal (17) from the DF/F (4) as a data input signal using this CM signal (16), the output side of the DF/F (5) is as shown in Figure 2. A logically determined COM signal (18) can be obtained. In other words,

[Example 15] While the signal (10) is in the active state (L), the CM signal (16) should not change, that is, the COM signal (
18) is disabled, so the operation of this controller will not become unstable. In addition,

[Outer 16] for signal (13)

[Outside 17] Setup time and hold time of signal (10) are 10
ns or more. In addition, in FIG. 2, the dotted line indicates the state where the COM signal (18) does not change, that is, the CMD signal (12
) is not imported into the controller.

0010

As described above, the present invention provides a controller that starts or ends its operation upon access from a microprocessor unit, in which a clock signal for writing the operation of the controller is output from the microprocessor unit. Since the select signal does not change while it is active, a logically determined command signal can be obtained, which prevents the controller from becoming unstable and allows easy connection with various MPUs. play.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is an operation timing diagram of FIG. 1;

FIG. 3 is a circuit configuration diagram showing a conventional semiconductor integrated circuit device.

FIG. 4 is an operation timing diagram of FIG. 3;

[Explanation of symbols]

1 Counter 2 to 5 D type flip-flop 6 A
ND circuit

Claims (1)

[Claims] Claim 1: A controller that starts or ends an operation upon access from a microprocessor unit,
A semiconductor integrated circuit device, wherein a clock signal for writing an operation of the controller does not change while a chip select signal output from the microprocessor unit is in an active state.