JPH04101147U - Edge detection circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Even in the stop mode where the operating clock is stopped, rising and falling edges are detected in the same way as in normal operation. [Configuration] D flip-flop 1 for falling edge detection
and a D flip-flop 2 for detecting rising edges, input terminal 3 receives a falling/inverted rising selection signal φ1, and input terminal 4 receives a falling/inverted rising selection signal inverted by an inverter 12. Input φ1. Next, the data signal φ2 is applied to the clock terminal 5 of the D flip-flop 1.
A data signal inverted by an inverter circuit 11 is input to the clock terminal 6 of the D flip-flop 2. Then, the output signals of the output terminals 9 and 10 of the D flip-flops 1 and 2 are outputted as an edge detection signal φ5.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention has a low power consumption mode (stop mode) that stops the operating clock. Edge (rising/rising edge) in the external interrupt function of microcontrollers with This relates to the downlink) detection circuit.

0002

[Conventional technology]

FIG. 3 shows a configuration example of a conventional edge (rising/falling) detection circuit. This figure 3 When falling edge detection is selected in the circuit (falling/inverted rising selection signal φ1 A time chart showing the operation of H) is shown in FIG.

0003 The D flip-flop 101 outputs the input data φ2 at the falling edge of the clock φ7. Output to the power end 109. Similarly, the D flip-flop 102 also receives the rise of the clock φ7. On the downstream side, the Q output of the D flip-flop 101 is outputted to the Q output terminal 110.

0004 When falling edge detection is selected, falling/inverted rising select signal φ1 is H. Since the AND circuit 113 is selected from the AND circuits 113 and 114, The Q output of the D flip-flop 101 is L (the inverted Q output is H), and the D flip-flop When the Q output of the pulley 102 is H, the detection signal φ5 becomes H, and a falling edge is detected.

[0005] When rising edge detection is selected, the falling/inverted rising edge selection signal φ1 is L. Since the AND circuit 104 is selected, the Q output of the D flip-flop 101 is Detected when the input voltage is H and the Q output of the D flip-flop 102 is L (the inverted Q output is H). The output signal φ5 becomes H, and the rising edge is detected.

[0006]

[Problem that the idea aims to solve]

However, in the edge (rising/falling) detection circuit with the above structure, the input data The clock pulse φ7 is required to detect the falling and rising edges of the data signal φ2.

[0007] Two D flip-flops 101 and 102 turn on after clock pulse φ7. A Q output equal to the input data before the pulse input is performed. Therefore, clock pulse φ7 is not present, the input data signal φ2 is input to the D flip-flop 101. Also, the Q output of the D flip-flop 101 is not performed accordingly, and the D flip-flop The Q output of drop 102 also remains unchanged.

[0008] For example, when you select falling edge detection, the falling/inverted rising select signal φ1 changes from L to H, but since there is no clock pulse φ7, the D flip-flop There is no change after the Q output of the loop 101, and both the AND circuit 113 and the AND circuit 114 Because it is not selected, the falling edge cannot be detected.

[0009] Similarly, when rising edge detection is selected, the Q of the D flip-flop 101 is No change appears after the output, and the rising edge cannot be detected.

0010 For the above reasons, such conventional edge (rising/falling) detection circuits In stop mode, where the clock pulse stops, falling and rising edges can be detected. I can't do it.

[0011] The purpose of this invention is to , eliminates the problem of not being able to detect falling and rising edges, and To provide an edge detection circuit that can detect falling and rising edges even in It's there.

0012

[Means to solve the problem]

The above-mentioned problem of not being able to detect rising and falling edges in stop mode In order to solve this problem, the present invention has the following measures.

[0013] First, there is a first input terminal to which a falling selection signal is input, and a first input terminal to which a data signal is input. a clock terminal, a first reset terminal, and a first output terminal that outputs a falling detection signal. a first D flip-flop having a second D flip-flop, and a first D flip-flop having The first inverter circuit outputs the data signal, and the second inverter circuit inputs the rising edge selection signal. inputting the data signal inverted by the input terminal and the first inverter circuit; A second clock terminal, a second reset terminal, and a second output that outputs a rising edge detection signal. a second D flip-flop having a power terminal; a second D flip-flop having a power terminal; and an OR circuit that calculates the OR of edge detection signals and outputs an edge detection signal.

[0014] Alternatively, the falling and rising selection signals can be combined into one falling/inverted rising selection signal. Alternatively, use an inverted falling/rising selection signal. The selection signal is falling/inverted falling In the case of a selection signal, input the selection signal as it is to one of the first D input terminals. However, it is connected to the second D input terminal via an inverter circuit. And the output inputting a signal to the first and second reset terminals in response to an edge detection signal generated by the It consists of means for

[0015] Further, if the selection signal is the inverted falling/rising selection signal, The selection signal is input as is to one of the second D input terminals, and the selection signal is input to one of the second D input terminals. It is connected to the terminal via an inverter circuit for inverting the selection signal. And the output is means for inputting a signal to the first and second reset terminals in response to an edge detection signal; It consists of steps.

[0016]

[Effect]

According to the present invention, when falling edge detection is selected, the falling selection signal is H, and is input to the first input terminal of the first D flip-flop. On the other hand, the second input terminal of the second D flip-flop is connected to the rising edge detection terminal. Since I did not choose to go out, it remains at L.

[0017] If the data input to the first and second clock terminals falls , the signal at the clock terminal changes from H to L, and the first D flip-flop The output of the falling detection signal is set to H. The second D flip-flop is Since the rising edge selection signal remains L, even if the data rises, the rising edge detection The output of the output signal remains at L.

[0018] The detection signal is input to the logical sum circuit, the logical sum is calculated, and the edge detection is performed. Let the signal output be H.

[0019] When rising edge detection is selected, the rising selection signal becomes H and the above-mentioned It is input to the second input terminal of the second D flip-flop. On the other hand, the first The first input terminal of the D flip-flop indicates whether falling edge detection is selected or not. Therefore, it remains at L.

[0020] If the input data falls, the input data signal will change from L to H. , because the first inverter circuit is placed in the middle, the state changes from H to L. This conclusion As a result, the second D flip-flop outputs the rising edge detection signal. As with the case where the terminal is set to H and the falling edge detection described above is selected, the above-mentioned Outputs edge detection signal.

[0021] Also, the rising and falling selection signals can be combined into one falling/inverted rising selection signal or is an inverted falling/rising selection signal, and one of the first and second input terminals has that signal. By inputting the signal as it is and connecting it to the other side via an inverter circuit for inverting the selection signal. Therefore, signals of opposite phase are always input to the first and second input terminals. As a result, when the falling selection signal is H, the rising selection signal is L, and the falling selection signal is When is L, the rising selection signal becomes H. Then, in response to the edge detection signal, A signal output from the means is input to the first and second reset terminals, The edge detection signal is reset to L.

[0022] Due to the above action, clock pulses are used to detect the rising and falling edges of input data. This makes it possible to operate an edge detection circuit that does not require a bus.

[0023]

【Example】

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing a second embodiment of the present invention. FIG. 2 is a circuit diagram showing an example. In FIG. 2, the falling/inverted rising select signal φ1 in FIG. By dividing into two signals, the rising selection signal φ1a and the rising selection signal φ1b. , falling edge detection and rising edge detection can be selected individually or simultaneously. It is a circuit. Note that in FIGS. 1 and 2, the same circuit as the conventional edge detection circuit in FIG. The configuration requirements are displayed using the same number.

[0024] Figure 4 shows the circuit in Figure 1 when falling edge detection is selected (falling/inverted rising edge selection). 3 is a time chart showing the operation when the signal φ1 is H).

[0025] The edge (rising/falling) detection circuit in Figure 1 uses the falling/inverted rising select signal φ The D input terminal 3 that inputs 1 and the clock terminal 5 that inputs the input data signal φ2 are connected. A D flip-flop having a set terminal 7 and a Q output terminal 9 that outputs a detection signal φ3. 1, an inverter circuit 11 inputting the input data signal φ2, and a falling/inverting An inverter circuit 12 that inputs a rising selection signal φ1 and outputs it in reverse phase; D input terminal 4 inputs the output of the circuit 12 and inputs the output of the inverter circuit 11 The clock terminal 6, the reset terminal 8, and the Q output terminal 10 that outputs the detection signal φ4 are connected to each other. A D flip-flop 2 having a The OR circuit 13 that outputs the and a means 14 consisting of, for example, a gate circuit, which inputs the gate signal φ6. .

[0026] The edge (rising/falling) detection circuit in FIG. 2 has an inverter circuit 12. The falling selection signal φ1a and the rising selection signal φ1b are separately connected to the D input terminal. 3 and D input terminal 4. And instead of Q output terminals 9 and 10, The inverted Q output terminal 9a and the inverted Q output terminal 10a are connected to the non-AND circuit 13a, and the logic It works in the same way as a logic and sum circuit.

[0027] The operation of this embodiment will be explained with reference to FIGS. 1 and 4.

[0028] When selecting falling edge detection, the falling/inverted rising select signal φ1 is set to H. select. If input data φ2 falls (H→L), D flip-flop 1 The detection signal φ3 from the Q output terminal 9 becomes H. At this time, D flip-flop 2 The D input terminal 4 of the Since the upstream selection signal φ1 (inverted falling/rising selection signal) is input, even if the Even if the force data φ2 rises, the detection signal φ4 remains at L level.

[0029] A logical sum circuit 13 calculates the logical sum of the output results of the D flip-flops 1 and 2 described above. Since the detection signal φ3 is H, the detection signal φ5 is H. standing After the falling edge is detected, the reset signal φ6 is set to H by the reset signal input means 14. do. As a result, the D flip-flop 1 is reset and the detection signal φ5 is set to L. Ru.

[0030] When selecting rising edge detection, the falling/inverted rising edge selection signal φ1 is set to L. By selecting and passing the inverter circuit 12, the D input of the D flip-flop 2 It becomes H at terminal 4. If input data φ2 rises (L→H), the inverter Due to the circuit 11, the clock terminal 6 changes from H to L, resulting in a D flip-flop. The detection signal φ4 from the Q output terminal 10 of the top 2 becomes H. At this time, D flip Since the input to the D input terminal 3 of the loop 1 is L, the detection signal φ3 remains at L. There is even.

[0031] A logical sum circuit 13 calculates the logical sum of the output results of the D flip-flops 1 and 2 described above. Since the detection signal φ4 is H, the detection signal φ5 is H. standing After the rising edge is detected, the reset signal φ6 is set to H by the reset signal input means 14. As a result, the D flip-flop 2 is reset and the detection signal φ5 is set to L. .

[0032] A gate circuit can be used as the reset signal input means 14, but in this case The reset signal input means in the present invention is not limited to this, but can be Edge detection signal φ with the pulse width required in devices using edge detection circuits Any mechanism that generates the reset signal φ6 after 5 is output is sufficient, and a number of mechanisms are possible. Variations are possible.

[0033] The operation of the embodiment shown in FIG. 2 is as follows: The falling selection signal φ1a to the D input terminal 3 of the flip-flop 1 and the D input terminal of the D flip-flop 2 The rising selection signal φ1b to the power terminal 4 is divided into two. By this division, the falling It is possible to select rising edge detection and rising edge detection individually or simultaneously. However, the falling and rising edge detection operations are the same as in the embodiment of FIG. .

[0034]

[Effect of the idea]

As explained in detail above, according to the present invention, the clock end of the D flip-flop Since the input data signal is input to the child, it is possible to detect rising and falling edges. Therefore, it is useful in stop mode where the operating clock is stopped. It is possible to detect rising and falling edges in the same way as during normal operation.

[0035] Also, one falling/inverted rising selection signal is used as that of two D flip-flops. If one is input in opposite phase to each input terminal, when the falling selection signal is H, the rising When the selection signal is L and the falling selection signal is L, the rising selection signal becomes H, and one It is possible to select between falling edge detection and rising edge detection for the signal.

[Brief explanation of drawings]

FIG. 1 shows an edge (rising/falling) detection circuit according to a first embodiment of the present invention.

FIG. 2 shows an edge (rising/falling) detection circuit according to a second embodiment of the present invention.

FIG. 3 shows an edge (rising/falling) detection circuit according to the prior art.

[Figure 4] Edges (rising/falling) of Figure 1, which is the invention
5 is a time chart showing the operation of the detection circuit when falling edge detection is selected.

FIG. 5 is a time chart showing the operation of the conventional edge (rising/falling) detection circuit shown in FIG. 3 when falling edge detection is selected.

[Explanation of symbols]

1 D flip-flop for falling edge detection 2 D flip-flop for rising edge detection 11 Inverter circuit for inverting input data 12 Inverter circuit for inverting falling/inverted rising selection signal 13 OR circuit 14 Reset signal generation means

Claims (3)

[Scope of utility model registration request] Claim 1: (a) A first input terminal for inputting a falling selection signal, a first clock terminal for inputting an input data signal, a first reset terminal, and a first output terminal for outputting a first detection signal. a first D flip-flop having an output terminal;
(b) a first inverter circuit to which the input data signal is input; (c) a second input terminal to which the rising edge selection signal is input; a second clock terminal to which the output signal of the first inverter is input; a second D flip-flop having a second reset terminal and a second output terminal that outputs a second detection signal; An edge detection circuit for detecting rising and falling edges of the input data signal, comprising an OR circuit that outputs a signal. (a) A first input terminal to which a falling/inverted rising selection signal is input, and a first input terminal to which an input data signal is input.
(b) a first D flip-flop having a clock terminal, a first reset terminal, and a first output terminal that outputs a first detection signal; (b) a first D flip-flop that receives the input data signal;
(c) a second inverter circuit that receives the falling/inverted rising selection signal and outputs it as an inverted falling/rising signal; (d) a second inverter circuit that receives the inverted falling/rising selection signal; a second clock terminal into which the output signal of the first inverter is input;
a second D flip-flop having a reset terminal and a second output terminal that outputs a second detection signal; and (f) means for inputting a reset signal to the first and second reset terminals in response to the third detection signal. Edge detection circuit that detects rising and falling edges. 3. (a) a first inverter circuit that inputs an inverted falling/rising selection signal and outputs a falling/inverted rising selection signal; (b) a first inverter circuit that inputs the falling/inverted rising selection signal; (c) a first D flip-flop having one input terminal, a first clock terminal inputting an input data signal, a first reset terminal, and a first output terminal outputting a first detection signal; a second inverter circuit to which the input data signal is input; (d) a second input terminal to which the inverted falling/rising selection signal is input; and a second clock terminal to which the output signal of the first inverter is input. and second
(e) a second D flip-flop having a reset terminal and a second output terminal that outputs a second detection signal; and (f) means for inputting a reset signal to the first and second reset terminals in response to the third detection signal. Edge detection circuit that detects rising and falling edges.