JPH04239272A - Compressing and extending device - Google Patents

Abstract

PURPOSE:To obtain a compressing and extending device at a low cost by dividing data such as a picture signal into a high-order one and a differential low- order one in order to be in the number of bits capable of being used by an LSI at a low cost. CONSTITUTION:The high-order bit of digital data such as the picture signal is turned into a compressed signal by a first compressor 2 at a compression side, and decoded by a decoder 3. Then, a difference between the decoded signal and the original signal is searched by a differential equipment 6, the low-order bit of the difference is compression-encoded by a second compressor 7, the output of the first compressor 2 is switched to the compression-encoded data by a switcher 8, and the data are outputted as compressed data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for compressing and expanding digital signals such as images.

0002

2. Description of the Related Art Conventionally, various companies have developed LSIs that can compress 8-bit gradation input signals in accordance with international standards. For normal television images, 8-bit gradation is sufficient. However, for some medical images, such as images from X-ray films, it is necessary to display even the slightest level change, so there are some applications where 8-bit gradation input/output is insufficient. This countermeasure requires 10bit or 12bit
In order to enable bit gradation input/output, it is necessary to manufacture a new LSI with an increased number of internal bits of arithmetic precision. However, since the use of 10-bit or 12-bit LSIs is limited, there is little hope that LSI prices will decrease due to mass production effects. Furthermore, as the number of gates mounted on the LSI increases, the scale of the LSI becomes larger. On the other hand, TTL
Although it is possible to construct a circuit equivalent to an LSI using elements, etc., the scale, power, etc. would be unrealistic.

0003

[Problem to be solved by the invention] The above-mentioned prior art includes:
If the number of gradation bits of the image signal to be handled exceeds 8 bits, there is a drawback that inexpensive LSI cannot be used and the device becomes expensive. An object of the present invention is to solve the above-mentioned drawbacks by dividing image signal data into a plurality of upper and differential lower parts and processing the data so that the number of bits can be used by an inexpensive LSI.

0004

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first compressor and a decoder for compressing and encoding upper-level image data, and calculates the difference between the decoded signal and the original signal.
The lower bits of the difference are encoded by the second compressor.

[0005]

[Operation] For convenience of explanation, it is assumed that the original image data is 12 bits, and the upper, middle, and lower 4 bits are L, M, and S, respectively.
It is called. It is also assumed that the compressor has 8-bit input and output. The first compressor uses the upper L, excluding the lower 4 bits S,
A total of 8 bits of medium M are compressed to create upper compressed data CH. Next, the decoder expands the CH and 8 bits from the upper
Create decoded data of t. Then, using a subtractor, the original image data L, M, S 12 bits and the upper 8 bits are decoded.
Differences ΔL, ΔM, and ΔS between t data L' and M' are determined. By the way, normally ΔL is "0", and the difference is only 8 bits in total, ΔM and ΔS from the lower order. The second compressor compresses the lower 8 bits of the difference, and compresses the lower differential compressed data C.
Create ΔL. In other words, bits are first encoded from the higher order bits (creation of CH), and then quantization errors including the lower order bits that are excluded from the target are re-encoded (creation of CΔL). The above is an explanation on the compression encoding side, but on the decoding side, by adding the upper 8 bits of data L', M' obtained by expanding CH and CΔL, and the lower 8 bits of ΔM, ΔS, , a total of 12 bits of data can be decoded.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the overall configuration of a first embodiment of the present invention. In the figure, 1 is an input terminal for the original image, and the bit configuration consists of upper, middle, and lower L, M, and S bits. L, M are connected to the input of compressor 2. The output CH of the compressor 2 is connected to the input of the decoder 3 and delay5. The output CHd of delay 5 is connected to the A input of switch 8. The outputs L' and M' of the decoder 3 are connected to the A input of the differentiator 6, and the Ld, Md, and Sd obtained by delaying L, M, and S from the terminal 1 with delay 17 are connected to the B input of the differentiator 6. Ru. The outputs ΔM and ΔS of the differentiator 6 are connected to the input of the compressor 7. The output CΔL of the compressor 7 is connected to the B input of the switch 8. The outputs CHd and CΔL of the switch 8 are connected to the output terminal 9 of the code. The output CHd and CΔL of the terminal 9 are input to a transmission line or a recording device. Further, the extracted CHd·CΔL is applied to the code input terminal 10. Terminal 10 is connected to delay 11 and decoder 13. The output of delay 11 is connected to decoder 12. The outputs LR', MR' of the decoder 12 are connected to the input A of the adder 15. The outputs ΔMR and ΔSR of the decoder 13 are connected to the input B of the adder 15. Outputs LR, MR, and SR of the adder 15 are connected to an output terminal 16 for the decoded signal.

Next, the operation of the present invention will be explained. To simplify the explanation below, the original image data is D11 to D0.
With 12 bits, D11 to D8 are L, D7 to D4 are M,
It is assumed that D3 to D0 are expressed as S and each has 4 bits. The compressor 2 performs compression processing on the input image signal consisting of upper and middle bits of a total of 8 bits of L and M to create upper compressed data CH. This CH is input to the decoder 3, and an 8-bit decoded image signal consisting of L' and M' is reproduced. The difference unit 6 receives the upper 8-bit signal consisting of the values L' and M' created by the decoder 3, and the original signal L.
, M, and S. L'
, M' also roughly represent the original signal, so the above-mentioned difference is 8 bits or less in most cases. The 8-bit differential lower-order data ΔM and ΔS obtained in this manner are used in the compressor 7 to create differential lower-order compressed data called CΔL. The switch 8 outputs the upper compressed data CHd and the differentially lower compressed data CΔL in line with each other in the time axis direction. The compression side data CHd and CΔL are created in the above manner.

The processing on the decoding side will be described below. d
elay11 delays CHd until the time when compressed data CΔL begins to be input to the decoder 13. The result C
ΔL and CHd are applied to decoders 13 and 12 simultaneously. The decoder 12 outputs 8-bit data of upper and middle LR' and MR' by decompression processing. In addition, LR' in the figure
, MR' are the same data as L' and M' on the encoding side. The decoder 13 outputs the middle and lower ΔMR and ΔSR of the difference through expansion processing. The adder 15 adds 8 bits of LR' and MR' from the higher order and 8 bits of ΔMR and ΔSR from the lower order applied to inputs A and B, respectively, to generate 12 bits.
Outputs LR, MR, and SR of t.

The above-mentioned operation will be described for the case where the input signal has waveform (1) in FIG. 2 as an example. The waveform consisting of L' and M' obtained by compressing, decoding and expanding the upper and middle 8 bits is as shown in (2). In other words, in the gradual rising portion, the lower bits are truncated, resulting in a false contour. Here, (1)-(2) are performed to obtain a difference waveform (3) from the subtractor 6. Note that since the difference occurs with positive and negative values, it is necessary to add 80H or the like as an offset value so that the difference occurs around the positive 80H. On the compression side, the waveforms (2) and (3) are compressed and encoded to create CH and CΔL. The CH/CΔL that has passed through the transmission path etc. is decompressed by the decoders 12 and 1 in decompression processing on the decoding side.
Waveforms (2) and (3) are created from 3, respectively, and addition processing is performed to obtain a waveform close to (1). Here, the reason why it is expressed as "close" is that it is not necessarily possible to create a waveform identical to (3) through companding processing. This is because it is not always possible to create a waveform identical to (3).

FIG. 3 shows the overall configuration of a second embodiment of the present invention. The difference from FIG. 1 is that on the compression side there is a filter 4 between the decoder 3 and the subtractor 6, and on the decoding side there is a filter 4 between the decoder 3 and the subtractor 6.
The filter 14 is inserted between the adder 15 and the adder 15, respectively. That is, the outputs L', M' of the decoder 3
is connected to the input of the filter 4, and its outputs L'', M'', S'' are connected to the A input of the differentiator 6. Also, the outputs LR', MR' of the decoder 12 are connected to the input of the filter 14, Its outputs LR'', MR'', SR'' are connected to the A input of adder 15. This operation will be explained mainly with respect to the parts that are different from those in FIG. 1. As in the first embodiment, the output L of the decoder 3
The 8-bit signal consisting of ', M' has a processing accuracy of 1
A filter 4 having 2 bits calculates L'', M'', and S'' including S'' corresponding to the lower rank from changes in a total of 8 bits of the upper and middle ranks. Note that the basic properties of the filter are preferably two-dimensional LPF. The differentiator 6 has 12 bits consisting of the predicted values L″, M″, and S″ created by this filter 4.
The difference between the signal and the 12-bit signal consisting of the original signals L, M, and S is determined. Since L″, M″, and S″ also roughly represent the original signal, the above-mentioned difference is mostly due to the 8bit
t or less. Incidentally, since there is a possibility that a difference exceeding 8 bits may occur in rare cases, such a signal is limited to 8 bits and output. This is because the compressor 7 supports 8 bits. Furthermore, if the difference is mostly 7 bits or less, if the difference is enlarged by bit shifting or the like beforehand, and then outputted after being limited to 8 bits, it is possible to more accurately represent even a slight gradation change. In this way, the 8-bit differential lower-order data ΔM
, ΔS are obtained. The other data CHd and CΔL on the compression side are created in the same manner as in the first embodiment.

[0011] Regarding the processing on the decoding side, the decoder 1
The upper and middle LR′ output from 2 by decompression processing,
The 8-bit data of MR' is converted into 12-bit data of LR'', MR'', and SR'' by a filter 14 having the same configuration as the filter 4.
t data. In addition, LR″, MR″, S in the figure
R'' is the same data as L'', M'', and S'' on the compression side. The decoder 13 outputs the middle and lower ΔMR and ΔSR of the difference through expansion processing. The adder 15 receives the 12 bits LR'', MR'' and SR'' applied to inputs A and B and the lower side 8b.
12-bit LR by adding it to ΔMR and ΔSR
, MR, and SR are output. The above-described operation will be described for the case where the input signal has waveform (1) in FIG. 4. The waveform consisting of L' and M' obtained by compressing, decoding and expanding the upper and middle 8 bits is as shown in (2). In other words, in the gradual rising portion, the lower bits are truncated, resulting in a false contour. By filtering this (3
), the waveform has characteristics somewhat similar to (1). Here, perform (1)-(3) and convert the difference waveform (4) to the difference filter 6.
Get more. Note that the difference occurs as positive and negative, so add 80H etc. as an offset value to calculate the positive 80H difference.
It is necessary to make sure that this occurs mainly. The compression side is (2)
, (4) compression-encoded CH and CΔL
Create. The CH/CΔL that has passed through the transmission path etc. is output from the decoders 12 and 13 (2) and (
The waveform of (4) is created, and after (2) is converted into the waveform of (3) by the filter 14, addition processing is performed to obtain a waveform close to (1). Here, the reason why it is expressed as "close" is that it is not necessarily possible to create a waveform identical to (4) through companding processing.

The delay 17 delays the original data L, M, and S by the processing time of the compressor 2 and decoder 3. Specifically, this can be easily achieved by using Nippon Precision's SM5828 or the like. As the filter 4, a 12-bit compatible product with a configuration equivalent to Fujitsu's MB86281 may be used. Note that the output of the difference is 8b
If it does not fall within the range of .it, it is necessary to clip the output to 8 bits and convert ΔMCP and ΔSCP into signals. A simple means to achieve this is the ROM table lookup method, and the differentiator 6 uses such a ROM table lookup method.
The above explanation assumes that the output stage has a built-in output stage. In the above, the compression and expansion of image data have been described, but it is clear that the invention can also be applied to other data such as audio data.

[0013]

According to the present invention, it is possible to perform highly accurate gradation expansion processing even for multi-gradation images or audio that cannot be handled by a compandor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of FIG. 1;

FIG. 3 is a block diagram showing the overall configuration of a second embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of FIG. 3;

[Explanation of symbols]

2 Compressor 3 Decoder 4 Filter 5 Delay device 6 Differentiator with amplitude limit 7 Compressor 8 Switcher 11 Delay device 12 Decoder 13 Decoder 14 Filter 15 Adder 17 Delay device

Claims (4)

[Claims] Claim 1: In a compression/expansion device for original image data consisting of an upper bit group L, a middle bit group M, and a lower bit group S, the compression side first compresses and encodes the data consisting of the bit groups L and M. The upper compressed data CH is calculated, and secondly, the differences ΔL, ΔM, ΔS between L', M' created by decoding this data CH and each bit group L, M, S of the original image data are calculated.
, create differential lower-order data ΔMCP and ΔSCP with bit restrictions within the target bit width of the compression encoder,
Thirdly, these ΔMCP and ΔSCP are compressed and encoded to calculate differential lower compressed data CΔL, and fourthly, these CH and C
The configuration is such that ΔL is compressed code data, and on the other hand, the decoding side first decompresses the upper compressed data CH to obtain bit groups LR',
MR' is obtained, secondly, the differential lower data CΔL is expanded to obtain bit groups ΔMCP・R, ΔSCP・R, and thirdly, these bit groups LR′, MR′ and ΔMCP・R, ΔSCP・R are obtained.
1. A compression/expansion device characterized in that the compression/expansion device is configured to obtain decoded image data consisting of bit groups LR, MR, and SR by adding the bit groups LR, MR, and SR. [Claim 2] In claim 1, on the compression side, bit groups L'', M'', After obtaining S″, the differential lower-order data ΔM
CP, ΔSCP are created, and on the decoding side, from LR', MR' obtained by expanding the upper compressed data CH, a bit group LR'',
After obtaining MR″, SR″, bit group ΔMCP・R, Δ
A compression/expansion device characterized in that it performs addition with SCP/R. [Claim 3] In claim 1 or 2, on the compression side, after amplifying the differences ΔL, ΔM, and ΔS from the original image data by N times, bit restriction is applied to obtain ΔN・MCP, ΔN・SCP.
is compressed and encoded to calculate CΔN・L, which is used as differential lower compressed data. On the decoding side, ΔN・MCP・R obtained by expanding CΔN・L and ΔN・SCP・R are multiplied by 1/N and then A compression/expansion device characterized in that addition of LR' and MR' is performed. 4. The compression/expansion apparatus according to claim 1, wherein the original image data and the decoded image data are used as original audio data and decoded audio data, respectively.