JPH0786955A - Encoder - Google Patents

Abstract

PURPOSE:To reduce hardware scale by uniformly handling compressed encoding and channel encoding. CONSTITUTION:As the compressed encoding, ADRC encoding is applied. A television signal Vin is quantized and divided into blocks later. The output pixel data of a block circuit 13 are supplied to a detection circuit 14, and a minimum value MIN and a maximum value MAX are detected for each block. A dynamic range DR is provided from a subtraction circuit 15 for each block. Data DTI removing the minimum value MIN from the pixel data are provided from a subtraction circuit 17 and at an encoder 18, an encoded code DT is provided by quantizing those data again while deciding the number of bits to be quantized corresponding to the dynamic range DR. The encoded code for each picture element is outputted by a selector circuit 23 while being inverted for every other picture element, and additive data DR and MIN for each block are outputted from a selector circuit 19 while being inverted for every other block. The ratio of a DC component is decreased by the inversion, and the compressed encoding and the channel encoding can be handled in a unified way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an encoding device that performs block encoding such as DRC encoding.

[0002]

2. Description of the Related Art Conventionally, when image transmission (including recording) is considered, compression encoding for reducing information itself to be transmitted and channel encoding for compensating for characteristics in a transmission system are separately performed. Has been done. In this case, the compression coding and the channel coding have different purposes, and under the present circumstances, a coding method that optimizes each is considered.

The compression coding includes, for example, ADRC coding, DCT transform coding, wavelet transform coding and the like. In channel coding, a method in which the DC component is cut, such as M ² , 8-9 conversion, 8-10 conversion, etc., is usually proposed for optical transmission, magnetic recording, magneto-optical recording, and the like. There is.

FIG. 7 shows a general coding method.
The input signal is compression-encoded by the compression encoding circuit 1 and channel-encoded by the channel encoding circuit 2, and the encoded signal output from the channel encoding circuit 2 is supplied to the transmission line 3. The coded signal transmitted through the transmission path 3 is channel-decoded by the channel decoding circuit 4 and compression-decoded by the compression decoding circuit 5 to derive an output signal.

[0005]

Conventionally, compression encoding and channel encoding are performed by different encoding systems as described above, but if they can be handled by one unified encoding system. It is expected that benefits such as reduction in hardware scale and cost reduction will be obtained.

Therefore, according to the present invention, it is possible to provide a coding apparatus which can handle compression coding and channel coding in a unified manner and can obtain benefits such as reduction in hardware scale and cost reduction. It is a thing.

[0007]

An encoding device according to the present invention has a compression encoding means for converting an input digital signal into blocks and performing compression encoding, and a predetermined encoding signal output from the compression encoding means. And a signal inverting means for inverting and non-inverting alternately on a sample point basis or on a predetermined block basis.

[0008]

When the correlation between the coded signals of the adjacent sample points after compression coding remains, the bit balance of "1" and "0" of the coded signals of the adjacent sample points becomes similar. The same can be said when the correlation between the coded signals of the adjacent blocks after compression coding remains. In the present invention, since the encoded signal after compression encoding is alternately inverted and non-inverted in units of predetermined sample points or units of predetermined blocks, it is possible to reduce the ratio of the DC component, and to perform compression encoding and channel code. It becomes possible to deal with the conversion in a unified manner.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will now be described with reference to the drawings
Examples will be described. In this example, the compression encoding is A
This is an example in which DRC encoding is applied. The ADRC encoding method is disclosed in JP-A-61-144989 and JP-A-61-11-1.
It is well known in Japanese Patent Publication No. 47689.

The basic principle of ADRC encoding will be described with reference to FIG. For example, when a television signal is quantized with 8 bits, the signal level changes from 0 to 255, but one screen is divided into small blocks composed of V lines × H pixels as shown in FIG. In many cases, the pixel levels in a block are very close to each other due to the strong correlation of images. Therefore, by detecting the maximum value and the minimum value in the block and defining the local dynamic range of the block which is the difference between them, the redundancy in the level direction is removed, and each pixel in the block is requantized. It is possible to significantly reduce the number of bits required for. Here, it should be noted that some image correlation remains in the coded codes of the requantized adjacent pixels.

FIG. 1 shows the coding block of the first embodiment. In the figure, 11 is an input terminal, and the television signal Vin supplied to this input terminal 11 is A /
The data is quantized by the D converter 12 with, for example, 1 sample of 8 bits, and then supplied to the blocking circuit 13. The blocking circuit 13 converts each two-dimensional block, which is a unit of coding, into a continuous signal. For example, one block has a size of 4 lines × 4 pixels.

The pixel data output from the blocking circuit 13 is supplied to the maximum / minimum value detection circuit 14. The detection circuit 14 has a minimum value MIN and a maximum value MA for each block.
X is detected. Then, the minimum value MIN and the maximum value MAX output from the detection circuit 14 are supplied to the subtraction circuit 15, and the subtraction circuit 15 obtains the dynamic range DR (MAX-MIN) for each block.

Further, the pixel data output from the blocking circuit 13 has the minimum value MI as described above in the delay circuit 16.
After being delayed by the time required to detect N, the maximum value MAX, the signal is supplied to the subtraction circuit 17. In the subtraction circuit 17, the minimum value M output from the detection circuit 14 from the pixel data
IN is subtracted, and the 8-bit data DTI after the minimum value removal output from the subtraction circuit 17 is supplied to the encoder 18. In the encoder 18, the number of quantization bits is determined according to the dynamic range DR output from the subtraction circuit 15, and the data DTI is requantized with the determined number of quantization bits (1 bit to 8 bits). An encoding code (requantization code) DT is obtained for each pixel.

The dynamic range DR output from the subtraction circuit 15 and the minimum value M output from the detection circuit 14
IN constitutes additional data for each block. These dynamic range DR and minimum value MIN
Is directly supplied to the selection circuit 19 and the inverting circuit 20.
The inverted value DR bar and MIN bar are supplied to the selection circuit 19 and then supplied to the selection circuit 19. In the selection circuit 19, the non-inverted values DR and MIN and the inverted values DR bar and MIN bar are alternately selected for each block and led to the output terminals 21 and 22, respectively.

The coded code DT for each pixel output from the encoder 18 is directly supplied to the selection circuit 23, and is also supplied to the selection circuit 23 after being converted into the inverted value DT bar by the inversion circuit 24. In the selection circuit 23, the non-inverted value DT and the inverted value DT bar are alternately selected for each pixel and led to the output terminal 25.

The data obtained at the output terminals 21, 22, 25 is transmitted for each block via a buffer memory (not shown). FIG. 3 shows an example of a transmission format when a block of 4 lines × 4 pixels is set, for example. In the figure, DR ₁ is a non-inverted value of the dynamic range DR, and DR ₂ bar is the dynamic range DR.
Shows the inverted value of. MIN ₁ is the minimum value MIN
, The non-inverted value of MIN ₂ bar indicates the inverted value of the minimum value MIN. Further, X ₁₁ , X ₁₃ , ... Show non-inverted values of the encoded code DT, and X ₁₂ bar, X ₁₄ bar, ... Show inverted values of the encoded code DT.

FIG. 2 shows the decoding block of the first embodiment. In the figure, input terminals 31, 32 and 3
Data DR / DR bar, MIN / MIN bar and DT / DT bar transmitted from the coding block side of the example of FIG. 1 are respectively supplied to 3. The data DR / DR bar and MIN / MIN bar supplied to the input terminals 31 and 32 are directly supplied to the selection circuit 34 and the inverting circuit 35.
The inverted values DR bar / DR and MIN bar / MIN are supplied to the selection circuit 34. In the selection circuit 34, only the non-inverted value is selected for each block, and the dynamic range DR and the minimum value MIN for each block are obtained.

Further, the data D supplied to the input terminal 33
The T / DT bar is directly supplied to the selection circuit 36, and
The inverted value DT bar / DT is obtained by the inversion circuit 37 and then supplied to the selection circuit 36. In the selection circuit 36, only the non-inverted value is selected for each pixel, and the coding circuit DT for each pixel is obtained from the selection circuit 36.

The coded code DT for each pixel output from the selection circuit 36 is supplied to the decoder 38. Decoder 3
In 8, the dequantization is performed according to the dynamic range DR output from the selection circuit 34, and 8-bit data DTI after removal of the minimum value is obtained. The data DTI output from the decoder 38 is supplied to the adder circuit 39. In this addition circuit 39, the minimum value MIN output from the selection circuit 34 is added to the data DTI to restore the original pixel data.

The pixel data output from the adder circuit 39 is supplied to the block decomposition circuit 40, converted into the original TV signal series, and then converted into an analog signal by the D / A converter 41, and is output to the television at the output terminal 42. The signal Vout is derived.

As described above, in the coded block of this example, the coded code DT for each pixel is inverted every other pixel, and the additional data DR, MIN for each block is inverted every other block. The ratio of components can be reduced, and compression coding and channel coding can be handled in a unified manner. As a result, it is possible to obtain benefits such as reduction in hardware scale including the decoding block and cost reduction.

In the above embodiment, the additional data for each block is the dynamic range DR and the minimum value MIN, but the dynamic range DR and the maximum value MAX, or the minimum value MIN and the maximum value MAX is the additional data. Can be similarly configured.

In the above embodiment, ADRC coding is applied as compression coding, but a case where other compression coding is applied will be considered. For example, DCT,
In the case of transform coding such as the wavelet transform, correlation does not remain between each coefficient after transformation, but when viewed between blocks, correlation often remains between corresponding coefficients. Therefore, in the case of applying transform coding such as DCT (Discrete Cosine Transform) or wavelet transform as compression coding, the coefficient of the transform is inverted every other block to reduce the ratio of the DC component. It is possible to handle compression coding and channel coding in a unified manner.

FIG. 5 shows a coding block according to the second embodiment of the present invention. This example uses DCT as compression encoding.
It is an example to which encoding is applied. In the figure, 51 is an input terminal, and the television signal Vin supplied to this input terminal 51 is quantized by an A / D converter 52 and then supplied to a blocking circuit 53. In the blocking circuit 53, each two-dimensional block which is a unit of coding is converted into a continuous signal.

The pixel data output from the blocking circuit 53 is supplied to the DCT conversion circuit 54. The DCT conversion circuit 54 performs DCT conversion processing for each block, and the number of coefficient data corresponding to the block size is obtained from this DCT conversion circuit 54. The coefficient data for each block output from the DCT conversion circuit 54 is quantized by a quantization circuit 55.
And requantized to obtain a coded code (requantized code) DQ for each pixel.

The coded code DQ for each pixel output from the quantizing circuit 55 is directly supplied to the selecting circuit 56, and after being converted into an inverted value DQ bar by the inverting circuit 57, is supplied to the selecting circuit 56. In the selection circuit 56, the non-inverted value DQ and the inverted value DQ bar are alternately selected for each block and led to the output terminal 58. The data DQ / DQ bar obtained at the output terminal 58 is transmitted for each block via a buffer memory (not shown).

FIG. 6 shows the decoding block of the second embodiment. In the figure, the data DQ / DQ bar transmitted from the coding block side of the example of FIG. 5 is supplied to the input terminal 61. Data DQ / supplied to the input terminal 61
The DQ bar is directly supplied to the selection circuit 62, and is also supplied to the selection circuit 62 after being made the inverted value DQ bar / DQ by the inversion circuit 63. In the selection circuit 62, only the non-inverted value is selected for each block, and the coded code DQ for each pixel is obtained from this selection circuit 62.

The coded code DQ for each pixel output from the selection circuit 62 is supplied to the dequantization circuit 64 and dequantized to obtain coefficient data. The coefficient data output from the inverse quantization circuit 64 is supplied to the inverse DCT conversion circuit 65 and subjected to inverse DCT conversion to restore the original pixel data. The pixel data output from the inverse DCT conversion circuit 65 is supplied to the block decomposition circuit 66, converted into the original TV signal sequence, and then converted into an analog signal by the D / A converter 67, and is output to the television 68 at the output terminal 68. The signal Vout is derived.

In this way, in the coding block of this example, the coding code DQ for each pixel is inverted every other block, so that the ratio of the DC component can be reduced, and compression coding and channel coding can be performed. Can be handled in a unified manner, and benefits such as reduction in hardware scale and cost reduction can be obtained.

In the above embodiment, the example of inverting each pixel or each block has been shown, but two pixels, three pixels, ... Or two blocks, three blocks, ...・ You may invert with.
However, if there is no correlation between adjacent units, it is not possible to obtain the effects of the above-described embodiment.

Further, in the above-mentioned embodiment, the example in which the television signal is coded has been shown, but it goes without saying that the same can be applied to the coding of the audio signal.

[0032]

According to the present invention, since the encoded signal after compression encoding is alternately inverted and non-inverted in units of predetermined sample points or units of predetermined blocks, it is possible to reduce the proportion of DC components. The compression coding and the channel coding can be handled in a unified manner, and effects such as reduction in hardware scale and cost reduction can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a coding block according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a decoding block according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of a transmission format of the first embodiment.

FIG. 4 is a diagram for explaining the basic principle of ADRC encoding.

FIG. 5 is a block diagram showing an encoding block according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a decoding block of a second embodiment of the present invention.

FIG. 7 is a block diagram for explaining a general encoding method.

[Explanation of symbols]

 11, 31-33, 51, 61 Input terminal 12, 52 A / D converter 13, 53 Blocking circuit 14 Maximum value / minimum value detection circuit 15, 17 Subtraction circuit 16 Delay circuit 18 Encoder 19, 23, 34, 36 , 56, 62 Selection circuit 20, 24, 35, 37, 57, 63 Inversion circuit 21, 22, 25, 42, 58, 68 Output terminal 38 Decoder 39 Adder circuit 40, 66 Block decomposition circuit 41, 67 D / A conversion Device 54 DCT conversion circuit 55 Quantization circuit 64 Inverse quantization circuit 65 Inverse DCT conversion circuit

Claims (2)

[Claims] 1. A compression encoding means for converting an input digital signal into blocks to perform compression encoding, and an encoded signal output from the compression encoding means are alternately inverted and non-inverted in a unit of a predetermined sample point or in a unit of a predetermined block. An encoding device comprising: a signal inverting means for inverting. 2. The compression encoding is ADRC encoding, and the signal inversion means inverts the encoded code for each sample point every other sample point and inverts the additional data for each block every other block. The encoding device according to claim 1, wherein