JPH0423824B2 - - Google Patents
Info
- Publication number
- JPH0423824B2 JPH0423824B2 JP12323083A JP12323083A JPH0423824B2 JP H0423824 B2 JPH0423824 B2 JP H0423824B2 JP 12323083 A JP12323083 A JP 12323083A JP 12323083 A JP12323083 A JP 12323083A JP H0423824 B2 JPH0423824 B2 JP H0423824B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- resist film
- tungsten
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 16
- 229910052721 tungsten Inorganic materials 0.000 claims description 16
- 239000010937 tungsten Substances 0.000 claims description 16
- 238000010894 electron beam technology Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910001385 heavy metal Inorganic materials 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 4
- 239000004926 polymethyl methacrylate Substances 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 but in reality Chemical compound 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electron Beam Exposure (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体集積回路の配線層上にコンタク
トホールを自己整合的に形成する方法に係り、特
にタングステン等の重金属を用いた配線層上に電
子ビーム描画法でコンタクトホールを形成するの
に好適な半導体装置の製造方法に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method of forming contact holes in a self-aligned manner on a wiring layer of a semiconductor integrated circuit, and in particular to a method of forming contact holes in a wiring layer using heavy metals such as tungsten. The present invention relates to a method of manufacturing a semiconductor device suitable for forming contact holes using a beam writing method.
従来、半導体装置特にMOSデバイスを用いた
集積回路素子の能動層を形成するゲート配線では
そのゲート配線直下のゲート配化膜が非常に薄い
ために、能動層上又は能動層に近い部分で該ゲー
ト配線上に電気的導通を得るためのコンタクトホ
ールを形成することは、コンタクトホール形成時
の重ね合せずれ等により、ゲート配線下の酸化膜
を破損しやすいため、避けられていた。このた
め、コンタクトホールは能動層から離れた厚い酸
化膜上に形成せざるを得ないため、配線層パター
ンの微細化が制限されるという欠点があつた。
Conventionally, in a gate wiring forming an active layer of a semiconductor device, especially an integrated circuit element using a MOS device, the gate wiring film directly under the gate wiring is very thin, so that the gate is formed on the active layer or near the active layer. Forming a contact hole for obtaining electrical continuity on the wiring has been avoided because the oxide film under the gate wiring is likely to be damaged due to misalignment when forming the contact hole. For this reason, the contact hole has to be formed on a thick oxide film away from the active layer, which has the disadvantage that miniaturization of the wiring layer pattern is restricted.
本発明の目的は前述したゲート配線上のコンタ
クトホール形成上の制限をなくし、能動層上でも
ゲート酸化膜を破損することなく、コンタクトホ
ールを形成することのできる半導体装置の製造方
法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device, which eliminates the above-mentioned restrictions on the formation of contact holes on gate wiring, and can form contact holes even on active layers without damaging the gate oxide film. It is in.
MOSLSIの高性能化、高集積化に伴い、その
ゲート寸法は年々微細化されている。従来このゲ
ート配線はpoly Siが使われていた。しかしゲー
ト長の微細化に伴いゲートの抵抗が素子の応答速
度を律するようになつて来た。このため、ゲート
配線の低抵抗化が検討されており、タングステ
ン、モリブデン又はこれらのシリサイドが、ゲー
ト配線として着目されている。一方ゲート長等素
子の微細化は従来の光学的な転写法から、より微
細なパターンの加工が可能な電子線描画法が使わ
れるようになつて来ている。電子線描画では、加
工しようとする半導体基板上に被着した電子線レ
ジストに入射した電子と該電子線レジストを透過
して基板に到達した電子の一部が基板より反射し
た、いわゆる後方散乱電子の総和が電子線レジス
トの化学変化に寄与する。電子線を物質に入射さ
せた時の反射電子はJouynal of Applied
Physics誌32巻８号1505頁G.D.Archard著の文献
等から明らかなように、重元素程大きい。例えば
Siでは入射した電子の15％程度しか反射しないの
に対し、タングステンでは50％近く反射する。従
つて、タングステンのような重金属又は重金属と
Siの合金で形成された配線上では、通常のSi基板
上で電子線レジスト中に化学変化を起させるより
少い電子線照射量で同様の化学変化を起させるこ
とができる。これを第１図で詳しく説明する。Si
基板上で従来より測定されているPMMAレジス
トの残膜特性を図に示す。この場合Si基板からの
電子の反射は10〜15％である。一方タングステン
上では電子の反射は50％であるため、タングステ
ン上では実効的に30〜40％感度が向上する。この
場合の残膜特性を第１図に示す。すなわちSi基板
上では70μc／cm2程度必要であつた照射量が、タ
ングステン上では50μc／cm2となる。従つて
50μc／cm2の電子線照射ではタングステン上の
PMMAのみ残膜が０となり、Si基板上では塗布
膜に対し44％のPMMAが残ることになる。ここ
で記述した例ではSi基板とタングステン上で同一
の膜厚が塗布されているとしたが、実際にはSi基
板上の一部にタングステンが加工されて被着して
いることが多く、この場合タングステンの膜厚だ
けレジスト膜厚が薄くなる。このため膜厚が薄く
なつた分だけさらに残膜特性は高感度側にシフト
し、レジスト膜厚の半分の膜厚のタングステンが
ついた場合の例を第１図に示してある。従つてこ
の場合は更に低照射量、30μc／cm2程度の電子線
照射でタングステン上のPMMAが除去され、Si
基板上には塗布膜厚の83％が残ることになる。
As MOSLSIs become more sophisticated and highly integrated, their gate dimensions are becoming smaller year by year. Conventionally, polySi was used for this gate wiring. However, with the miniaturization of gate length, the resistance of the gate has come to control the response speed of the element. For this reason, efforts are being made to reduce the resistance of gate wiring, and tungsten, molybdenum, or their silicides are attracting attention as gate wiring. On the other hand, for miniaturization of elements such as gate length, the conventional optical transfer method is being replaced by an electron beam lithography method that can process finer patterns. In electron beam lithography, electrons that are incident on an electron beam resist deposited on a semiconductor substrate to be processed and some of the electrons that have passed through the electron beam resist and reached the substrate are reflected from the substrate, so-called backscattered electrons. The sum of these contributes to chemical changes in the electron beam resist. The reflected electrons when an electron beam is incident on a material are Jouynal of Applied
As is clear from the literature by GDArchard, Physics magazine, Vol. 32, No. 8, p. 1505, the heavier the element, the larger it is. for example
Si reflects only about 15% of incident electrons, while tungsten reflects nearly 50%. Therefore, heavy metals such as tungsten or
A similar chemical change can be caused on a wiring made of a Si alloy with a smaller amount of electron beam irradiation than the chemical change that is caused in an electron beam resist on a normal Si substrate. This will be explained in detail with reference to FIG. Si
The figure shows the residual film characteristics of PMMA resist that have been conventionally measured on substrates. In this case, the reflection of electrons from the Si substrate is 10-15%. On the other hand, since 50% of electrons are reflected on tungsten, the sensitivity is effectively improved by 30 to 40% on tungsten. The residual film characteristics in this case are shown in FIG. That is, the amount of irradiation that was required on the Si substrate was about 70 μc/cm 2 but on tungsten it was 50 μc/cm 2 . Accordingly
Electron beam irradiation at 50μc/ cm2
Only PMMA had a residual film of 0, and on the Si substrate, 44% of the PMMA remained relative to the coated film. In the example described here, it is assumed that the same film thickness is applied on the Si substrate and tungsten, but in reality, tungsten is often processed and deposited on a part of the Si substrate, so this In this case, the resist film thickness becomes thinner by the thickness of the tungsten film. For this reason, as the film thickness becomes thinner, the remaining film characteristics further shift to the high sensitivity side, and FIG. 1 shows an example in which tungsten is deposited with a film thickness that is half the resist film thickness. Therefore, in this case, the PMMA on the tungsten is removed by electron beam irradiation at an even lower dose of about 30μc/ cm2 , and the Si
83% of the coating film thickness remains on the substrate.
以下、本発明の一実施例を第２図により説明す
る。本実施例ではMOSメモリのメモリセル部に
応用した場合を示す。第２図はメモリセル部レイ
アウトの一部および、ゲート部の断面構造を示
す。ここでゲート金属３としてはタングステン
3500Åを用い、ゲート３上に層間絶縁膜７として
PSG膜を4000Å被着してある。ａでは上記構造
上にポジ型電子線レジストRE5000P（日立化成商
品名）８を1.2μm塗布した状態を示す。ここに電
子線を30KVの加速電圧で4μc／cm2全面に照射す
る。しかる後に同レジストをNMD−３（東京応
化商品名）で２分間現像する。
An embodiment of the present invention will be described below with reference to FIG. This embodiment shows a case where the present invention is applied to a memory cell portion of a MOS memory. FIG. 2 shows a part of the layout of the memory cell section and the cross-sectional structure of the gate section. Here, the gate metal 3 is tungsten.
3500 Å as interlayer insulating film 7 on gate 3.
A PSG film of 4000Å is deposited. Figure a shows a state in which a positive electron beam resist RE5000P (trade name of Hitachi Chemical) 8 is applied to a thickness of 1.2 μm on the above structure. Here, the entire surface is irradiated with an electron beam at 4 μc/cm 2 at an accelerating voltage of 30 KV. Thereafter, the resist was developed with NMD-3 (trade name of Tokyo Ohka Chemical Co., Ltd.) for 2 minutes.
この結果同図ｂに示すようにタングステン上の
RE5000Pは膜厚が０となり他の部分９は5000Å
程度の残膜があつた。ついで該レジストをマスク
としてPSG膜７をCF4＋H2ガスによりドライエ
ツチし、レジストを除去した場合を同図ｃに示
す。 As a result, as shown in figure b,
RE5000P has a film thickness of 0 and the other part 9 is 5000Å
There was some residual film. Then, using the resist as a mask, the PSG film 7 is dry-etched with CF 4 +H 2 gas, and the resist is removed, as shown in FIG.
この結果、タングステン上へのコンタクトホー
ルは全くパターンを用意する必要がないか又は重
ね合せ余裕を全く考慮する必要がなくなつた。一
方本技術により第３図に示す如く、従来必要であ
つた広いコンタクト穴領域が不要となり、セル面
積を50％に減らすことが可能となつた。 As a result, there is no need to prepare any pattern for contact holes on tungsten, or there is no need to consider overlapping margins at all. On the other hand, as shown in FIG. 3, the present technology eliminates the need for a wide contact hole area that was conventionally necessary, making it possible to reduce the cell area by 50%.
本発明によれば下地に形成した重金属層上に選
択的にレジスト開孔部を設けることができるため
重ね合せ余裕を考慮必要がないことや、コンタク
ト層を全面照射に置き換えられる等の利点ばかり
でなく従来必要であつた広いコンタクト穴領域を
不要にできるため、大幅なパターンの縮小、集積
度の増大が可能になる等の効果がある。
According to the present invention, resist openings can be selectively formed on the heavy metal layer formed as the base, so there are many advantages such as there is no need to consider overlay margin and the contact layer can be replaced with full-surface irradiation. This eliminates the need for a wide contact hole area, which was conventionally required, and has effects such as a significant reduction in pattern size and an increase in the degree of integration.
第１図はポジ型電子線レジストの感度特性を示
す曲線図、第２図は本発明法によるレイアウトパ
ターンと各工程の断面を示す図、第３図は発明に
よつて形成されたメモリセルレイアウト図の一例
と従来法によつて形成したときのレイアウトを比
較した図である。
１……アイソレーシヨン領域、２……ポリシリ
コン領域、３……タングステンゲート、４……Si
基板、５……フイールド酸化膜、６……ゲート酸
化膜、７……PSG膜、８……塗布後のレジスト
膜、９……現像後のレジスト膜、１０……レジス
ト開孔部、１１……PSG開孔部、１２……Al配
線。
Fig. 1 is a curve diagram showing the sensitivity characteristics of a positive electron beam resist, Fig. 2 is a diagram showing a layout pattern and cross-sections of each process according to the method of the present invention, and Fig. 3 is a memory cell layout formed by the invention. FIG. 3 is a diagram comparing an example of the diagram with a layout formed by a conventional method. 1...Isolation region, 2...Polysilicon region, 3...Tungsten gate, 4...Si
Substrate, 5... Field oxide film, 6... Gate oxide film, 7... PSG film, 8... Resist film after coating, 9... Resist film after development, 10... Resist opening, 11... ...PSG opening, 12...Al wiring.
Claims (1)
体からなる所定の形状を有する電極を形成する工
程と、少なくとも該電極上に絶縁膜を形成する工
程と、電子線に感度を有するポジ型レジスト膜を
該絶縁膜上に塗布する工程と、該電極上の該レジ
スト膜は化学変化を起し、該電極上以外の領域の
該レジスト膜は化学変化を起さない量の電子線を
少なくとも該電極上の所定の領域上の該レジスト
膜に照射する工程と、該レジスト膜を現像処理す
ることにより、該電子線が照射された該電極上の
該レジスト膜に開口部を形成して該絶縁膜を露出
する工程と、露出された該絶縁膜をエツチングし
て該電極を露出する工程とを含む半導体装置の製
造方法。 ２ 上記重金属は、タングステン又はモリブデン
であることを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。 ３ 上記重金属を含む導体は、タングステンシリ
サイド又はモリブデンシリサイドであることを特
徴とする特許請求の範囲第１項乃至第２項に記載
の半導体装置の製造方法。[Claims] 1. A step of forming an electrode having a predetermined shape made of a heavy metal or a conductor containing the heavy metal on a semiconductor substrate, a step of forming an insulating film at least on the electrode, and a step of making the electrode sensitive to electron beams. A step of applying a positive resist film on the insulating film, the resist film on the electrode undergoes a chemical change, and the resist film in an area other than the electrode receives an amount of electrons that does not cause a chemical change. forming an opening in the resist film on the electrode irradiated with the electron beam by irradiating the resist film on at least a predetermined region on the electrode with a beam, and developing the resist film; A method for manufacturing a semiconductor device, comprising: exposing the insulating film; and etching the exposed insulating film to expose the electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the heavy metal is tungsten or molybdenum. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the conductor containing the heavy metal is tungsten silicide or molybdenum silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12323083A JPS6015920A (en) | 1983-07-08 | 1983-07-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12323083A JPS6015920A (en) | 1983-07-08 | 1983-07-08 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6015920A JPS6015920A (en) | 1985-01-26 |
| JPH0423824B2 true JPH0423824B2 (en) | 1992-04-23 |
Family
ID=14855417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12323083A Granted JPS6015920A (en) | 1983-07-08 | 1983-07-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6015920A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100296126B1 (en) | 1998-12-22 | 2001-08-07 | 박종섭 | Gate electrode formation method of highly integrated memory device |
| KR100299386B1 (en) | 1998-12-28 | 2001-11-02 | 박종섭 | Gate electrode formation method of semiconductor device |
| JP3988342B2 (en) | 1998-12-29 | 2007-10-10 | 株式会社ハイニックスセミコンダクター | Method for forming gate electrode of semiconductor element |
-
1983
- 1983-07-08 JP JP12323083A patent/JPS6015920A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6015920A (en) | 1985-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20050040491A1 (en) | Fuse stucture | |
| JP3520114B2 (en) | Method for manufacturing semiconductor device | |
| JPH11330245A (en) | Method for contact formation of semiconductor device | |
| US6072242A (en) | Contact structure of semiconductor memory device for reducing contact related defect and contact resistance and method for forming the same | |
| US4487795A (en) | Method of forming patterned conductor lines | |
| JP3397663B2 (en) | Circuit element manufacturing method | |
| JPH0423824B2 (en) | ||
| JPH03180041A (en) | Semiconductor device | |
| US5945739A (en) | Semiconductor device having a conductor through an inter-level layer and a spin-on-glass in the inter-level layer with substantially planar upper surfaces of the conductor, the inter-level layer, and the spin-on-glass | |
| JP2765133B2 (en) | Method for manufacturing semiconductor device | |
| US6001743A (en) | Method for fabricating a self-aligned contact | |
| US6068964A (en) | Method for patterning an insulator film and installing a grounding pin through electron beam irradiation | |
| JP3034538B2 (en) | Method of forming wiring structure | |
| JPH08330249A (en) | Manufacture of semiconductor device | |
| JP3165693B2 (en) | Stacked capacitor type DRAM | |
| JP3180333B2 (en) | Method for manufacturing semiconductor memory device | |
| JP2738693B2 (en) | Fine pattern forming method | |
| KR0155787B1 (en) | Formation method of contact hole in semiconductor device | |
| JP3395720B2 (en) | Mask structure of semiconductor memory device and method of manufacturing semiconductor memory device | |
| JP2750164B2 (en) | Method of forming memory cell pattern | |
| JP3048919B2 (en) | How to form wiring patterns | |
| KR100372657B1 (en) | Method for forming contact of semiconductor device | |
| JPH0845811A (en) | Formation of pattern and manufacture of semiconductor integrated circuit device using formation of pattern | |
| JPS59163838A (en) | Manufacture of semiconductor device | |
| JPS59181647A (en) | Manufacture of semiconductor device |