JPH0423649A - Discrimination signal generating circuit - Google Patents

Abstract

PURPOSE:To reduce the time for signal interruption for a demodulator by applying A/D conversion to each base band signal of P and Q channels in orthogonal relation and outputting a valid area discrimination signal when an outside of outermost shell signal point and four corners in a signal point arrangement on a phase plane is represented. CONSTITUTION:Six-value signals being P and Q channel input base band signals are converted into 4-bit binary digital signals comprising 3-bit data signals D1, D2, D3 and a 1-bit error signal El according to the conversion rule and outputted to a valid area discrimination circuit 13. Then the valid area discrimination circuit 13 detects logic state of digital signals D1P-D3P, E1P, and D1Q-D3Q, E1Q at the outside of the sampling point, brings its output signal to logical 1 when the logic state represents the position at the outside of an outer circumference line of an outermost signal position, brings it to logical 0 when the logic state indicates a void part where 32 signal points exist in other cases and outputs logical 1 or 0 signal to an output terminal 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a determination signal generation circuit in a digital wireless communication system, and particularly to a 32-value quadrature amplitude modulation (hereinafter referred to as 32Q
The present invention relates to a determination signal generation circuit that determines whether or not a demodulated signal point position is in a valid region in a demodulation device that employs an AM method.

[Conventional technology]

In recent years, in order to increase the efficiency of use of radio frequency bands in digital wireless communication systems, multilevel quadrature amplitude modulation methods have been promoted, and 32QAM methods have already been put into practical use.

The signal point arrangement of the conventional 32QAM system has six signal points of +1 to +3 and -1 to -3 on both sides of the P axis and Q axis, respectively, as shown in Figure 7, which shows a general signal point arrangement. have. This ideal position of the signal point causes an error representing a deviation from the ideal position due to distortion generated in the circuit of the demodulator and propagation distortion due to fading and the like occurring in the propagation path. In order to correct the above-mentioned distortion, a transversal equalizer is usually used, and a tap control signal for the transversal equalizer is generated based on an error signal representing the deviation from the ideal position. It has become

Now, the method for determining the error signal of each signal point will be explained by focusing on two signal points A and B at ideal positions shown in FIG.

As shown in Figure 8, the error signal is expressed as "1" for deviations from the ideal value of each signal point in the upward and outward directions, and as "0" for deviations in the downward and inward directions. However, if the signal that should originally be received at signal point position B is received at point The signal becomes "0", which is within the error range of signal point A. That is, this error signal (
At point X), it is mistakenly recognized that the signal that should be received at signal point position A has been received with a downward shift, resulting in an incorrect error signal. If the transversal equalizer is controlled by a control signal generated based on this erroneous error signal, the entire demodulation system including the transversal equalizer will diverge, so in such a case, Conventionally, each control signal is once reset to its initial value, and during the reset period, the operation of each control signal generating circuit is stopped.

The method for determining the error signal of signal points A and H described above is described in the seventh
This is applied to all signal points of the 32QAM system shown in the figure.

Therefore, the shift of the signal point in the outermost shell of the signal points is the 7th
Even if an error signal point was received in the shaded area in the diagram, an error signal of "1" representing an outward shift was output and a reset was applied.

[Problem to be solved by the invention]

The conventional determination signal generation circuit described above is reset even when the error signal point of the outermost signal point in the 32QAM system is located outside the diagonal line in FIG. 7, so during the reset period, the transversal system, etc. There is a drawback that the equalization operation of the equalizer is stopped. Therefore, once loss of synchronization occurs due to fading or the like, the demodulation system remains in a signal-off state until the fading distortion is sufficiently reduced.

[Means to solve the problem]

The determination signal generation circuit of the present invention detects P channel and Q channel baseband signals having an orthogonal relationship in the determination signal generation circuit that determines the error signal position of the signal point position of a demodulator using the 32-value orthogonal amplitude modulation method. An A-D converter that inputs and outputs a 4-bit binary digital signal consisting of 3 data bits and 1 error bit, and an error signal point of the outermost signal point among 32 signal points. effective area determining means for outputting a determination signal when the signal exists in an effective area that is an outer area of an outer peripheral line connecting arrangement points of the outermost shell signal points, and when the determination signal is output, the demodulating Do not reset the transversal equalizer included in the device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The embodiment shown in FIG. 1 includes an A/D converter 11. which converts a P channel baseband signal at an input terminal 1 into a digital signal. Input terminal 2
an A/D converter 12 that converts the Q-channel baseband signal of the A/D converter 11. ．． Input terminal for inputting a clock signal 3. The information is refined from a storage circuit 14 formed of a ROM that stores information that serves as a criterion for the valid area determination circuit 13. As a further supplement, the P channel and Q channel multilevel baseband signals, which are orthogonal to each other, obtained by a demodulator (not shown) are sent to the A/D converter 11.12 via the input terminal 1.2, respectively. is input.

Further, the clock signal applied to the input terminal 3 is given as a clock for determining the identification timing, etc. of the A/D converters 11 and 12 and the effective area determination circuit 13. Further, the ROM of the storage circuit 14 uses the logic state at the sampling point position of each output digital signal of the A/D converters 11 and 12 as address information, and this ROM contains the address information and the signal point arrangement. A table is stored in advance to associate the information.

Next, the operation of each circuit will be explained. A/D converter 11.12
As shown in the explanatory diagram of FIG. 2, 6-value signals of input signals P-channel and Q-channel baseband signals are converted into 3-bit data signals DI, D2 . It is converted into a 4-bit binary digital signal consisting of D3 and the 1-bit error signal E1, and output to the valid area determination circuit 13.

As shown in FIG. 1, the output signals of the A/D converter 11 are 3-bit data signals Dzp, D2p, D3p and 1-bit error signals E and P.
The output signal is a 3-bit data signal D IQI D 2
This results in QI D 3cs and a 1-bit error signal Elq.

Next, the operation of the valid area determination circuit 13 is based on digital signals P to D, P, E□2 and DIQ to D5. , E□9 is detected, and when the logic state indicates the shaded area outside the outer circumferential line of the outermost signal point position in the signal point arrangement shown in FIG. 7, the output signal is " 1
In other cases, if it is a white area with 32 signal points, it will be "O" binding, and the "1" or "0" signal will be output to the output terminal 4.
Output to. The shaded area will be referred to as an effective area, and the white area will be referred to as an invalid area. Furthermore, this operating principle can be explained in a third way.
This will be explained with reference to the explanatory diagram of the figure. In Fig. 3, if the signal point position C is the outermost signal point position, and if a signal is actually received at a position Y outside of this signal point position C, the signal point arrangement will not be included in the information of the signal point position C. Since it does not exist, position Y
It can be said that there is an extremely high probability that the signal received at the signal point position C that should have been received at the closest signal point position C was received with a shift. In other words, the error signal EIP or EIQ for the received signal at position Y is "1", which can be said to provide a correct error signal.

Further, a case where the outermost signal points are located at the four corners (sections A1-A4 in FIG. 7) will be described with reference to FIG. 4. If a signal point is received at position H in area Z, then the distance from the outermost signal point E to position H! Since j is shorter than the distance m from the internal signal point G to the position H, it can be said that the probability that the signal to be received at the signal point position E is received with a shift is extremely high. In other words, in Fig. 4, the area Z
If a signal is received in the area, it is much more likely that the outermost signal point E or signal point F is shifted than the internal signal point G is shifted. The error signal can be judged to be correct.

Next, the ROM, which is the storage circuit 14, stores information that is the criterion for valid area determination circuit 13 as described above, and the setting procedure for this information table is shown in FIGS.
, (c) showing the relationship between the signal point arrangement and the effective area in the first quadrant, and the explanatory diagram of the memory contents of the ROM in FIG. 6.

Considering the first quadrant in FIG. 5, it can be divided into three regions. In other words, in FIG. 5(a) of the first region, Q
The value of the signal level on the axis is 3 or more (D2-=1,
E1-=1). Figure 5(b) of the second area
, the value of the signal level on the P axis is 3 or more (D 2P = 1
, E tp = 1). FIG. 5(c) in the third region shows that the signal level on the Q axis is 2.5 or more (D2-
=1. D3q=O, Et-=O), and the signal level on the P axis is 2.5 or more (D2P=1, D3PO
, Etp=O). In the memory contents of the ROM shown in Fig. 6, the "x" mark indicates that it can be either "0" or 1. Now, the input signals DIP to D 3P in Fig. 6,
The bit patterns of the 8-bit digital signals of E tp, D 1q to D3Q, and EIQ are shown in FIGS.
), the output signal S becomes "1", and a valid region determination signal can be generated. Then, only the data signal and error signal obtained when S=1 are generated. It is used as a probable signal for each control, and the data in the invalid area is treated as an error signal as before.

〔Effect of the invention〕

As explained above, the present invention performs A/D conversion on each of the mutually orthogonal P channel and Q channel baseband signals acquired in the demodulator, and converts the logic at the sampling point position of each digital signal. Since the valid area determination signal is output when the state indicates the outside and four corners of the outermost signal point position (shaded area in Figure 4) in the signal point arrangement on the phase plane, the demodulation system is prevented from losing synchronization. This has the effect of increasing the probability that a correct error signal can be quickly captured without resetting the transversal equalizer even if the transversal equalizer has occurred. Therefore, control systems such as transversal equalizers can be quickly converged.
This has the effect of shortening the signal interruption time of the demodulator.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of input signals and output signals of the A/D converter of this embodiment, and Figs. 3 and 4 are diagrams showing the effectiveness of this embodiment. Diagram explaining the principle of area determination, Part 5
Figures (a), (b), and (c) are explanatory diagrams showing the effective area in the first quadrant of this embodiment, Figure 6 is an explanatory diagram of the ROM of this embodiment, and Figure 7 is a general 32QAM system. FIG. 8 is an explanatory diagram of the operation of a conventional determination signal generation circuit. 1.2.3...Input terminal, 11.12...A/D converter, 13...Valid area determination circuit, 14...Storage circuit.

Claims (1)

[Claims] In a determination signal generation circuit for determining an error signal position of a signal point position of a demodulator using a 1-, 32-value orthogonal amplitude modulation method, P-channel and Q-channel baseband signals having an orthogonal relationship are each Input 3 data bits and 1
An A-D converter that outputs a 4-bit binary digital signal consisting of 32 error bits, and an error signal point of the outermost signal point among the 32 signal points connect the arrangement point of the outermost signal point. a transversal type equalizer included in the demodulator, the transversal type equalizer having a valid area determining means for outputting a determination signal when the signal exists in an effective area that is an outside area of the outer circumferential line; A determination signal generation circuit characterized in that it does not reset. 2. The 4 bits 2 to which the valid area determination means is input
2. The determination signal generation circuit according to claim 1, further comprising a storage circuit that stores a comparison table between address information of sample point positions of the value digital signal and the valid area divided into three areas.