JPH04236464A - Vacuum electron-wave interference transistor - Google Patents

Abstract

PURPOSE:To realize a vacuum electron-wave interference transistor which can be operated at room temperature and in which electrons are easily emitted from an emitter. CONSTITUTION:An extraction electrode 7 and a gate electrode 3 are formed between an emitter 1 and a collector 2. Electron waves are emitted into a vacuum from the emitter 1 and the electron waves are divided into the following: electron waves which are passed through the upper side of the gate electrode 3 and which reach the collector 2; and electron waves which are passed through the lower side of the gate electrode 3 and which reach the collector 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a vacuum electron wave interference transistor.

0002

[Background Art] With the recent progress in ultrafine structure fabrication technology, research on electronic wave interference devices that utilize the coherence of electron waves has been actively conducted.
onov)-Bohm effect (hereinafter referred to as "AB effect transistor") using an AlGaAs/GaAs double heterojunction has been proposed (for example, Techni
cal Digest of IEDM 86, pp.
．． 76-79). However, this conventional AB effect transistor requires cooling to an extremely low temperature below the liquid helium temperature (4.2 K) in order to maintain electron coherence, making it difficult to use easily. It is also disadvantageous in terms of cost.

In order to solve this problem, the present applicant proposed in Japanese Patent Application No. 2-173003 a vacuum AB effect transistor configured to allow electrons to travel in vacuum. In this vacuum AB effect transistor, by applying a sufficiently high voltage between the emitter and collector, electron waves are emitted from the emitter (cathode) into a vacuum. This electron wave is split by a blocker negatively biased with respect to the emitter into an electron wave passing through one side of the blocker and an electron wave passing through the other side of the blocker. These two electron waves then meet at the collector. Then, interference between these two electron waves at the collector is controlled by controlling the phase difference between these two electron waves using a gate electrode provided outside the path of electrons from the emitter to the collector. and performs transistor operation. This patent application Hei 2-
According to the vacuum AB effect transistor proposed in No. 173003, since it is configured so that electrons travel in a vacuum, unlike conventional AB effect transistors in which electrons travel in a semiconductor, electrons are not affected by temperature. Therefore, coherence can be maintained. This allows operation at temperatures much higher than liquid helium temperatures,
Operation at room temperature is also possible.

0004

However, in the vacuum AB effect transistor proposed in the above-mentioned Japanese Patent Application No. 2-173003, the blocker must be negatively biased with respect to the emitter, which is the source of electron emission. However, there was a problem in that the electric field near the tip of the emitter became weaker, making it difficult for electron emission itself to occur. Accordingly, an object of the present invention is to provide a vacuum electron wave interference transistor that can operate at room temperature and that emitters easily emit electrons.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention divides an electron wave emitted into a vacuum from an emitter (1) into a plurality of electron waves, and then divides the plurality of electron waves into a collector. (2), and the phase difference between a plurality of electron waves is controlled by a gate electrode (3), the emitter (1) and the gate electrode (3) An extraction electrode (7) is provided between them, and the extraction electrode (7) causes the emitter (1) to emit an electron wave and divides the electron wave into a plurality of electron waves.

[0006]

[Operation] According to the vacuum electron wave interference transistor of the present invention configured as described above, an extraction electrode is provided between the emitter and the gate electrode, and the extraction electrode allows the emitter to emit electron waves and emit electrons. Since the wave is divided into a plurality of electron waves, there is no need to provide a negatively biased blocker to the emitter as in the conventional method, and the problem of weakening the electric field near the tip of the emitter due to the blocker is eliminated. Therefore, electron emission from the emitter is likely to occur. Furthermore, since it is configured to allow electrons to travel in a vacuum, it can operate at room temperature.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view of a vacuum AB effect transistor according to an embodiment of the present invention, and FIG.
FIG. 2 is a sectional view taken along line 2-2 of FIG.

As shown in FIGS. 1 and 2, in the vacuum AB effect transistor according to this embodiment, a substrate (not shown), such as a semi-insulating GaAs substrate, has a pointed tip, for example, in the shape of a quadrangular pyramid. Square prism emitter 1
and a collector 2 are formed such that their tips face each other. Here, the central axes of the emitter 1 and collector 2 are on the same straight line. Further, these emitter 1 and collector 2 are formed of, for example, GaAs. An example of the cross-sectional dimensions of the emitter 1 and collector 2 is, for example, about 0.5 μm×0.5 μm. Reference numeral 3 indicates a gate electrode. This gate electrode 3 is supported by support parts (not shown) at both ends thereof, and has a floating structure in the part between them. In this case, the part of the gate electrode 3 between the emitter 1 and the collector 2 is perpendicular to the direction connecting the emitter 1 and the collector 2, but the parts on both sides are bent toward the collector 2. There is.

This gate electrode 3 includes, for example, an n-type GaAs layer 4, a semi-insulating GaAs layer 5, and an n-type GaAs layer 4, which are stacked on each other.
It has a parallel plate capacitor structure consisting of a type GaAs layer 6. In this case, these n-type GaAs layers 4 and n-type Ga
The As layer 6 constitutes an electrode. In addition, these n-type GaA
The s-layer 4, the semi-insulating GaAs layer 5, and the n-type GaAs layer 6 are parallel to the direction connecting the emitter 1 and the collector 2. An example of the width of the gate electrode 3 in the direction connecting the emitter 1 and the collector 2 is, for example, about 0.5 μm. In this embodiment, an extraction electrode 7 is formed between the emitter 1 and the gate electrode 3. In this case, the portion of the extraction electrode 7 between the emitter 1 and the collector 2 is perpendicular to the direction connecting the emitter 1 and the collector 2, and is therefore parallel to the gate electrode 3. , the parts on both sides thereof are bent toward the emitter 1 side. Also, emitter 1
and this extraction electrode 7 in the part between the collector 2
is divided into a lower extraction electrode 4a and an upper extraction electrode 4b, and a portion between the lower extraction electrode 4a and the upper extraction electrode 4b is open. An example of the width of the lower extraction electrode 4a and the upper extraction electrode 4b in the direction connecting the emitter 1 and the collector 2 is, for example, about 0.5 μm.

Next, the operation of the vacuum AB effect transistor according to this embodiment constructed as described above will be explained. In this vacuum AB effect transistor, a voltage is applied between the emitter 1 and the collector 2 so that the collector 2 has a higher potential. A voltage of sufficient magnitude to cause electrons to be emitted from the emitter 1 in an electric field is applied between the emitter 1 and the extraction electrode 7 such that the potential of the extraction electrode 7 is higher than that of the emitter 1 . That is, the extraction electrode 7
is positively biased with respect to emitter 1. As a result, an electron wave is emitted from the emitter 1, and this electron wave is transmitted by the lower extraction electrode 7a and the upper extraction electrode 7b, which are positively biased with respect to the emitter 1.
The collector 2 passes above the gate electrode 3 in FIGS. 1 and 2.
The electron waves are divided into those that reach the collector 2 through the lower side of the gate electrode 3. The phase difference between these two electron waves is determined by the difference in potentials V1 and V2 between the n-type GaAs layer 4 and the n-type GaAs layer 6, which are the electrodes of the parallel plate capacitor constituting the gate electrode 3. Therefore, the phase difference between these two electron waves is controlled by the difference between the potentials V1 and V2, and the interference between these two electron waves at the collector 2 is controlled. This modulates the quantum mechanical transition probability of electrons from the emitter 1 to the collector 2, causing the transistor to operate.

Next, a method of manufacturing the vacuum AB effect transistor according to this embodiment constructed as described above will be explained. Note that the following description will be made regarding a cross section taken along line 2-2 in FIG. As shown in FIG. 3A, first, for example, an n-type GaAs layer 12 having a shape corresponding to the extraction electrode 7 is formed on a semi-insulating GaAs substrate 11. This n-type Ga
The As layer 12 is formed by, for example, metal organic chemical vapor deposition (MOCV).
It is formed by epitaxially growing an n-type GaAs layer over the entire surface by method D) and then patterning this n-type GaAs layer by etching. Next, gate electrode 3
Then, a resist pattern 13 having an opening 13a in a portion corresponding to the extraction electrode 7 is formed by lithography. Thereafter, a SiO2 film 14, for example, is formed inside the opening 13a of the resist pattern 13. Next, after removing the resist pattern 13, as shown in FIG. 3B,
A resist pattern 15 having an opening 15a in a portion corresponding to the gate electrode 3 is formed. Next, by etching the SiO2 film 14 in a direction perpendicular to the substrate surface by, for example, reactive ion etching (RIE) using this resist pattern 15 as a mask, the SiO2 film 14 is partially etched as shown in FIG. 3C. to be removed. The upper surface of the SiO2 film 14 in this removed portion is made to be at the same height as the lower surface of the gate electrode 3.

Next, after removing the resist pattern 15, as shown in FIG. 3D, the n-type GaAs layer 4 and the semi-insulating G
An aAs layer 5 and an n-type GaAs layer 6 are epitaxially grown in sequence, and a SiO2 film 16, for example, is formed on the entire surface. Next, as shown in FIG. 3E, a resist pattern 17 having a shape corresponding to the gate electrode 3 is formed on the SiO2 film 16.
form. Next, by etching the SiO2 film 16 in a direction perpendicular to the substrate surface using the resist pattern 17 as a mask, the SiO2 film 16 is etched as shown in FIG. 3F.
Film 16 is partially removed. Next, after removing the resist pattern 17, as shown in FIG. 3G, the gate electrode 3
Then, a resist pattern 18 having a shape corresponding to the extraction electrode 7 is formed. Next, by etching the SiO2 film 16 in a direction perpendicular to the substrate surface using the resist pattern 18 as a mask, the SiO2 film 16 is etched as shown in FIG. 3H.
The O2 film 16 is partially removed.

Next, after removing the resist pattern 18, an n-type GaAs layer 19 is epitaxially grown as shown in FIG. 3I. The upper surface of this n-type GaAs layer 19 is
The height should be the same as the top surface of the extraction electrode 7. Next, a gate electrode 3 is placed on the n-type GaAs layer 19 and the SiO2 film 16.
After forming a resist pattern (not shown) having a shape corresponding to the extraction electrode 7, the n-type GaAs layer 19 is etched in a direction perpendicular to the substrate surface using this resist pattern as a mask. 1
Partially remove 9. Next, the resist pattern is removed to obtain the state shown in FIG. 3J. After this, SiO2 is etched by wet etching.
Films 14 and 16 are removed. As a result, FIGS. 1 and 2
A gate electrode 3 and an extraction electrode 7 are formed as shown in FIG. The emitter 1 and the collector 2 are formed before or after the gate electrode 3 and the extraction electrode 7 are formed. In this case, the emitter 1 and the collector 2 are formed by forming a pair of square prism-shaped protrusions facing each other, and then forming a quadrangular pyramid-shaped part by epitaxial growth on the tip surfaces of these protrusions. .

As described above, according to this embodiment, the lower lead-out electrode 7a and the upper lead-out electrode 7b formed between the emitter 1 and the gate electrode 3
It is possible to emit an electron wave from the gate electrode 3 and to divide this electron wave into an electron wave passing above the gate electrode 3 and an electron wave passing below the gate electrode 3. For this reason, a negatively biased blocker is used to separate the electron wave emitted from the emitter 1 into two electron waves, as in the case of the vacuum AB effect transistor proposed in Japanese Patent Application No. 2-173003. It is no longer necessary, and therefore the electric field near the tip of the emitter 1 does not become weaker. Therefore, electron emission from the emitter 1 is likely to occur. Moreover, the distance between the emitter 1 and the extraction electrode 4 can be reduced to, for example, about 1500 Å by using dry etching technology and epitaxial growth technology together. Therefore, the voltage applied between the emitter 1 and the extraction electrode 7 can be lowered to cause electrons to be emitted from the emitter 1 in an electric field.

Furthermore, since the gate electrode 3 has a parallel plate capacitor structure, the potentials in the spaces above and below the gate electrode 3 can be kept constant. Therefore, no potential difference occurs between the paths of electrons passing above and below the gate electrode 3, thereby sufficiently increasing the modulation efficiency of the quantum mechanical transition probability of electrons from the emitter 1 to the collector 2. be able to. Furthermore, since the gate electrode 3 can be formed quite thin, the path of electrons from the emitter 1 to the collector 2 will not be so curved. Therefore, the collection efficiency of the electrons emitted from the emitter 1 by the collector 2 can be increased. Furthermore, since the vacuum AB effect transistor according to this embodiment allows electrons to travel in a vacuum, it can operate at room temperature.

Although one embodiment of the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various modifications can be made based on the technical idea of the present invention. . For example, in the above-described embodiment, the gate electrode 3 has a parallel plate capacitor structure, but it is also possible to use a gate electrode 3 having a structure different from this parallel plate capacitor structure.

[0017]

[Effects of the Invention] As explained above, according to the present invention, an extraction electrode is provided between the emitter and the gate electrode,
This extractor electrode allows electron waves to be emitted from the emitter and is divided into multiple electron waves, allowing operation at room temperature and allowing vacuum electrons to easily emit electron waves from the emitter. A wave interference transistor can be realized.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a vacuum AB effect transistor according to an embodiment of the present invention.

[Figure 2] 2-2 of the vacuum AB effect transistor shown in Figure 1
FIG. 3 is a cross-sectional view along the line.

3 is a cross-sectional view for explaining a method of manufacturing the vacuum AB effect transistor shown in FIGS. 1 and 2. FIG.

[Explanation of symbols]

1 Emitter 2 Collector 3 Gate electrode 7 Extraction electrode

Claims (1)

[Claims] Claim 1: After dividing an electron wave emitted into a vacuum from an emitter into a plurality of electron waves, the plurality of electron waves are combined at a collector, and the phase difference between the plurality of electron waves is adjusted by a gate electrode. A vacuum electron wave interference transistor configured to control, wherein an extraction electrode is provided between the emitter and the gate electrode, the extraction electrode causes the emitter to emit the electron wave, and
A vacuum electron wave interference transistor characterized in that the electron wave is divided into a plurality of electron waves.