JPH0423263Y2 - - Google Patents

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Publication number
JPH0423263Y2
JPH0423263Y2 JP1985075402U JP7540285U JPH0423263Y2 JP H0423263 Y2 JPH0423263 Y2 JP H0423263Y2 JP 1985075402 U JP1985075402 U JP 1985075402U JP 7540285 U JP7540285 U JP 7540285U JP H0423263 Y2 JPH0423263 Y2 JP H0423263Y2
Authority
JP
Japan
Prior art keywords
substrate
wiring
electrodes
electrode
anisotropic conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1985075402U
Other languages
Japanese (ja)
Other versions
JPS61196277U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985075402U priority Critical patent/JPH0423263Y2/ja
Publication of JPS61196277U publication Critical patent/JPS61196277U/ja
Application granted granted Critical
Publication of JPH0423263Y2 publication Critical patent/JPH0423263Y2/ja
Expired legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

【考案の詳細な説明】 イ 産業上の利用分野 本考案は基板上に複数並列配置された配線から
この配線の側部方向に信号電極を設け、この電極
と上記配線とを接続する電極接続構造に関する。
[Detailed description of the invention] A. Industrial application field The present invention is an electrode connection structure in which a signal electrode is provided in the side direction of a plurality of wirings arranged in parallel on a substrate, and this electrode is connected to the above wiring. Regarding.

ロ 従来の技術 液晶表示装置において、ガラス基板上に設けら
れた駆動用の半導体チツプと、このガラス基板上
に複数並列配置され、入力ラインを構成する配線
とを電気的に接続するに際し、従来は例えば特公
昭59−17977号に示されるようなワイヤボンデイ
ングを用いて行つていた。即ち、第3図の上面図
に示す如くガラス基板1上に設けられた配線2,
2…と半導体チツプ3上の所望のボンデイングパ
ツド4,4…はワイヤ5,5…でボンデイングさ
れていた。尚、ここで、6,6…は半導体チツプ
3からの出力ラインである。
B. Prior Art In a liquid crystal display device, when electrically connecting a driving semiconductor chip provided on a glass substrate to a plurality of wiring lines arranged in parallel on the glass substrate and forming input lines, conventional techniques have been used. For example, wire bonding was used as shown in Japanese Patent Publication No. 59-17977. That is, as shown in the top view of FIG. 3, the wiring 2 provided on the glass substrate 1,
2... and desired bonding pads 4, 4, . . . on the semiconductor chip 3 were bonded with wires 5, 5, . Here, 6, 6, . . . are output lines from the semiconductor chip 3.

ハ 考案が解決しようとする問題点 ところが、こうした接続構造にすると、ボンデ
イング距離が長くなり第4図の断面図のようにワ
イヤ5が垂下して他の配線2に接触する惧れがあ
つた。このため、第5図のようにワイヤ5を持ち
上げて他の配線2に接触しないような修正を行わ
なければならず、ボンデイング工程が煩雑になる
と云う問題があつた。
C. Problems to be Solved by the Invention However, with such a connection structure, the bonding distance becomes long, and as shown in the cross-sectional view of FIG. 4, there is a risk that the wire 5 will hang down and come into contact with other wiring 2. For this reason, as shown in FIG. 5, it is necessary to lift the wire 5 and correct it so that it does not come into contact with other wiring 2, which poses a problem in that the bonding process becomes complicated.

ニ 問題点を解決するための手段 本考案はこのような点に鑑みて為され、第1の
基板となるガラス基板上に複数本並列に設けられ
た配線の側部に、配線と交差する方向に、複数並
列状態に形成された電極を設け、導電パターンが
形成された第2の基板とこの第2の基板を保持す
る異方性導電膜により、各配線と電極との電気的
接続を採つている。
D. Means for Solving the Problems The present invention has been made in view of the above points, and includes a wire in a direction intersecting with the wire on the side of a plurality of wires provided in parallel on the glass substrate serving as the first substrate. A plurality of electrodes are formed in parallel, and electrical connections between each wiring and the electrodes are made using a second substrate on which a conductive pattern is formed and an anisotropic conductive film that holds the second substrate. It's on.

ホ 作用 複数本並列に配置された配線の側部に複数の電
極を設け、これ等の電極と各配線とを上記第2の
基板上の導電パターン及び異方性導電膜により電
気的に接続しているので、配線からの電極の取り
出しが安全に行え、こうした電極取り出し構造を
液晶表示器のガラス基板上の配線と、駆動用の半
導体チツプと、の電気的接続を採るのに利用出来
る。
E. Effect A plurality of electrodes are provided on the sides of a plurality of wirings arranged in parallel, and these electrodes and each wiring are electrically connected by a conductive pattern and an anisotropic conductive film on the second substrate. Therefore, the electrode can be safely taken out from the wiring, and this electrode extraction structure can be used to make an electrical connection between the wiring on the glass substrate of the liquid crystal display and the driving semiconductor chip.

ヘ 実施例 第1図は本考案電極取り出し構造を用いたガラ
ス基板上の要部上面図、第2図はその要部断面図
であつて、第3図乃至第5図と同一部分には同一
符号が付してある。これ等の図において、入力ラ
インとなる複数本並列配置された配線2,2…と
チツプ3の間のガラス基板1上には多数の電極
7,7…が形成されている。8は第2の基板とな
るフレキシブルプリント基板(以下、FPCと称
す)であつて、上記配線2,2…及び電極7,7
…の少くとも一部を被うように設けられている。
9,9…は上記各配線2,2…とFPC8間に介
在された異方性導電膜を示し垂直方向への導電性
を有する。10は上記電極7,7…とFPC8と
の間に介在された異方性導電膜であつて垂直方向
には導電性を示し、電極7,7…の配列方向には
絶縁性を示すようになつている。また、これ等の
異方性導電膜9,9…10はガラス基板1と、
FPC8との間の距離を保つスペーサの役目も果
たしている。11,11…は上記FPC8表面に
設けられた導電パターンであつて、上記配線2,
2…上の異方性導電膜9,9…位置と、上記各電
極7,7…直上の導電膜10位置と、を夫々電気
的に接続する。また、上記電極7,7…と半導体
チツプ3上のボンデイングパツド4,4…はワイ
ヤ5,5…でボンデイングされている。
F Example Fig. 1 is a top view of the main part on a glass substrate using the electrode extraction structure of the present invention, and Fig. 2 is a sectional view of the main part thereof. A code is attached. In these figures, a large number of electrodes 7, 7, . . . are formed on a glass substrate 1 between a chip 3 and a plurality of wirings 2, 2, . . ., which are input lines arranged in parallel. Reference numeral 8 denotes a flexible printed circuit board (hereinafter referred to as FPC) serving as a second board, on which the wirings 2, 2... and electrodes 7, 7 are connected.
It is provided so as to cover at least a part of...
Reference numerals 9, 9, . . . indicate anisotropic conductive films interposed between the wirings 2, 2, . . . and the FPC 8, which have vertical conductivity. Reference numeral 10 denotes an anisotropic conductive film interposed between the electrodes 7, 7... and the FPC 8, which exhibits conductivity in the vertical direction and exhibits insulation in the direction in which the electrodes 7, 7... are arranged. It's summery. Moreover, these anisotropic conductive films 9, 9...10 are connected to the glass substrate 1,
It also serves as a spacer to maintain the distance between it and the FPC8. 11, 11... are conductive patterns provided on the surface of the FPC 8, and the wirings 2,
The positions of the anisotropic conductive films 9, 9, . . . on the electrodes 7, 7, . Further, the electrodes 7, 7, . . . and the bonding pads 4, 4, . . . on the semiconductor chip 3 are bonded with wires 5, 5, .

従つて、このような構成において、入力ライン
となる配線2,2…に信号が与えられると、異方
性導電膜9,9…、FPC8の導電パータン11,
11…、異方性導電膜10、電極7,7…、ワイ
ヤ5,5…を介して半導体チツプ3のボンデイン
グパツド4,4…に伝えられる。このとき電極
7,7…及びFPC8間の異方性導電膜10は上
述した如く、電極7,7…配列方向には絶縁性を
有しているので、この箇所で短落が生じることは
ない。
Therefore, in such a configuration, when a signal is applied to the wirings 2, 2... serving as input lines, the anisotropic conductive films 9, 9..., the conductive patterns 11,
11..., the anisotropic conductive film 10, the electrodes 7, 7..., and the wires 5, 5... to the bonding pads 4, 4... of the semiconductor chip 3. At this time, as mentioned above, the anisotropic conductive film 10 between the electrodes 7, 7... and the FPC 8 has insulating properties in the arrangement direction of the electrodes 7, 7..., so no shortening occurs at this location. .

尚、上記異方性導電膜9,9…10としては例
えばアンソルムAC−1052(商品名、日立化成(株)
製)、CP−1000、CP−2000(商品名、ソニーケミ
カル(株)製)等が使用される。また、こうした異方
性導電膜9,9…10はFPC8に取り付けられ
たものを設け、FPC8をガラス基板1に取り付
けるとき、これ等の異方性導電膜9,9…10を
配線2,2…及び電極7,7…に熱圧着すること
により取り付ける構成にすると良い。
The anisotropic conductive films 9, 9...10 are, for example, Ansolm AC-1052 (trade name, Hitachi Chemical Co., Ltd.).
), CP-1000, CP-2000 (trade name, manufactured by Sony Chemical Co., Ltd.), etc. are used. Further, these anisotropic conductive films 9, 9...10 are provided attached to the FPC 8, and when the FPC 8 is attached to the glass substrate 1, these anisotropic conductive films 9, 9...10 are attached to the wirings 2, 2. . . . and the electrodes 7, 7 . . . by thermocompression bonding.

ト 考案の効果 以上述べた如く、本考案電極接続構造は、第1
の基板上に複数本並列に配置された配線の側部に
複数の電極を設け、これ等の電極と各配線とを第
2の基板上の導電パターン及び異方性導電膜によ
り電気的に接続しているので配線からの信号の取
り出しが安全に行え、こうした電極接続構造を液
晶表示器のガラス基板上の配線と、表示駆動用の
半導体チツプと、の電気的接続を採るのに利用し
て、信頼性の高い装置が提供される。
G. Effects of the invention As stated above, the electrode connection structure of the invention
A plurality of electrodes are provided on the sides of multiple wirings arranged in parallel on a second substrate, and these electrodes and each wiring are electrically connected by a conductive pattern and an anisotropic conductive film on a second substrate. This makes it possible to safely extract signals from the wiring, and this electrode connection structure can be used to make electrical connections between the wiring on the glass substrate of a liquid crystal display and the semiconductor chip for driving the display. , a highly reliable device is provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案電極接続構造の要部を示す上面
模式図、第2図は本考案要部断面模式図、第3図
は従来の配線半導体チツプの接続状態を示す上面
模式図、第4図、第5図は配線と半導体チツプの
従来の接続状態を示す断面模式図である。 1……ガラス基板、2,2……配線、3……半
導体チツプ、4,4……ボンデイングパツド、
5,5……ワイヤ、7,7……電極、8……
FPC、9,9…10……異方性導電膜、11,
11……導電パターン。
Fig. 1 is a schematic top view showing the main parts of the electrode connection structure of the present invention, Fig. 2 is a schematic sectional view of the main parts of the invention, Fig. 3 is a schematic top view showing the connection state of a conventional wiring semiconductor chip, and Fig. FIG. 5 is a schematic cross-sectional view showing a conventional connection state between wiring and a semiconductor chip. 1... Glass substrate, 2, 2... Wiring, 3... Semiconductor chip, 4, 4... Bonding pad,
5, 5...wire, 7,7...electrode, 8...
FPC, 9,9...10...Anisotropic conductive film, 11,
11... Conductive pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1の基板上に複数並列状態に形成された配線
と、この配線側部の第1の基板上に上記配線と交
差する方向に複数並列状態に形成された電極と、
少くともこの電極直上部及び上記配線の一部を被
う第2の基板と、上記配線及び電極上に設けら
れ、上記第1の基板と第2の基板とのスペーサと
なるとともに、垂直方向に導電性を有する異方性
導電膜と、上記第2の基板表面に形成され上記配
線上の導電膜位置から上記電極上の導電膜位置を
結ぶ導電パターンと、から成る電極接続構造。
a plurality of wirings formed in parallel on a first substrate; a plurality of electrodes formed in parallel in a direction intersecting the wirings on the first substrate on the side of the wiring;
a second substrate that covers at least directly above the electrode and a part of the wiring; and a second substrate that is provided on the wiring and the electrode and serves as a spacer between the first substrate and the second substrate; An electrode connection structure comprising an anisotropic conductive film having conductivity and a conductive pattern formed on the surface of the second substrate and connecting a conductive film position on the wiring to a conductive film position on the electrode.
JP1985075402U 1985-05-21 1985-05-21 Expired JPH0423263Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985075402U JPH0423263Y2 (en) 1985-05-21 1985-05-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985075402U JPH0423263Y2 (en) 1985-05-21 1985-05-21

Publications (2)

Publication Number Publication Date
JPS61196277U JPS61196277U (en) 1986-12-06
JPH0423263Y2 true JPH0423263Y2 (en) 1992-05-29

Family

ID=30616591

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985075402U Expired JPH0423263Y2 (en) 1985-05-21 1985-05-21

Country Status (1)

Country Link
JP (1) JPH0423263Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6016124B2 (en) * 1978-12-30 1985-04-24 松下電器産業株式会社 antenna angle adjustment device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6016124U (en) * 1983-07-08 1985-02-02 シャープ株式会社 Transmissive liquid crystal display device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6016124B2 (en) * 1978-12-30 1985-04-24 松下電器産業株式会社 antenna angle adjustment device

Also Published As

Publication number Publication date
JPS61196277U (en) 1986-12-06

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