JPH0423171A - Inspecting device for connection of circuit diagram - Google Patents

Abstract

PURPOSE:To reduce storage area and to process a circuit diagram of a large scale by processing a connecting relation closed in a drawing, the connecting relation covering the drawings, and the connecting relation covering the hierarchies while reading successively the drawings and deleting a processed store structure after its processing. CONSTITUTION:A logic circuit diagram data base 2 stores the data on a store structure showing the connecting relation between the elements into a logic circuit diagram which is divided for each hierarchy consisting of one or more sheets of drawings. A connection rule data base 3 stores a connection rule showing the propriety of the connecting relation. Then a circuit diagram connection inspecting part 1 reads successively the divided drawings and at the same time processes the connecting relation between the elements closed in a single drawing or hierarchy for each hierarchy. The connecting relation between the elements is extracted and inspected by a system itself based on the connection information in regard of the connecting relation covering the hierarchies. Then the processed store structure is deleted after processing. Thus it is possible to reduce the working capacity of a main storage storing the store structure and to process a circuit diagram of a large scale.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention reads a logic circuit diagram in units of drawings on a computer, and checks the validity by comparing the connection relationships of elements on the circuit diagram with connection rules. Regarding the device to be verified.

〔overview〕

The present invention provides a means for verifying connections in a logic circuit diagram, in which connection relationships that are closed within a drawing, connection relationships that span between drawings, and connections that span between layers are verified at the stages of drawing processing, hierarchy processing, and inter-layer processing. By processing connection relationships while sequentially reading the drawings and deleting the processed storage structure after processing, it is possible to reduce the storage area for storing the storage structure and process large-scale circuit diagrams. It is.

[Conventional technology]

In the conventional example, when a logic circuit diagram is divided into layers and each layer is divided into multiple drawings, the structure of the layer division and drawing division is expanded and removed after reading all the drawings, and the circuit is flattened. Verification was performed after generating information about the connection relationships between elements.

[Problem to be solved by the invention]

In such conventional examples, connection information that has been flattened by fully expanding the circuit's hierarchical structure must be generated and stored within the system. If the logic circuit becomes a logical circuit, there is a drawback that processing becomes impossible because connection information cannot be stored. Furthermore, in flat circuit information, connection information between closed elements in a lower circuit hierarchy exists for the number of times the lower hierarchy appears in the circuit, so it is processed multiple times even though the connection relationship is the same. This has the disadvantage that processing time becomes longer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit diagram connection verification device that eliminates such drawbacks and can avoid redundant processing.

Means for Solving Problem C] The present invention stores data related to a storage structure that shows connection relationships between elements described on a logic circuit diagram that is divided into layers and each layer consists of one or more drawings. a first memory means for
In a circuit diagram connection verification device equipped with a second storage means that holds a connection rule indicating the validity of this connection relationship, the connection relationship between elements is defined as a first connection relationship that is closed within the same drawing, and a second connection relationship that is closed in the same drawing, There is a method for classifying connection relationships into second connection relationships that span drawings or third connection relationships that span different hierarchies, and a first method that verifies the first connection relationships by comparing them with the connection rules each time a drawing is read. Based on the storage structure related to the verification means and the drawing whose validity has been verified by the first verification means, information indicating the second connection relationship is copied to the inter-drawing storage structure, and information indicating the third connection relationship is stored between hierarchies. The apparatus is characterized by comprising a first deletion means for deleting data related to the storage structure from the first storage means after copying the data to the storage structure.

Also, a second verification means that verifies the second connection relationship by comparing it with the connection rule after reading all the drawings in one hierarchy, and an inter-drawing storage structure of the hierarchy whose validity is verified by the second verification means. a second deletion means for copying the information indicating the third connection relationship to the inter-layer storage structure based on the information and then deleting the data related to the inter-drawing storage structure of this layer; and the third connection relationship after reading all the drawings of all the layers. It is preferable to include third verification means for verifying by comparing the connection rule with the connection rule.

[Effect]

Rather than generating and processing flat connection information by removing the circuit hierarchy division and drawing division structure after reading all drawings, the divided drawings are read sequentially and closed within one drawing or one hierarchy. The connection relationships between elements are processed for each layer, and the connection relationships that span between layers are processed by the system itself by tracking different layers based on the connection information stored while maintaining the hierarchical structure. The connection relationships are extracted and verified and verified.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of this embodiment, and FIG. 2 shows the configuration of the circuit diagram connection verification section of FIG. 1.

As shown in FIG. 1, this embodiment includes a circuit diagram connection verification section 1, a logic circuit diagram database 2, and a connection rule database 3.
As shown in the figure, the connection relation sorting includes a means 11, a first verification means 12, a first deletion means 13, a second verification means 14, a second deletion means 15, and a third verification means 16. .

That is, this embodiment is a first storage means for storing data related to a storage structure showing connection relationships between elements described on a logic circuit diagram divided into layers and each layer consisting of one or more drawings. The present invention is equipped with a logic circuit diagram database 2 and a connection rule database 3 which is a second storage means for holding connection rules indicating the validity of this connection relationship. Connection relationship sorting for sorting relationships into a first connection relationship that is closed within the same drawing, a second connection relationship that spans different drawings within the same hierarchy, or a third connection relationship that spans different levels is performed using means 11 and reading the drawing. a first verification means 12 for verifying the first connection relationship by comparing it with the connection rule for each time;
The information indicating the second connection relationship is copied to the inter-drawing storage structure based on the storage structure related to the drawing whose validity was verified in a first deletion means 13 for deleting related data from the first storage means; a second verification means I4 for verifying the second connection relationship by comparing it with the connection rules after reading all the drawings in one hierarchy; After copying the information indicating the third connection relationship to the inter-layer storage structure based on the inter-drawing storage structure of the layer whose validity has been verified by the second verification means 14, the data related to the inter-drawing storage structure of this layer is deleted. 2 deletion means 15; and a third verification means 16 for verifying the third connection relationship by comparing it with the connection rule after reading all the drawings in all the hierarchies.

Next, the operation of this embodiment will be explained.

FIG. 3 is a flowchart of the entire processing of this embodiment.

After the system is started (step 5101), processing starts from the top level of the logic circuit diagram, and as long as there is an unprocessed hierarchy (step S102), there are unprocessed logic circuit diagrams of the relevant hierarchy. (Step S103
), after reading each drawing (step S10
4) Perform the following processing. In-drawing connection verification process (step S
105), as shown in Figure 3, the connection relationships between elements are classified into three types: closed within the same drawing, across different drawings within the same hierarchy, or across different levels. , the connection validity is verified only for connection relationships between closed elements within the same drawing. After that, only the connection relationships that span different drawings are extracted from the storage structure of one screen's worth of connection information and copied to the storage structure between drawings, and the connection relationships that do not span drawings but span different hierarchies are extracted. Step S106) Extract and copy and save to inter-layer storage structure.
. - Since the drawing storage structure is no longer needed, - the process of deleting all the drawing storage structures is performed (step S107).
. When the drawing-by-drawing processing of all drawings is completed and there are no unprocessed drawings (step S103), the inter-drawing storage structure for one level has been completed, and the next processing is performed. In the inter-drawing connection verification process (step 3108), connection relationships that do not span different hierarchies in the inter-drawing storage structure are verified. After that, the connection relationships spanning different hierarchies are copied from the inter-drawing storage structure to the inter-layer storage structure (step 5109), but at this time, elements for inter-drawing connections within the connection relationships are removed,
Copy with the drawing division structure erased.

Since the inter-drawing storage structure is no longer necessary, inter-drawing storage structure deletion processing (step 5IIO) is performed. Processing of all layers is completed and there are no unprocessed layers (step S10).
2>, the inter-layer connection verification process (step 5ill) is performed on the inter-layer storage structure of all the layer elements of the circuit by sequentially tracing different layers up the upper layer and detecting elements in a connection relationship to check the connection validity. Verify gender.

As shown in FIG. 1, this embodiment processes data stored in a logic circuit diagram database 2 divided into drawing units created by a circuit artist such as Kanstem. The connection rule database 3 describes rules for forced connection and prohibited connection between elements, and the circuit diagram connection verification section 1 verifies these rules. The verification results are output by writing the name of the connection relationship that violates the rules in the verification result list.

FIG. 4 is a flowchart showing details of step 5105 in FIG. - After reading the drawing, generate a storage structure within one screen, that is, a structure that indicates which pin of which element in the drawing is connected for each connection relationship (step 5201>
. As long as there are unprocessed connection relationships in the drawing (step 5202), the process ends (step S20).
Process up to 7) in sequence.

As long as there are unprocessed connection elements, - Obtain the circuit elements connected in the connection relationship (step S203), determine the type of connection element (step S204), and connect the circuit elements between drawings. If the element is for the purpose of
If the connection element is an element that connects between layers (called an interlayer terminal) or an element that has a circuit diagram of a lower layer (called a macro), the type of connection relationship is defined as a connection relationship that spans different layers. Set (Step S205)
. Validity verification processing is performed only on connection relationships that are closed within drawings that are set in step S205 as neither between drawings nor between hierarchies (step S206).

FIG. 5 is a specific example of a logic circuit diagram explaining the storage structure generated by the present invention. This circuit consists of the TOP layer and the M layer below it.
It has a two-layer structure with the AC layer, and the TOP layer drawing is divided into a drawing 401 and a drawing 402, and the connection relationship N6 and the connection relationship N7 are connected via the inter-page terminal J1. A macro M1 is arranged in drawing 401, and its internal circuit is shown in drawing 403.

FIG. 6 is a diagram showing the storage structure of drawing 401.

A circuit element name and a pin salt of the circuit element are associated with each connection relationship name. Here, connection relationship N6 is connected to the inter-page terminal, so it is a connection relationship that spans different drawings, and connection relationship N3 and connection relationship N4 are connected to macro M1, so it is a connection relationship that spans different layers. , and other connections are closed in the drawing.

FIG. 7 is a diagram showing the inter-drawing storage structure of the TOP layer,
001 drawing 401 of TOP layer and 002 of TOP layer
It includes a drawing 402 and a MAC layer 001 drawing 403 . From the storage structure in the drawing in Figure 6, the drawing salt, connection relationship name,
Circuit element names and pin salts have been copied. Since a connection relationship occurs between different drawings when the terminal names between pages are the same, the connection relationship between the OUT bin of element C3 and the IN bin of element C5 is extracted via the interpage terminal J1, and the connection relationship between drawings is verified. Processed in stages.

FIG. 8 is a diagram showing an inter-layer storage structure of the circuit example shown in FIG. In this example, there is no connection relationship that spans between drawings and between hierarchies, so from Fig. 6, the hierarchy salt,
Connection relationship names, circuit element names, and pin salts are duplicated. During the inter-layer connection verification process, a connection relationship occurs between layers when the pin level of the circuit element in the upper layer and the inter-layer terminal name in the lower layer are the same, so basically the connection relationship is generated from the upper layer along the different layer tracing path. Trace down to the lower hierarchy and extract connected elements.

FIG. 9 is a logic circuit diagram as a specific example for explaining the present invention. This circuit has a two-layer structure of TOP2 and MAC2 below it.
Two MACs are placed inside. For this purpose MA
The connection relationship N1 in the 0 old drawing 802 of the C2 hierarchy exists in two places when the circuit is flattened, but the connection relationship N1 between the circuit element C1 and the circuit element C2 exists at the stage of connection verification processing in the drawing 802. Validity verification only needs to be processed once.

〔Effect of the invention〕

As explained above, the present invention uses a storage structure that stores drawing division and hierarchy division of a circuit, and closes connections within the drawing at each stage of drawing processing, one-layer processing, and inter-layer processing. Relationships, connections between drawings, and connections between hierarchies are processed while sequentially reading the drawings, and the processed storage structure is deleted after processing, so the main memory that stores the storage structure is It is possible to process large-scale circuit diagrams by reducing the amount of space used, and it also speeds up processing time because it only needs to be processed once to verify closed connections within lower layers that have been placed multiple times. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing the overall configuration of an embodiment of the present invention. FIG. 2 is a configuration diagram showing the configuration of the circuit diagram connection verification section shown in FIG. 1. FIG. 3 is a flowchart showing the operation of the embodiment of the present invention. FIG. 4 is a flowchart showing the operation of the embodiment of the present invention. FIG. 5 is a specific example of a logic circuit diagram for explaining the present invention. FIG. 6 is a diagram showing the storage structure of one screen of drawing 001 in the TOP hierarchy of FIG. FIG. 7 is a diagram showing the inter-drawing storage structure of the TOP layer in FIG. FIG. 8 is a diagram showing the inter-layer storage structure of FIG. 5. FIG. 9 is a specific example of a logic circuit diagram for explaining the present invention. DESCRIPTION OF SYMBOLS 1... Circuit diagram connection verification unit, 2... Logic circuit diagram database, 3... Connection rule database, 11... Connection relationship sorting means, 12... First verification means, 13...
- First deletion means, 14...Second verification means, 15...
Second deletion means, 16...Third verification means, 401...
001 drawing of TOP layer, 402...0 of TOP layer
02 drawing, 403...001 drawing of MAC layer, 80
1...0 old drawing of TOP2 hierarchy, 802...MAC
2-layer 001 drawing, 01-C5...Circuit element, IN
, OUT...external terminal, Jl...terminal between pages, M
L M2...Macro, N1-N10...Connection. Actual flag I1 to complete practice diagram history method bamboo example / 1 also king shiujime knku diagram, 5201 movement chart diagram diagram diagram diagram z plane mark hosohashikyari diagram a diagram Figure Figure

Claims (1)

[Claims] 1. A first storage means for storing data related to a storage structure showing connection relationships between elements described on a logic circuit diagram divided into layers and each layer consisting of one or more drawings. and a second storage means for retaining a connection rule indicating the validity of this connection relationship, a first connection relationship in which the connection relationship between elements is closed in the same drawing;
connection relationship sorting means for sorting into a second connection relationship spanning different drawings in the same hierarchy or a third connection relationship spanning different levels; Based on the first verification means to be verified and the storage structure related to the drawing whose validity has been verified by this first verification means, information indicating the second connection relationship is copied to the inter-drawing storage structure, and information indicating the third connection relationship is copied. 1. A circuit diagram connection verification device comprising: first deletion means for copying data into an inter-layer storage structure and then deleting data related to this storage structure from the first storage means. 2. A second verification means for verifying the second connection relationship against the connection rule after reading all the drawings in one hierarchy, and an inter-drawing storage structure for the hierarchy whose validity has been verified by the second verification means. a second deletion means for copying the information indicating the third connection relationship to the inter-layer storage structure based on the information and then deleting the data related to the inter-drawing storage structure of this layer; and the third connection relationship after reading all the drawings of all the layers. 2. The circuit diagram connection verification device according to claim 1, further comprising third verification means for verifying by comparing the connection rules with the connection rules.