JPH04205566A - Verifying device for data designing mask pattern of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To automatically verify the corresponding relation between cell information and a net list before executing the generating work of a mask pattern by collating an input/output terminal name and input/output terminal attribute information between the cell information and the net list. CONSTITUTION:Information used in common between cell information and a net list is a cell name to specify a cell, an input/output terminal name within the cell and a input/output terminal attribute information to indicate whether an input/output terminal is an input terminal or an output terminal. A unit information retrieving means 4 retrieves the cell name same as the cell name extracted from within the net list 2 from within the cell information. When the same cell name is not retrieved, the discrimination of the effect of uncoincidence is executed by a verified result discriminating means. When the same cell name is retrieved, the input/output terminal name and the input/output terminal attribute information are collated in the both cells. Thus, when the uncoincidence is generated, since the discrimination of the effect of the uncoincidence is executed by a verified result discriminating means 7, corresponding relation between the cell information and the net list can be verified automatically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a verification device for mask pattern design data for semiconductor integrated circuits.

[Conventional technology]

An automatic layout method using a standard cell method is known as a method for designing mask patterns for semiconductor integrated circuits. In this method, some general-purpose functional block cells and logic cells are designed in advance as standard cells, and when designing a specific semiconductor integrated circuit, the prepared standard cells are combined to create the overall layout. Do the design. In other words, standard cells are prepared as a cell library, and this cell library is used to design the layout of an actual integrated circuit. Normally,
A standard cell may be used multiple times in the same integrated circuit, and may be used repeatedly in different integrated circuits. Therefore, once a standard cell is designed, it can be kept as a design asset and used effectively in the future.

In this automatic layout method using the standard cell method, cell information prepared as a cell library and a netlist for a semiconductor integrated circuit to be specifically designed are prepared, and predetermined calculations are performed based on these. By doing this, a mask pattern will be automatically generated.

[Problem to be solved by the invention]

As mentioned above, in the automatic layout method using the standard cell method, a mask pattern is automatically generated based on the cell information and the netlist, but if there is a mismatch between the two, It becomes impossible to obtain a desired mask pattern.

Generally, in a semiconductor integrated circuit, a large number of cells having a hierarchical structure are defined, and each cell is interconnected in a complicated manner. Therefore, when creating a netlist, it is easy to make mistakes such as mixing up cell names, mixing up the names of input/output terminals in each cell, and mixing up the input or output attributes. If the netlist contains such mistakes,
An erroneous mask pattern will be generated, and time will be wasted in the wasteful process of re-generating the mask pattern after correcting the mistake.

Therefore, an object of the present invention is to provide a verification device for mask pattern design data for semiconductor integrated circuits that can automatically verify the correspondence between cell information and a netlist before performing mask pattern generation work. purpose.

[Means to solve the problem]

The present invention provides a cell name for specifying a cell, an input/output terminal name for specifying an input/output terminal provided for this cell, and input/output terminal position information for specifying a position of the input/output terminal. , input/output terminal layer information for specifying the input/output terminal or the wiring layer used, and input/output terminal attribute information for specifying whether the input/output terminal is an input terminal or an output terminal, in one cell. Define unit information about
Cell information obtained by defining this unit information for multiple cells is prepared, and a cell name to identify the cell, an input/output terminal name to identify the input/output terminal provided for this cell, Input/output terminal attribute information for specifying whether an input/output terminal is an input terminal or an output terminal, and inter-cell connection information indicating the mutual connection status of lower cells, for one cell. A netlist obtained by defining this unit information for multiple cells is prepared, and when designing a mask pattern for a semiconductor integrated circuit based on the prepared cell information and netlist, the cell A verification device for verifying the correspondence between information and a netlist, comprising: cell information storage means for storing cell information; netlist storage means for storing the netlist; and a verification device for any one cell from the netlist storage means. unit information extraction means for extracting unit information of the unit; unit information retrieval means for retrieving unit information having the same cell name as the cell name related to the unit information extracted by the unit information extraction means from the cell information storage means; common information extraction means for extracting input/output terminal names and input/output terminal attribute information from the unit information extracted by the information extraction means; A common information matching means that matches the input/output terminal name and input/output terminal attribute information in the unit information searched by the unit information searching means, and when unit information with the same cell name cannot be retrieved by the unit information searching means. Alternatively, when the comparison result by the common information comparison means does not match, a verification result judgment means outputs a judgment result indicating that there is a mismatch in the correspondence relationship.

[For production]

The information commonly used between cell information and netlists is the cell name to identify it as a cell, the name of the input/output terminal within that cell, and whether this input/output terminal is an input terminal or an output terminal. and input/output terminal attribute information. The unit information search means searches cell information for the same cell name as the cell name extracted from the netlist. If the same cell name is not retrieved, the verification result determining means determines that there is no match. If the same cell name is retrieved, input/output terminal names and input/output terminal attribute information are compared between the cells. As a result, if a mismatch occurs, the verification result determining means determines that there is a mismatch. In this way, the correspondence between the cell information and the netlist can be automatically verified.

〔Example〕

The present invention will be described below based on illustrated embodiments. FIG. 1 is a block diagram showing the basic configuration of a verification device according to the present invention. The cell information storage means 1 and the netlist storage means 2 are both storage devices such as a disk or a magnetic tape connected to a computer constituting a mask pattern design device (not shown) for a semiconductor integrated circuit. The mask pattern design device generates a desired mask pattern based on the cell information stored in the cell information storage means 1 and the netlist stored in the netlist storage means 2. The verification device according to the present invention compares the cell information stored in the cell information storage means 1 and the netlist stored in the netlist storage means 2 before performing mask pattern generation processing by this mask pattern design device. The purpose is to verify the correspondence relationship.

The cell information stored in the cell information storage means 1 is composed of a plurality of unit information, and one unit information is defined corresponding to one cell. More specifically, one piece of unit information includes a cell name for specifying a cell, an input/output terminal name for specifying an input/output terminal provided for this cell, and an input/output terminal name for specifying the position of the input/output terminal. Input/output terminal position information, input/output terminal layer information for specifying the wiring layer used by the input/output terminal, and input/output terminal attribute information for specifying whether the input/output terminal is an input terminal or an output terminal. It consists of five elements.

On the other hand, the netlist stored in the netlist storage means 2 is composed of a plurality of unit information, and one unit information is defined corresponding to one cell. More specifically, one piece of unit information includes a cell name to identify the cell, an input/output terminal name to identify the input/output terminal provided for this cell, and whether the input/output terminal is an input terminal or an output terminal. 4. Input/output terminal attribute information to identify which one is, and inter-cell connection information for lower cells.
It consists of two elements.

In order to verify the correspondence between the cell information in the cell information storage means 1 and the netlist in the netlist storage means 2, this device uses unit information extraction means 3 and unit information retrieval means 4.
, common information extraction means 5, common information collation means 6, and verification result determination means 7. Each of these means is actually realized by computer software.

The unit information extraction means 3 extracts from the netlist storage means 2,
It has a function to extract unit information about any one cell. Further, the unit information retrieval means 4 includes the unit information extraction means 3.
It has a function of searching the cell information storage means 1 for unit information having the same cell name as the cell name related to the unit information extracted from the cell name. Furthermore, the common information extraction means 5 extracts input/output terminal names and input/output terminal attribute information from the unit information extracted by the unit information extraction means 3, and the common information collation means 6 extracts input/output terminal names and input/output terminal attribute information from the unit information extracted by the unit information extraction means 3. It has a function of comparing the name and input/output terminal attribute information with the input/output terminal name and input/output terminal attribute information in the unit information searched by the unit information search means 4. Then, when the unit information retrieval means 4 is unable to retrieve unit information having the same cell name, or when the common information collation means 6 results in a mismatch, the verification result determination means 7 determines the correspondence relationship. Outputs the determination result that there is a mismatch.

Next, the operation of the apparatus shown in FIG. 1 will be explained in detail based on a specific example. Assume now that data as shown in FIG. 2 is stored as one unit of information in the cell information storage means 1. This unit information is data for defining a standard cell as shown in FIG. The first line of the data shown in FIG. 2 indicates that this unit information is information about a cell with the cell name rC220J. Continued 2
The type of this cell is shown in the row 1, and it is shown that this cell is rSTANDARD CELL J, that is, a standard cell. The 3rd and 4th lines are the data that defines the size of this cell, and the 3rd line is the coordinate value (0
, 0), and the fourth line shows the coordinates li&(150°80). That is, as shown in FIG.
, 80) as the upper right corner point. The following 5th to 7th lines show information regarding the input/output terminals for this cell. In the fifth line, the input/output terminal with the input/output terminal name rAJ is located at the coordinate value (0°50), and the input/output terminal attribute information is "INJ".
(that is, an input terminal), and the input/output terminal layer information is rPOLYJ (that is, a polysilicon layer is used as a wiring layer).

Similarly, on the 6th line, the input/output terminal with the input/output terminal name rBJ is located at the coordinate value (0, 30), the input/output terminal attribute information is rINJ, and the input/output terminal layer information is rPOL.
It is shown that YJ. Furthermore, on the 7th line, the input/output terminal with the input/output terminal name "C" has the coordinate value (150,
40), and its input/output terminal attribute information is rOUTJ.
(that is, an output terminal), and the input/output terminal layer information indicates that it is rAL2J (that is, the second aluminum layer is the wiring layer). From the 8th line onwards, information regarding the inside of this cell is listed, or is omitted here. From the above explanation, it can be understood that the cell information shown in FIG. 2 corresponds to the cell C220 shown in FIG. 3. In this way, the cell information storage means 1 stores information about one cell as one unit information.
A large amount of unit information or cell libraries are provided.

Next, an example of a netlist stored in the netlist storage means 2 will be shown. FIG. 4 shows an example of a cell configuration of a semiconductor integrated circuit having a hierarchical structure. Below the first layer cell marked TOP, second layer cells marked C100 to C300 are defined, and cell C200
Cells C210 to C240 of the third hierarchy are further defined under the cell C220, and cells C221 and C222 of the fourth hierarchy are defined further below the cell C220. The netlist in the netlist storage means 2 becomes information indicating the connection relationship between cells for each cell having such a hierarchical structure. For example, FIG. 5 shows an example of netlist data for cell C220, that is, one piece of unit information. The first line of the data shown in FIG. 5 indicates that this unit information is information about a cell with the cell name 1''C220j.
The string J is rAJ and rBJ before ","
indicates the input terminal name of this cell, and "C" after ";"
" indicates the output terminal name of this cell. In the second and third rows, rc221J is added as a lower cell.
A NAND gate with the cell name rC222J and an INv (inverter) with the cell name rC222J are defined. Then, nodes A and B are connected to the input terminal of cell C221.
Node B2 is connected to each output terminal, and further,
It is shown that the node B2 is connected to the input terminal of the cell C222, and the node FC is connected to the output terminal of the cell C222. Note that in this example, node A.

B and C have input/output terminals A and B of cell C220.
.

The same name as C is used, and nodes and terminals with the same name are connected. The symbol “rEND” in the fourth and final line indicates a break between one unit of information.

After all, the netlist shown in FIG. 5 defines a cell C220 as shown in FIG.

In other words, the netlist shown in FIG.
The unit information for this cell) is the cell name for this cell (
C220), input/output terminal names (A, B, C on the first line), and input/output terminal attribute information (input terminal or output terminal depending on whether it is before or after the ":" on the first line). It is shown)
and inter-cell connection information (second and third rows) for lower-order cells.

Now, on the one hand, data as shown in FIG. 2 as one unit information in the cell information storage means 1, and on the other hand, data as shown in FIG. 5 as one unit information in the netlist storage means 2, If each is prepared, the first
Let us explain the verification operation by the verification device shown in the figure. FIG. 7 is a flowchart showing the procedure of this verification operation. First, in step S1, predetermined unit information is extracted from the netlist. That is, the unit information extraction means 3 extracts one predetermined unit information from the netlist storage means 2. Since the unit information extraction means 3 has a function of extracting any one unit information in the netlist storage means 2, for example, the unit information may be extracted one by one in the order in which they are described as a list. . As shown in FIG. 4, the netlist storage means 2 contains data for one cell for a large number of cells having a hierarchical structure.
Defined as unit information. If necessary, all of these cells may be verified, or only cells in a specific hierarchy may be verified.

In any case, it is sufficient to sequentially extract unit information about cells to be verified one by one.

Subsequently, in step S2, corresponding unit information is searched from the cell information. That is, the unit information search means 4
will search the cell information storage means 1 and find the corresponding unit information. Here, "corresponding unit information" is unit information about cells defined with the same cell name.

For example, in step S1, the unit information extraction means 3
Assume that unit information as shown in FIG. 2 is extracted.

The cell name of this unit information is "C220". Therefore, in step S2, the unit information search means 4 searches for cell information such as the cell name or rC220J. As a result, the unit information shown in FIG. 5 is retrieved.

If the corresponding unit information is found as a result of the search in step S2, common information is extracted in step S4. Here, "common information" refers to information that is commonly used in both the cell information and the netlist, and specifically includes input/output terminal names and input/output terminal attribute information. Therefore, the common information extraction means 5 extracts rAJ and rBJ from the data shown in FIG. 2 extracted by the unit information extraction means 3.

The input/output terminal name "C" and the input/output terminal attribute information rlNJ, rlNJ, rOUTJ for these are extracted. Then, in the subsequent step S5, common information is verified. That is, the common information collation means 6 performs rAJ and rBJ for the data shown in FIG. 5 retrieved by the unit information retrieval means 4.

Check the existence of the same input/output terminal name "C" and check the input/output terminal attributes for these.

Check whether rINJ and rOUTJ are set.

If the two completely match, it is a normal state.

In the specific example shown here, the first line of the data shown in FIG. Since it is a description, both the input/output terminal name and the input/output terminal attribute information match.

In this way, if the matching result in step S5 is -, the process proceeds to step S7 via step S6. and,
The above procedure is repeated until all necessary unit information has been extracted from the netlist storage means 2. However, if the corresponding unit information is not retrieved in step S3, or if the collation results do not match in step S6, a non-coincidence determination process is performed in step S8. That is, the verification result determination means 7 outputs a determination result indicating that there is a mismatch. Specifically, it is preferable to output the state of mismatch to a display device, printer, or the like so that the operator can clearly see what kind of mismatch has occurred.

If the corresponding unit information is not detected in step S3, this indicates that the cell corresponding to the cell in the netlist storage means 2 has not been found in the cell information storage means 1. This indicates that a mistake was made when creating the netlist, such as using a cell other than the cell library prepared in the cell information storage means 1 or writing a wrong cell name. In addition, if it is determined that there is a mismatch in step S6, there may be a mistake such as using an input/output terminal name different from the input/output terminal name defined in the cell library when creating the netlist, or incorrectly specifying the attributes of the input/output terminal. This indicates that this has occurred. In this way, if an error occurs in the correspondence between the cell information and the netlist, such an error can be automatically recognized by the output from the verification result determining means 7. If the verification result determination means 7 does not output a mismatch determination, it is verified that there is no problem in the correspondence between the cell information and the netlist, and the reliability of the mask pattern created based on this is improved. do.

The above description is based on embodiments illustrating the present invention.
The present invention is not limited to this embodiment, and can be implemented in various other ways.

It should be noted that the data in FIGS. 2 and 5 show simple models for convenience of explanation, and are not practically meaningful data.

〔Effect of the invention〕

As described above, according to the verification device of the present invention, since the input/output terminal names and input/output terminal attribute information are compared between the cell information and the netlist, the It becomes possible to automatically verify the correspondence between information and a netlist.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a verification device according to the present invention, FIG. 2 is a diagram showing an example of data corresponding to one unit of information in the cell information storage means shown in FIG. 1, and FIG. Second
4 is a diagram showing an example of the cell configuration of a semiconductor integrated circuit having a hierarchical structure. FIG. 5 is a conceptual diagram of a cell corresponding to the data shown in the figure. FIG.
FIG. 6 is a conceptual diagram of a cell corresponding to the data shown in FIG. 5, and FIG. 7 is a flowchart showing the operating procedure of the apparatus shown in FIG. 1. DESCRIPTION OF SYMBOLS 1... Cell information storage means, 2... Netlist storage means, 3... Unit information extraction means, 4... Unit information search means, 5... Common information extraction means, 6... Common Information collation means, 7...Verification result determination means, 0100-C3
00...Cell. Patent applicant: Dai Nippon Printing Co., Ltd. Applicant's agent: Patent attorney Hiroshi Shimura
O0 BODY 750 80
PORT A O50/N
POLYPORT B030) ~ POLY PORT C150400UT AL2 Cicada 2 (0,0) Grasshopper 3 (2) CELL C220A, B:C NAND C227, B:B2/NV
C222B2: C Guan 6 figure

Claims (1)

[Claims] A cell name for specifying a cell, an input/output terminal name for specifying an input/output terminal provided for this cell, and an input/output terminal for specifying the position of the input/output terminal. position information, input/output terminal layer information for specifying the wiring layer used by the input/output terminal, and input/output terminal attribute information for specifying whether the input/output terminal is an input terminal or an output terminal. , is defined as the unit information for one cell, and the cell information obtained by defining this unit information for multiple cells is prepared, and the cell name to identify the cell and the input provided for this cell are prepared. The input/output terminal name for specifying the output terminal, the input/output terminal attribute information for specifying whether the input/output terminal is an input terminal or an output terminal, and the mutual connection status of lower cells. Define inter-cell connection information shown as unit information for one cell, prepare a netlist obtained by defining this unit information for a plurality of cells, , a verification device for verifying the correspondence between the cell information and the netlist when designing a mask pattern for a semiconductor integrated circuit, comprising: a cell information storage means for storing the cell information; and a cell information storage means for storing the netlist. netlist storage means for extracting unit information for an arbitrary cell from the netlist storage means; and a cell name that is the same as the cell name related to the unit information extracted by the unit information extraction means. unit information retrieval means for searching the cell information storage means for unit information having the unit information extracted by the unit information extraction means;
common information extraction means for extracting input/output terminal names and input/output terminal attribute information; and input/output terminal names and input/output terminal attribute information extracted by the common information extraction means into units searched by the unit information searching means. common information matching means for matching the input/output terminal name and input/output terminal attribute information in the information; and when unit information having the same cell name cannot be retrieved by the unit information searching means, or the common information matching means 1. A verification device for verifying data for mask pattern design of a semiconductor integrated circuit, comprising: verification result determination means for outputting a determination result indicating that there is a mismatch in the correspondence relationship when the verification results obtained by the above do not match.