JPH04225536A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPH04225536A JPH04225536A JP41520290A JP41520290A JPH04225536A JP H04225536 A JPH04225536 A JP H04225536A JP 41520290 A JP41520290 A JP 41520290A JP 41520290 A JP41520290 A JP 41520290A JP H04225536 A JPH04225536 A JP H04225536A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- compound semiconductor
- substrate
- thermal expansion
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 150000001875 compounds Chemical class 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000010931 gold Substances 0.000 claims description 12
- 238000002844 melting Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 238000005476 soldering Methods 0.000 abstract description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 238000007747 plating Methods 0.000 description 6
- 239000010953 base metal Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- -1 GaAs compound Chemical class 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、ＧａＡｓ電界効果トラ
ンジスタ（以下、ＦＥＴという）などの化合物半導体装
置の半導体基板と容器（パッケージ）との接続方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting a semiconductor substrate of a compound semiconductor device such as a GaAs field effect transistor (hereinafter referred to as FET) to a container (package).
【０００２】0002
【従来の技術】ＧａＡｓ電界効果トランジスタは、Ｇａ
Ａｓ半導体からなる基板の表面にゲート・ソース・ドレ
インの電極が作成され、この基板の裏面は裏面金属膜を
介してヒートシンク、チップキャリアなどのパッケージ
に接続される。この裏面金属層は、基板の表面とバイア
ホールを介して電気的に接続されていることもある。[Prior Art] A GaAs field effect transistor is a GaAs field effect transistor.
Gate, source, and drain electrodes are formed on the front surface of a substrate made of an As semiconductor, and the back surface of this substrate is connected to a package such as a heat sink or a chip carrier through a back metal film. This back metal layer may be electrically connected to the front surface of the substrate via a via hole.
【０００３】裏面金属層は、高い電気伝導率と熱伝導率
が求められるため金（Ａｕ）がその主成分として用いら
れる。また、この裏面金属層は、数μｍ以上の比較的厚
い膜厚を必要とされるため、電気めっき法で作成される
。裏面金属層とパッケージとの接続は、はんだ付け、す
なわち３００℃程度の温度で融解する低融点金属をパッ
ケージ表面上で加熱融解し、融解面に裏面金属層を押し
当てたまま冷却し、低融点金属を固化させることで行う
。[0003] Gold (Au) is used as the main component of the back metal layer because it is required to have high electrical conductivity and high thermal conductivity. Furthermore, this back metal layer requires a relatively thick film thickness of several μm or more, and is therefore created by electroplating. The back metal layer and the package are connected by soldering, that is, a low melting point metal that melts at a temperature of about 300°C is heated and melted on the package surface, and the back metal layer is cooled while being pressed against the molten surface. This is done by solidifying the metal.
【０００４】0004
【発明が解決しようとする課題】しかしながら、このよ
うなはんだ付けを行った場合に半導体基板が反るという
問題がある。とくに、高電力を出力するＦＥＴの場合は
、基板寸法が大きくなるためこの反りはますます顕著と
なる。反りが生じた場合、はんだ付けの低融点金属層の
厚みが周辺部で部分的に厚くなり、熱抵抗の増大および
電気抵抗の増大を招く。また、反りがより顕著な場合、
癖開性を有する半導体基板が破壊される、また、反りの
応力のため圧電性を生ずるような半導体基板をもちいた
場合は正常な動作が不可能となる。[Problems to be Solved by the Invention] However, when such soldering is performed, there is a problem that the semiconductor substrate warps. Particularly in the case of FETs that output high power, this warpage becomes more and more noticeable as the board size increases. When warpage occurs, the thickness of the soldered low-melting point metal layer becomes partially thicker at the periphery, leading to an increase in thermal resistance and an increase in electrical resistance. Also, if the warpage is more pronounced,
If a semiconductor substrate that has a tendency to open is destroyed, or if a semiconductor substrate that produces piezoelectricity due to the stress of warping is used, normal operation will be impossible.
【０００５】本発明の目的は、パッケージへのはんだ付
け時に生じるこのような反りを防ぐ半導体基板とパッケ
ージの接続方法を提供することにある。An object of the present invention is to provide a method for connecting a semiconductor substrate and a package that prevents such warping that occurs during soldering to the package.
【０００６】[0006]
【問題点を解決するための手段】本発明の発明者は、こ
のような反りが化合物半導体基板と低融点金属層との熱
膨張率の相違により生ずるものであるとの観点から、こ
れらの間に化合物半導体基板の熱膨張係数より小さい熱
膨張係数を有する金属膜を介在させることによりこのよ
うな反りを防止できるとの着想に至った。[Means for Solving the Problems] The inventor of the present invention, from the viewpoint that such warpage is caused by the difference in thermal expansion coefficient between the compound semiconductor substrate and the low melting point metal layer, We came up with the idea that such warpage can be prevented by interposing a metal film having a thermal expansion coefficient smaller than that of the compound semiconductor substrate.
【０００７】すなわち、本発明による化合物半導体装置
の製造方法は、化合物半導体からなる基板の一方の主面
上に化合物半導体装置を構成する複数の電極を形成する
第１の工程、該基板の他方の主面上に前記化合物半導体
よりも熱膨張率の小さい第１の金属からなる第１の金属
膜を形成する第２の工程、該第１の金属膜上に前記化合
物半導体よりも熱膨張率の大きい第２の金属からなる第
２の金属膜を形成する
第３の工程、および、前記化合物半導体よりも熱膨張率
の大きい金属からなる金属を融解し前記基板を保持する
容器に該基板を固定する第４の工程を含むことを要旨す
るものである。That is, the method for manufacturing a compound semiconductor device according to the present invention includes a first step of forming a plurality of electrodes constituting the compound semiconductor device on one main surface of a substrate made of a compound semiconductor; a second step of forming a first metal film made of a first metal having a coefficient of thermal expansion smaller than that of the compound semiconductor on the main surface; a third step of forming a second metal film made of a larger second metal, and fixing the substrate in a container that holds the substrate by melting the metal made of a metal having a larger coefficient of thermal expansion than the compound semiconductor; The gist of this is that it includes a fourth step of.
【０００８】また、前記第１の金属がモリブデン（Ｍｏ
）またはタングステン（Ｗ）であり、前記第２の金属が
金（Ａｕ）であること、前記第１の金属の厚みは前記第
２の金属の厚みの２％以上であることが望ましい。[0008] Further, the first metal may be molybdenum (Mo
) or tungsten (W), the second metal is gold (Au), and the thickness of the first metal is preferably 2% or more of the thickness of the second metal.
【０００９】[0009]
【作用】このように第１の金属膜と第２の金属膜を積層
することで、重ね合わせた層状の複合金属の積層方向に
平行な方向の熱膨張係数αおよび弾性率Ｅｃは、次の式
で表わせる。
α＝α２＋（α１−α２）Ｖ１Ｅ１／ＥｃＥｃ＝Ｅ１Ｖ
１＋Ｅ２Ｖ２
ここでＥは弾性率、Ｖは金属膜の体積率であり、Ｖ１＋
Ｖ２＝１で規格化される。添字の１、２はそれぞれ第１
、第２の金属膜を示す。[Operation] By laminating the first metal film and the second metal film in this way, the coefficient of thermal expansion α and modulus of elasticity Ec in the direction parallel to the lamination direction of the laminated composite metal are as follows. It can be expressed by a formula. α=α2+(α1-α2)V1E1/EcEc=E1V
1+E2V2 Here, E is the elastic modulus, V is the volume fraction of the metal film, and V1+
It is normalized by V2=1. Subscripts 1 and 2 are the first
, indicates the second metal film.
【００１０】したがって、α１＜α２の場合、Ｖ２Ｅ２
／Ｅｃは正であるから、層状の複合金属の熱膨張係数α
はα２より小さくなる。したがって、実質的に裏面金属
層の熱膨張係数は小さくなり、半導体基板との差が低減
でき、反りを防ぐことができる。[0010] Therefore, if α1<α2, V2E2
/Ec is positive, so the thermal expansion coefficient α of the layered composite metal
becomes smaller than α2. Therefore, the coefficient of thermal expansion of the back metal layer becomes substantially smaller, the difference from the semiconductor substrate can be reduced, and warping can be prevented.
【００１１】[0011]
【実施例】以下本発明の実施例であるＧａＡｓ電力用Ｆ
ＥＴの製造工程を図１を用いて説明する。[Example] The following is a GaAs power F as an example of the present invention.
The manufacturing process of ET will be explained using FIG.
【００１２】ＧａＡｓ化合物半導体からなる厚さ４００
μｍの基板１の表面上に櫛型ゲート電極構造を有するゲ
ート電極２と、ソース・ドレイン電極３を作成する。基
板上の１素子の大きさは長さ２ｍｍ、幅０．５ｍｍであ
る。
基板部分の熱抵抗を低減するために基板を３０μｍの厚
さになるまでラッピングにより薄くする。[0012] A thickness of 400 mm made of GaAs compound semiconductor.
A gate electrode 2 having a comb-shaped gate electrode structure and a source/drain electrode 3 are formed on the surface of a substrate 1 having a thickness of μm. The size of one element on the substrate is 2 mm in length and 0.5 mm in width. To reduce the thermal resistance of the substrate portion, the substrate is thinned by lapping to a thickness of 30 μm.
【００１３】その後、めっき下地金属層４として、Ｔｉ
（５００Å）／Ｗ（５０００Å）／Ａｕ（３０００Å）
を順次基板裏面上にスパッタにより成膜する。Ｗ（タン
グステン）の線膨張係数は４．６×１０＾−６（１／℃
）であり、ＧａＡｓの線膨張係数６．８６×１０＾−６
（１／℃）よりも小さい。[0013] After that, Ti is used as the plating base metal layer 4.
(500Å)/W(5000Å)/Au(3000Å)
are successively deposited on the back surface of the substrate by sputtering. The linear expansion coefficient of W (tungsten) is 4.6×10^-6 (1/℃
), and the linear expansion coefficient of GaAs is 6.86×10^-6
(1/℃).
【００１４】めっき下地金属層４上にＡｕ（金）からな
る厚さ２０μｍのめっき金属層５を電気めっきにより作
成する。Ａｕ（金）の線膨張係数は１４．１×１０＾−
６（１／℃）であり、ＧａＡｓのそれよりも大きい。A plating metal layer 5 made of Au (gold) and having a thickness of 20 μm is formed on the plating base metal layer 4 by electroplating. The linear expansion coefficient of Au (gold) is 14.1×10^-
6 (1/°C), which is larger than that of GaAs.
【００１５】金属（金めっき銅板）からなるチップキャ
リア６を３００℃に加熱し、その表面にＡｕＳｎはんだ
（プリフォーム厚さ：３０μｍ）合金７を融解し、めっ
き金属層５を融着することでチップキャリア５上に基板
１を固定する。By heating the chip carrier 6 made of metal (gold-plated copper plate) to 300° C., melting the AuSn solder (preform thickness: 30 μm) alloy 7 on its surface and fusing the plated metal layer 5. A substrate 1 is fixed on a chip carrier 5.
【００１６】以上の実施例により作成した場合、反りは
基板の長さ方向（２ｍｍ）に対して約１０μｍとなり、
ＦＥＴの動作にほとんど影響を与えない。なお、Ｗの代
わりに線膨張係数が５．０×１０＾−６（１／℃）であ
るＭｏ（モリブデン）等を用いても同様の効果が得られ
る。When produced according to the above embodiment, the warpage is approximately 10 μm in the length direction (2 mm) of the substrate.
It has almost no effect on the operation of the FET. Note that the same effect can be obtained by using Mo (molybdenum) or the like having a linear expansion coefficient of 5.0×10^-6 (1/° C.) instead of W.
【００１７】［比較例］上記実施例においてめっき下地
金属層４を、Ｔｉ（５００Å）／Ａｕ（３０００Å）と
してＷ（タングステン）層を設けない場合、約２０μｍ
の反りが生じ、ＦＥＴの動作に支障をきたすことがしば
しば生じた。[Comparative Example] In the above example, when the plating base metal layer 4 is Ti (500 Å)/Au (3000 Å) and no W (tungsten) layer is provided, the thickness is about 20 μm.
This often caused warping, which interfered with the operation of the FET.
【００１８】[0018]
【発明の効果】以上説明したように、本発明による化合
物半導体装置の製造方法は、化合物半導体からなる基板
の一方の主面上に化合物半導体装置を構成する複数の電
極を形成する第１の工程、該基板の他方の主面上に前記
化合物半導体よりも熱膨張率の小さい第１の金属からな
る第１の金属膜を形成する第２の工程、該第１の金属膜
上に前記化合物半導体よりも熱膨張率の大きい第２の金
属からなる第２の金属膜を形成する第３の工程、および
、前記化合物半導体よりも熱膨張率の大きい金属からな
る金属を融解し前記基板を保持する容器に該基板を固定
する第４の工程を含むことを要旨するものである。As explained above, the method for manufacturing a compound semiconductor device according to the present invention includes a first step of forming a plurality of electrodes constituting a compound semiconductor device on one main surface of a substrate made of a compound semiconductor. a second step of forming a first metal film made of a first metal having a coefficient of thermal expansion smaller than that of the compound semiconductor on the other main surface of the substrate; a third step of forming a second metal film made of a second metal having a larger coefficient of thermal expansion than the compound semiconductor; and melting the metal made of a metal having a larger coefficient of thermal expansion than the compound semiconductor and holding the substrate. The gist of the method is to include a fourth step of fixing the substrate to a container.
【００１９】したがって、容器へのはんだ付け時に化合
物半導体基板の反りを生じることなく、熱抵抗の増大ま
たは電気抵抗が増大することはない。加えて、癖開性を
有する半導体基板が破壊されることもなく、また、反り
の応力のため圧電性を生ずるような半導体基板をもちい
た場合でも半導体装置の正常な動作が可能となる。[0019] Therefore, the compound semiconductor substrate does not warp during soldering to the container, and the thermal resistance or electrical resistance does not increase. In addition, a semiconductor substrate having a tendency to crack is not destroyed, and the semiconductor device can operate normally even when a semiconductor substrate that produces piezoelectricity due to the stress of warping is used.
【図１】本発明の実施例であるＦＥＴの製造工程を説明
するための断面図である。FIG. 1 is a cross-sectional view for explaining the manufacturing process of an FET that is an embodiment of the present invention.
１…化合物半導体からなる基板、２…ゲート電極、３…
ソース・ドレイン電極、４…めっき下地金属層、５…め
っき金属層、６…チップキャリア（容器）、７…ＡｕＳ
ｎはんだ合金。1... Substrate made of a compound semiconductor, 2... Gate electrode, 3...
Source/drain electrode, 4... Plating base metal layer, 5... Plating metal layer, 6... Chip carrier (container), 7... AuS
n solder alloy.
Claims (2)
面上に化合物半導体装置を構成する複数の電極を形成す
る第１の工程、該基板の他方の主面上に前記化合物半導
体よりも熱膨張率の小さい第１の金属からなる第１の金
属膜を形成する第２の工程、該第１の金属膜上に前記化
合物半導体よりも熱膨張率の大きい第２の金属からなる
第２の金属膜を形成する第３の工程、および、前記化合
物半導体よりも熱膨張率の大きい金属からなる金属を融
解し前記基板を保持する容器に該基板を固定する第４の
工程を含むことを特徴とする化合物半導体装置の製造方
法。1. A first step of forming a plurality of electrodes constituting a compound semiconductor device on one main surface of a substrate made of a compound semiconductor; a second step of forming a first metal film made of a first metal having a small coefficient of thermal expansion; a second metal film made of a second metal having a larger coefficient of thermal expansion than the compound semiconductor on the first metal film; The method is characterized by comprising a third step of forming a film, and a fourth step of melting a metal made of a metal having a higher coefficient of thermal expansion than the compound semiconductor and fixing the substrate to a container that holds the substrate. A method for manufacturing a compound semiconductor device.
またはタングステン（Ｗ）であり、前記第２の金属が金
（Ａｕ）であることを特徴とする請求項１記載の化合物
半導体装置の製造方法。2. The first metal is molybdenum (Mo).
2. The method for manufacturing a compound semiconductor device according to claim 1, wherein the second metal is gold (Au) or tungsten (W).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41520290A JPH04225536A (en) | 1990-12-27 | 1990-12-27 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41520290A JPH04225536A (en) | 1990-12-27 | 1990-12-27 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04225536A true JPH04225536A (en) | 1992-08-14 |
Family
ID=18523592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP41520290A Pending JPH04225536A (en) | 1990-12-27 | 1990-12-27 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04225536A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006517054A (en) * | 2002-11-27 | 2006-07-13 | フリースケール セミコンダクター インコーポレイテッド | GaAs thin die with copper backside metal structure |
-
1990
- 1990-12-27 JP JP41520290A patent/JPH04225536A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006517054A (en) * | 2002-11-27 | 2006-07-13 | フリースケール セミコンダクター インコーポレイテッド | GaAs thin die with copper backside metal structure |
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