JPH04222009A - Data processor - Google Patents

Abstract

PURPOSE:To prevent electric power from being uselessly consumed during the execution of data processing by forming or supplying clock signals only during the period of access to a resource and the execution of data processing CONSTITUTION:When bus use is permitted, a clock signal is generated and supplied to a data processing part, or an external clock signal is supplied to the data processing part, and at the time of completing data processing, the formation and supply of the clock signal is stopped, or the supply of the external clock signal is stopped. Power is supplied to the data processing part at the time of permitting bus use, and at the time of completing the data processing, power supply is stopped.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device that shares resources such as memory and I/O devices with other devices, and can access the resources by obtaining permission to use a bus.

0002

2. Description of the Related Art FIG. 1 is a block diagram showing the configuration of a data processing system consisting of a plurality of data processing devices each having a bus master function. In the figure, 1 is a data processing device, which shares resources 3 such as memory and I/O devices with each other, and each data processing device 1 is connected via a bus 4, which is a path for data, addresses, various control signals, etc. resource 3
access. The bus arbiter 2 is connected to each data processing device 1.
arbitrates the use of bus 4. The data processing request signal line 5 transmits a request signal for starting data processing from various devices (not shown) such as a CPU constituting the data processing system to each data processing device 1. A bus request signal line 6 transmits a request signal for the right to use the bus 4 from the data processing device 1 to the bus arbiter 2. A bus permission signal line 7 transmits a permission signal for use of the bus 4 from the bus arbiter 2 to the data processing device 1. The data processing device 1 that has been given a permission signal to use the bus 4 from the bus arbiter 2 can access the resource 3 .

FIG. 5 is a block diagram showing the configuration of a conventional data processing device 1. As shown in FIG. The bus control section 11 exchanges signals with the outside via the data processing request signal line 5, the bus request signal line 6, and the bus permission signal line 7, and controls each section inside the device. The clock generation unit 12 generates a clock and sends the clock signal to the data processing unit 13 via the clock signal line 10.
give to The bus control section 11 supplies a data processing start instruction signal to the data processing section 13 via the data processing start signal line 20 in response to a bus use permission signal given from the bus arbiter 2 . The data processing unit 13 accesses the resource 3 in response to a data processing start request signal and a data processing start instruction signal applied via the data processing request signal line 5, and processes data in synchronization with a clock signal. The data processing end signal line 8 transmits a data processing end signal from the data processing section 13 to the bus control section 11.

Next, the data processing operation of the data processing apparatus 1 having the above configuration will be explained. In Figure 1,
Data processing device 1 attempting to access resource 3 outputs a signal to bus arbiter 2 via bus request signal line 6 . The bus arbiter 2 outputs a usage permission signal to the data processing device 1 via the bus permission signal line 7, but when receiving requests for the right to use the bus 4 from multiple data processing devices 1, 1, etc. at the same time, which It is determined whether the data processing device 1 is to be allowed to use the bus 4, and a use permission signal is given via the bus permission signal line 7 to the data processing device 1 to which access is permitted. The data processing device 1 that has received the bus use permission signal accesses the resource 3 and starts data processing. During this time, other data processing devices 1 do not process data. When the data processing is completed, the data processing device 1 cancels the request signal for the right to use the bus 4. In FIG. 5, when a signal requesting data processing is input from outside the device, the bus control unit 11 requests the bus arbiter 2 for the right to use the bus 4. When permission to use the bus 4 is obtained, the bus control unit 11 controls the data processing unit 13
Outputs an instruction signal to start data processing. The data processing unit 13 that receives this signal accesses the resource 3 via the bus 4 and starts data processing. When the data processing is completed, the data processing section 13 outputs a completion signal to the bus control section 11, and upon receiving this signal, the bus control section 11 cancels the bus request signal to the bus arbiter 2. The clock generation section 12 always generates a clock signal and supplies it to the data processing section 13 while the data processing system is activated, regardless of whether the data processing device 1 is in operation or not.

[0005]

[Problems to be Solved by the Invention] As described above, the conventional data processing device always generates a clock and supplies it to the data processing section even when data processing is not being performed.
There is waste in power consumption for clock generation and power consumption due to input of the clock signal to the data processing section.

[0006] The present invention has been made in order to solve these problems, and is designed to stop clock generation when data processing is not performed, or stop supplying an external clock or power to the data processing section. The purpose of the present invention is to provide a data processing device that eliminates wasted power consumption.

[0007]

[Means for Solving the Problems] The data processing device of the present invention generates a clock signal and supplies it to the data processing section when permission to use the bus is obtained, or supplies an external clock signal to the data processing section. However, when the data processing is completed, the generation of the clock signal and the supply of the clock signal to the data processing section are stopped, or the supply of the external clock signal to the data processing section is stopped. Further, the data processing device of the present invention supplies power to the data processing unit and resets the data processing unit when permission to use the bus is obtained, and stops supplying power to the data processing unit when data processing is completed. It is characterized by

[0008]

[Operation] In the data processing device of the present invention, when bus use is permitted, the clock signal control section generates a clock signal and supplies it to the data processing section, or the clock signal control section supplies an external clock to the data processing section. The data processing unit accesses the resources via the bus and processes the data in synchronization with the clock signal. When the data processing is completed, the clock signal control section stops generating the clock signal and supplying the clock signal to the data processing section, or stops supplying the external clock signal to the data processing section. That is, the clock signal control section supplies a clock signal only while data processing is being performed. Further, in the data processing device of the present invention, when the use of the bus is permitted, the power control unit supplies power to the data processing unit to reset the data processing unit, and the data processing unit accesses resources via the bus. process the data. When the data processing is completed, the power control section stops supplying power to the data processing section. That is, the power control unit supplies power only while data processing is being performed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to figures showing embodiments thereof. FIG. 1 is a block diagram showing the configuration of a data processing system including a plurality of data processing devices each having a bus master function. In the figure, 1 is a data processing device, which shares resources 3 such as memory and I/O devices with each other, and each data processing device 1 is connected via a bus 4, which is a path for data, addresses, various control signals, etc. to access resource 3. The bus arbiter 2 arbitrates the use of the bus 4 by each data processing device 1. The data processing request signal line 5 transmits a request signal for starting data processing from various devices (not shown) such as a CPU constituting the data processing system to each data processing device 1. A bus request signal line 6 transmits a request signal for the right to use the bus 4 from the data processing device 1 to the bus arbiter 2. A bus permission signal line 7 transmits a permission signal for use of the bus 4 from the bus arbiter 2 to the data processing device 1. The data processing device 1 that has been given a permission signal to use the bus 4 from the bus arbiter 2 can access the resource 3 . Next, the data processing operation will be explained. Data processing device 1 attempting to access resource 3 outputs a signal to bus arbiter 2 via bus request signal line 6 . The bus arbiter 2 outputs a usage permission signal to the data processing device 1 via the bus permission signal line 7, but when receiving requests for the right to use the bus 4 from multiple data processing devices 1, 1, etc. at the same time, which It is determined whether the data processing device 1 is to be allowed to use the bus 4, and a use permission signal is given via the bus permission signal line 7 to the data processing device 1 to which access is permitted. The data processing device 1 that has received the bus use permission signal accesses the resource 3 and starts data processing. During this time, other data processing devices 1 do not process data. When the data processing is completed, the data processing device 1 cancels the request signal for the right to use the bus 4.

FIG. 2 shows a first diagram of a data processing apparatus according to the present invention.
FIG. 2 is a block diagram showing the configuration of an embodiment. Bus control section 11
It exchanges signals with the outside via a data processing request signal line 5, a bus request signal line 6, and a bus permission signal line 7, and controls each section inside the device. The clock generation section 12 generates a clock in response to a clock generation request signal given from the bus control section 11 via the clock generation request signal line 9, and supplies the clock signal to the data processing section 13 via the clock signal line 10. . The bus control section 11 supplies a data processing start instruction signal to the data processing section 13 via the data processing start signal line 20 in response to a bus use permission signal given from the bus arbiter 2 . The data processing unit 13 accesses the resource 3 in response to a data processing start request signal and a data processing start instruction signal applied via the data processing request signal line 5, and processes data in synchronization with a clock signal. The data processing end signal line 8 transmits a data processing end signal from the data processing section 13 to the bus control section 11.

Next, the data processing operation will be explained. When a signal requesting data processing is input from outside the device, the bus control section 11 requests the bus arbiter 2 for the right to use the bus 4. When permission to use the bus 4 is obtained, the bus control unit 11
outputs a clock generation request signal to the clock generation section 12, and outputs an instruction signal to the data processing section 13 to start data processing. Upon receiving the clock generation request signal, the clock generation section 12 generates a clock and supplies it to the data processing section 13 . When a signal is input via each of the data processing request signal line 5, clock signal line 10, and data processing start request signal line 20, the data processing unit 13 accesses the resource 3 via the bus 4 and starts data processing. do.

[0012] When the data processing is completed, the data processing section 1
3 outputs an end signal to the bus control unit 11, and upon receiving this signal, the bus control unit 11 issues a clock generation request signal to the clock generation unit 12, a bus request signal to the bus arbiter 2, and a data processing start signal to the data processing unit 13. Withdraw the instruction signal. The clock generation unit 19 stops generating the clock. The clock generation unit 12 receives a bus usage right request from the bus arbiter 2, and the data processing unit 1
Since the clock is generated only during the period when the device 3 is actually operating, there is no wasted power consumption. Further, since no clock is supplied when the data processing section 13 is not operating, power consumption in the data processing section 13 is not wasted.

FIG. 3 shows a second configuration of the data processing device according to the present invention.
FIG. 2 is a block diagram showing the configuration of an embodiment. In the figure, the same numbers are given to the same or corresponding parts as in the first embodiment, and the explanation thereof will be omitted. The external clock signal line 15 provides the clock control unit 14 with an external clock generated outside the device. When the clock control section 14 receives a clock generation request signal from the bus control section 11, it supplies an external clock provided via an external clock signal line 15 to the data processing section 13.

Next, the data processing operation will be explained. When a signal requesting data processing is input from outside the device, the bus control section 11 requests the bus arbiter 2 for the right to use the bus 4. When permission to use the bus 4 is obtained, the bus control unit 11 outputs a clock generation request signal to the clock control unit 14 and outputs an instruction signal to the data processing unit 13 to start data processing. Upon receiving the clock generation request signal, the clock control section 14 supplies an external clock supplied from outside the device to the data processing section 13 . When a signal is input via each of the data processing request signal line 5, clock signal line 10, and data processing start request signal line 20, the data processing unit 13 accesses the resource 3 via the bus 4 and starts data processing. do.

[0015] When the data processing is completed, the data processing section 1
3 outputs an end signal to the bus control unit 11, and upon receiving this signal, the bus control unit 11 issues a clock generation request signal to the clock control unit 14, a bus request signal to the bus arbiter 2, and a data processing start signal to the data processing unit 13. Withdraw the instruction signal. The clock control unit 14 stops supplying the external clock to the data processing unit 13. Since the clock control section 14 does not supply an external clock when the data processing section 13 is not operating, power consumption in the data processing section 13 is not wasted.

FIG. 4 is a block diagram showing the configuration of a third embodiment of a data processing apparatus according to the present invention. In the figure, the same numbers are given to the same or corresponding parts as in the first embodiment, and the explanation thereof will be omitted. The power control unit 16 supplies power supplied from outside the device via a power line 17 to the data processing unit 13 via the power line 17 . The power supply request signal line 19 transmits a signal instructing the data processing section 13 to supply power and input a reset signal to the power supply control section 16 .

Next, the data processing operation will be explained. When a signal requesting data processing is input from outside the device, the bus control section 11 requests the bus arbiter 2 for the right to use the bus 4. When permission to use the bus 4 is obtained, the bus control unit 11 outputs a power supply request signal to the power supply control unit 16, and after a predetermined time has elapsed, outputs an instruction signal to the data processing unit 13 to start data processing. When the power supply control unit 16 receives the power supply request signal, it supplies power supplied from outside the device to the data processing unit 13, and then outputs a reset signal. After the data processing unit 13 is supplied with power, it is reset by a reset signal, and when a request signal for starting data processing is input, it accesses the resource 3 via the bus 4 and starts data processing.

When the data processing is completed, the data processing section 1
3 outputs an end signal to the bus control unit 11, and upon receiving this signal, the bus control unit 11 issues a power supply request signal to the power supply control unit 16, a bus request signal to the bus arbiter 2, and a data processing start signal to the data processing unit 13. Withdraw the instruction signal. The power control unit 16 stops supplying power to the data processing unit 13. Since the power control unit 16 does not supply power when the data processing unit 13 is not operating, power consumption in the data processing unit 13 is not wasted.

[0019]

As described above, the data processing device of the present invention does not generate a clock when not processing data, and does not supply externally supplied clocks and power to the data processing unit. This has the excellent effect of eliminating wasted power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data processing system including a plurality of data processing devices.

FIG. 2 is a block diagram showing the configuration of a first embodiment of a data processing device according to the present invention.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the data processing device according to the present invention.

FIG. 4 is a block diagram showing the configuration of a third embodiment of a data processing device according to the present invention.

FIG. 5 is a block diagram showing the configuration of a conventional data processing device.

[Explanation of symbols]

1 Data processing device 2 Bus arbiter 3 Resources 4 Bus 5 Data processing request signal line 6 Bus request signal line 7 Bus permission signal line 8 Data processing end signal line 9 Clock generation request signal line 10 Clock signal line 11 Bus control section 12 Clock generation section 13 Data processing section 14 Clock control section 15 External clock signal line 16 Power control section 17 Power line 18 Reset signal line 19 Power supply request signal line 20 Data processing start signal line

Claims (2)

[Claims] Claim 1: In a data processing device that shares resources with other devices and becomes capable of accessing the resources and processing data when the use of a bus connecting the resources is permitted, a clock signal is used. A data processing unit that processes data synchronously, and a clock signal control that supplies a clock signal to the data processing unit when permission to use the bus is obtained, and stops supplying the clock signal to the data processing unit when data processing is completed. A data processing device comprising: Claim 2: Processing data in a data processing device that shares resources with other devices and becomes capable of accessing resources and processing data when permission is granted to use a bus that connects the resources. and a power control unit that supplies power to the data processing unit to reset the data processing unit when permission to use the bus is obtained, and stops power supply to the data processing unit when data processing is completed. A data processing device comprising: