JPH04221864A - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JPH04221864A JPH04221864A JP2413322A JP41332290A JPH04221864A JP H04221864 A JPH04221864 A JP H04221864A JP 2413322 A JP2413322 A JP 2413322A JP 41332290 A JP41332290 A JP 41332290A JP H04221864 A JPH04221864 A JP H04221864A
- Authority
- JP
- Japan
- Prior art keywords
- junction
- layer
- semiconductor substrate
- semiconductor device
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 230000003287 optical effect Effects 0.000 title claims description 43
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000010949 copper Substances 0.000 claims description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 238000000034 method Methods 0.000 abstract description 19
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 3
- 238000009835 boiling Methods 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 39
- 238000007747 plating Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 8
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 239000007791 liquid phase Substances 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229920001296 polysiloxane Polymers 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
[発明の目的] [Purpose of the invention]
【0001】0001
【産業上の利用分野】本発明は、光センサー、光結合素
子(フォトカプラー)、発光素子を用いたパイロットラ
ンプなどから成る光源更に半導体受光素子と組合わせた
光信号伝達器などの光半導体装置に好適するものである
。[Industrial Application Field] The present invention is applicable to optical semiconductor devices such as optical signal transmitters that combine light sources such as optical sensors, optical coupling elements (photocouplers), and pilot lamps using light emitting elements, as well as semiconductor light receiving elements. It is suitable for
【0002】0002
【従来の技術】半導体素子の組立工程には、リードフレ
ーム即ち支持部を利用する方式が多用されており、材質
も鉄、鉄−ニッケル合金、これらの元素のクラッド材な
どが用いられており、最近では銅系から成るものも実用
化されている。2. Description of the Related Art In the assembly process of semiconductor devices, lead frames, that is, supporting parts, are often used, and materials such as iron, iron-nickel alloys, and cladding materials of these elements are used. Recently, copper-based materials have also been put into practical use.
【0003】しかも、前記組立工程に不可欠なボンディ
ング工程における金属細線との接合状態や、保護層とし
て機能する透明樹脂との接着状態の改良のために、銀や
金メッキ層を被着するのが一般的であり、銅系のそれで
も同様な処理を行っているものもある。Moreover, in order to improve the bonding condition with the thin metal wire in the bonding process that is essential to the assembly process and the bonding condition with the transparent resin that functions as a protective layer, it is common to apply a silver or gold plating layer. Some copper-based metals are also treated in the same way.
【0004】ところで光センサー、光結合素子(フォト
カプラー)、発光素子を用いたパイロットランプなどの
光源更に半導体受光素子と組合わせた光信号発生器など
の光半導体装置を図1に示した断面図により説明する。By the way, FIG. 1 is a cross-sectional view of an optical semiconductor device such as an optical sensor, an optical coupling element (photocoupler), a light source such as a pilot lamp using a light emitting element, and an optical signal generator combined with a semiconductor light receiving element. This is explained by:
【0005】前記の材料から構成する支持部は、エッチ
ング工程か金型を利用するプレス工程により製造するが
、前者においては、エッチング工程を行ってから全面に
銀か金メッキ層を被覆し、後者にあっては、部分的に銀
や金メッキ層を被覆したものを使用する。[0005] The support part made of the above-mentioned material is manufactured by an etching process or a pressing process using a mold. In the former, the entire surface is coated with a silver or gold plating layer after the etching process, and in the latter If so, use one that is partially coated with a silver or gold plating layer.
【0006】メッキ層の厚さとしては、銀が1μm〜3
μm、金が0.5μm位であり、更に下地として設置す
る銅メッキ層即ち銅系部材の厚さは、約0.1μmであ
る。[0006] The thickness of the silver plating layer is 1 μm to 3 μm.
The thickness of gold is about 0.5 μm, and the thickness of the copper plating layer, that is, the copper-based member provided as a base, is about 0.1 μm.
【0007】図1では、支持部1及びアウターリード2
夫々の周囲にメッキ層3を表示しており、これに半導体
発光素子4を導電性接着剤5により重ねて固着する。In FIG. 1, a support portion 1 and an outer lead 2 are shown.
A plating layer 3 is displayed around each of them, and a semiconductor light emitting element 4 is overlaid and fixed to this using a conductive adhesive 5.
【0008】半導体発光素子4は、P+ 半導体層5に
液相成長法でP層6及びN層7を図2の断面図に示すよ
うに順次成長して半導体基板を形成し、両層により形成
するPN接合端部を半導体基板の側面に露出していわゆ
るメサ型とする。The semiconductor light emitting device 4 is formed by sequentially growing a P layer 6 and an N layer 7 on a P+ semiconductor layer 5 by a liquid phase growth method as shown in the cross-sectional view of FIG. 2 to form a semiconductor substrate. The PN junction end portion is exposed on the side surface of the semiconductor substrate to form a so-called mesa type.
【0009】また、半導体基板の表面と裏面を構成する
N層7及びP+ 層5に導電性金属からなる電極8、9
を設ける。Further, electrodes 8 and 9 made of conductive metal are provided on the N layer 7 and the P+ layer 5 that constitute the front and back surfaces of the semiconductor substrate.
will be established.
【0010】電極8とリード2の間には例えばAu製の
金属細線10をボンディング法により接合してから光透
過性封止樹脂(図示せず)を常法通り被覆して半導体発
光装置が得られる。A thin metal wire 10 made of, for example, Au is bonded between the electrode 8 and the lead 2 by a bonding method, and then a light-transmitting sealing resin (not shown) is coated in a conventional manner to obtain a semiconductor light-emitting device. It will be done.
【0011】光半導体装置の一種である光結合装置では
、支持部材にマウントする発光素子と受光素子間をフィ
ラーを含むシリコーンなどの絶縁物で構成するエンキャ
ップ材を充填被覆し、更にこれらを樹脂層により保護し
て外囲器とする手法が採られている。In an optical coupling device, which is a type of optical semiconductor device, the space between a light emitting element and a light receiving element mounted on a support member is filled and coated with an encap material made of an insulating material such as silicone containing a filler, and then these are coated with a resin. A method is adopted in which the material is protected by layers and used as an envelope.
【0012】0012
【発明が解決しようとする課題】下地のメッキ層として
銅系部材を備えた支持部または銅系材料からなる支持部
にマウントした光半導体装置を稼働した際、その近くに
銅をイオン化する要因があると電位差によりCu+ と
して電離し、電界によって負の電位側に引寄せられて、
金属性電気伝導層がPN接合と並列に形成する。[Problem to be Solved by the Invention] When operating an optical semiconductor device mounted on a support part having a copper-based member as an underlying plating layer or a support part made of a copper-based material, there are factors that ionize copper in the vicinity. When there is, it is ionized as Cu+ due to the potential difference, and is attracted to the negative potential side by the electric field,
A metallic electrically conductive layer is formed in parallel with the PN junction.
【0013】銅をイオン化する要因には、例えば光結合
装置外囲器内に設置するシリコーン内に添加するフィラ
ーなどが考えられる。[0013] Possible factors for ionizing copper include, for example, a filler added to silicone disposed within the optical coupler envelope.
【0014】このため、光半導体装置の稼働に必要な電
位が金属性電気伝導層に流れて所定の特性が得られない
現象が現われ、対策として銅系層のイオン化を防止する
ために例えばニッケルや金など被膜をメッキなどの手段
で被覆する手法が採られた。For this reason, a phenomenon occurs in which the potential necessary for the operation of the optical semiconductor device flows through the metallic electrically conductive layer, making it impossible to obtain the desired characteristics.As a countermeasure, for example, nickel or A method was adopted in which a film such as gold was coated by means such as plating.
【0015】しかし、厳しい価格競争におかれている半
導体産業にあっては、コストアップをもたらす前記手法
は問題にならざるを得ない。[0015] However, in the semiconductor industry, which is subject to severe price competition, the above-mentioned method of increasing costs inevitably becomes a problem.
【0016】本発明は、このような事情により成された
もので、銅系層を備えた支持部材に光半導体素子をマウ
ントしてPN接合と並列に金属性電気伝導層が形成され
ても、所定の特性が発揮できる光半導体装置を提供する
ことを目的とする。The present invention was made under these circumstances, and even if an optical semiconductor element is mounted on a support member provided with a copper-based layer and a metallic electrically conductive layer is formed in parallel with the PN junction, An object of the present invention is to provide an optical semiconductor device that can exhibit predetermined characteristics.
【0017】[発明の構成][Configuration of the invention]
【0018】[0018]
【課題を解決するための手段】銅系部材を備える支持部
と,前記支持部に重ねて固着しかつ銅系部材に近接して
配置する半導体基板と,前記半導体基板に形成するPN
接合と,前記半導体基板側面に露出するPN接合端部と
,前記PN接合端部を覆う絶縁物層と,前記積層体を被
覆する透明保護層に本発明に係わる光半導体装置の特徴
がある。[Means for Solving the Problems] A support portion including a copper-based member, a semiconductor substrate overlaid on and fixed to the support portion and disposed close to the copper-based member, and a PN formed on the semiconductor substrate.
The optical semiconductor device according to the present invention is characterized by a junction, a PN junction end exposed on the side surface of the semiconductor substrate, an insulating layer covering the PN junction end, and a transparent protective layer covering the laminate.
【0019】[0019]
【作用】本発明に係わる光半導体装置では、液相成長法
により導電型の違う層を半導体基板に順次重ねて生ずる
PN接合端を半導体基板の側壁に露出させ、かつ絶縁物
層により覆っている。[Function] In the optical semiconductor device according to the present invention, the PN junction end formed by sequentially stacking layers of different conductivity types on a semiconductor substrate using a liquid phase growth method is exposed on the side wall of the semiconductor substrate and covered with an insulating layer. .
【0020】このために、マウント用支持部に形成する
銅系部材に近い位置に前記半導体基板を配置しても、銅
系部材から発生したイオン化した金属がPN接合端付近
に付着することが防げる。For this reason, even if the semiconductor substrate is placed close to the copper-based member formed on the mounting support, ionized metal generated from the copper-based member can be prevented from adhering to the vicinity of the PN junction end. .
【0021】[0021]
【実施例】本発明に係わる一実施例を図3、図4及び図
5を参照して説明するが、理解を助けるために従来の技
術と同一の部品にも新番号を付ける。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 3, 4, and 5, and new numbers will be given to parts that are the same as those in the prior art to aid understanding.
【0022】図3に示すようにP+ 半導体基板15に
は、液相成長法によりP層16とN層17を順次重ねて
成長してPN接合18を形成し、その端部を側部に露出
していわゆるメサ型の半導体基板15を形成する。As shown in FIG. 3, on the P+ semiconductor substrate 15, a P layer 16 and an N layer 17 are sequentially grown by liquid phase growth to form a PN junction 18, and the ends thereof are exposed on the side. Thus, a so-called mesa-type semiconductor substrate 15 is formed.
【0023】露出したPN接合18端部には、厚さが約
0.1μm〜1.0μmの絶縁物層19をCVD法か過
酸化水素中での煮沸により設けてから組立工程に移行す
る。An insulating layer 19 having a thickness of about 0.1 μm to 1.0 μm is provided on the exposed end of the PN junction 18 by CVD or boiling in hydrogen peroxide, and then the assembly process begins.
【0024】組立工程は、リードフレーム20を利用す
る方式により行い、材質としては鉄、鉄−ニッケル、銅
または銅合金更にこれらの元素をクラッドしたクラッド
材料が使用できる。The assembly process is carried out using a lead frame 20, and the material may be iron, iron-nickel, copper, copper alloy, or a cladding material made of these elements.
【0025】リードフレーム20には全面メッキもしく
は部分メッキを施して厚さ1μm〜3μmの銀層か、厚
さ約0.5μmの金層を被着してボンディング工程にお
ける金属細線とのまたは保護層として被覆する透明樹脂
層の接着性を改善しており、このメッキ層の下地として
厚さが0.1μm程度の銅メッキ層即ち銅系部材を予め
形成する。The lead frame 20 is fully plated or partially plated and coated with a silver layer with a thickness of 1 μm to 3 μm or a gold layer with a thickness of about 0.5 μm to protect the thin metal wire during the bonding process or as a protective layer. A copper plating layer, that is, a copper-based member having a thickness of about 0.1 μm is previously formed as a base for this plating layer.
【0026】全面メッキか部分メッキの区分けは、リー
ドフレーム20の製造方法によるもので、エッチングに
よる際は全面に金型を使用するプレス工程前に部分メッ
キを施し、このような処理を施したリードフレーム20
のメッキ層に関する図3での記載は、各々を総称してメ
ッキ層21とする。The classification between full plating and partial plating depends on the manufacturing method of the lead frame 20. When etching is used, partial plating is applied to the entire surface before the pressing process using a mold, and the lead frame 20 is partially plated. frame 20
The descriptions in FIG. 3 regarding the plating layers are collectively referred to as plating layers 21.
【0027】導電型の違う液相成長層を重ねて形成する
PN接合18を備え、これを絶縁物層19で覆った発光
素子即ち半導体素子は、銅系部材を下地とするメッキ層
21の近くに導電性接着剤22や金共晶を介して固着し
、更に図示していないフィラーを含有した透明樹脂を被
覆して外囲器を構成して光半導体装置23を製造する。A light-emitting device, that is, a semiconductor device, is provided with a PN junction 18 formed by overlapping liquid-phase growth layers of different conductivity types, and is covered with an insulating layer 19, near a plating layer 21 whose base is a copper-based material. The optical semiconductor device 23 is manufactured by adhering to the conductive adhesive 22 or gold eutectic and further covering it with a transparent resin containing a filler (not shown) to form an envelope.
【0028】なお、P+ 層15とN層17の露出面に
は、導電性金属層を被覆して電極24、25を形成し、
さらに電極24とリードフレームに形成するアウターリ
ード間に金属細線例えば金線をボンディング(図1参照
)により電気的に接続して他の電子機器との電気的接続
に備える。Note that the exposed surfaces of the P+ layer 15 and the N layer 17 are coated with a conductive metal layer to form electrodes 24 and 25.
Further, a thin metal wire, such as a gold wire, is electrically connected between the electrode 24 and an outer lead formed on the lead frame by bonding (see FIG. 1) to prepare for electrical connection with other electronic equipment.
【0029】光半導体装置の一種である光結合素子にお
いては、マウントされる光半導体素子が受動素子と能動
素子であり、また両者間にシリコーンなどを埋設してか
ら樹脂封止工程に移行するが、光半導体装置23の稼働
時における銅イオンの挙動を図4aに、また図4bに一
般的な回路接続を明らかにした。In an optical coupling device, which is a type of optical semiconductor device, the optical semiconductor device to be mounted is a passive device and an active device, and silicone or the like is buried between the two before proceeding to the resin sealing process. The behavior of copper ions during operation of the optical semiconductor device 23 is shown in FIG. 4a, and the general circuit connection is shown in FIG. 4b.
【0030】図4aに示すようにCuが析出するのは、
導電性接着剤層22即ち導電性エポキシ樹脂を約150
℃〜200℃の高温状態で硬化して光半導体素子23を
リードフレーム20にマウントする際と、ボンディング
により電極を形成する時の高温状態200℃〜350℃
と、金共晶によるマウント時の450℃の高温状態であ
る。As shown in FIG. 4a, Cu precipitates because
The conductive adhesive layer 22, that is, the conductive epoxy resin
When mounting the optical semiconductor element 23 on the lead frame 20 by curing at a high temperature of 200°C to 200°C, and when forming electrodes by bonding, a high temperature state of 200°C to 350°C
This is the high temperature state of 450° C. when mounted using gold eutectic.
【0031】このように析出したCuがイオン化するの
は、光半導体装置23の外囲器を構成する透明樹脂に添
加されたフィラー、更にリードフレームを伝わって進入
した化学的物質から成る電解質例えばメッキ処理溶液が
考えられる。The Cu deposited in this manner is ionized by the filler added to the transparent resin constituting the envelope of the optical semiconductor device 23, and also by the electrolyte made of chemical substances that has entered through the lead frame, such as plating. Treatment solutions are considered.
【0032】しかも、光半導体装置23は、図4bに示
すような抵抗26を介して電源27に接続するのが一般
的であり、その稼働に伴う電界によりイオン化された正
のCu+ が負極に吸引されるが、半導体基板4の側壁
に露出したPN接合端部付近を覆う絶縁物層19には付
着されない。これに対して従来の光半導体装置23では
、露出したPN接合端部付近に並列に正のCu+から成
る金属導電層が形成されることになる。Moreover, the optical semiconductor device 23 is generally connected to a power source 27 through a resistor 26 as shown in FIG. 4b, and the positive Cu+ ionized by the electric field accompanying its operation is attracted to the negative electrode. However, it is not attached to the insulating layer 19 covering the vicinity of the PN junction end exposed on the side wall of the semiconductor substrate 4. In contrast, in the conventional optical semiconductor device 23, a metal conductive layer made of positive Cu+ is formed in parallel near the exposed PN junction end.
【0033】[0033]
【発明の効果】銅系部材を用いたリードフレームに光半
導体素子をマウントした光半導体装置に即ち発光素子で
定格電流例えば70mAを、光結合素子で受光素子に1
50mW〜300mWを印加する通電放置試験を行った
。この結果を示す図5は、光出力劣化を時間対比で表し
たグラフで、縦軸に相対光出力を横軸に時間をログスケ
ールで示したものである。直線aが従来技術により発光
素子を銅系部材を備えたリードフレームにマウントした
光半導体装置を、直線bが従来技術により発光素子銅系
リードフレームにマウントした光半導体装置を、直線c
が本発明に係わる光半導体装置を示している。Effect of the invention: In an optical semiconductor device in which an optical semiconductor element is mounted on a lead frame using a copper-based member, a rated current of, for example, 70 mA is applied to the light emitting element, and a rated current of 70 mA is applied to the light receiving element using an optical coupling element.
A energization leaving test was conducted in which 50 mW to 300 mW was applied. FIG. 5, which shows the results, is a graph showing the optical output deterioration versus time, with the vertical axis representing relative optical output and the horizontal axis representing time on a log scale. Straight line a represents an optical semiconductor device in which a light emitting element is mounted on a lead frame with a copper-based member according to a conventional technique, straight line b represents an optical semiconductor device in which a light emitting element is mounted on a copper-based lead frame according to a conventional technique, and straight line c
shows an optical semiconductor device according to the present invention.
【0034】即ち、従来の直線a、bでは、光出力が5
0%になる時間が約400時間なのに対して本発明に係
わる光半導体装置においては、10000時間以上光出
力の劣化が認められず、際立った効果が明らかになり、
本発明の優位性が立証される。That is, in the conventional straight lines a and b, the optical output is 5
While the time to reach 0% is about 400 hours, in the optical semiconductor device according to the present invention, no deterioration in optical output was observed for more than 10,000 hours, revealing a remarkable effect.
The superiority of the present invention is demonstrated.
【図1】従来の光半導体装置の内部断面図である。FIG. 1 is an internal sectional view of a conventional optical semiconductor device.
【図2】液相成長法で作られた光半導体素子の断面図で
ある。FIG. 2 is a cross-sectional view of an optical semiconductor device manufactured by liquid phase growth.
【図3】本発明に係わる光半導体装置の要部を示す断面
図である。FIG. 3 is a sectional view showing a main part of an optical semiconductor device according to the present invention.
【図4】図4aはCuイオンの発生移動経路を示す断面
図、図4bは、一般的に使用する電気回路図である。FIG. 4A is a cross-sectional view showing the generation and movement path of Cu ions, and FIG. 4B is a commonly used electrical circuit diagram.
【図5】通電放置試験における光出力劣化を時間対比で
明らかにしたグラフである。FIG. 5 is a graph illustrating optical output deterioration in a energized storage test versus time.
15:半導体基板 18:PN接合、 19:絶縁物層、 20:リードフレーム、 21:銅系部材を含むメッキ層、 22:導電性接着剤、 24,25:電極。 15: Semiconductor substrate 18: PN junction, 19: insulator layer, 20: lead frame, 21: Plated layer containing copper-based members, 22: conductive adhesive, 24, 25: Electrode.
Claims (1)
部に重ねて固着しかつ銅系部材に近接して配置する半導
体基板と,前記半導体基板に形成するPN接合と,前記
半導体基板側面に露出するPN接合端部と,前記PN接
合端部を覆う絶縁物層を具備することを特徴とする光半
導体装置1. A support portion including a copper-based member, a semiconductor substrate overlaid on and fixed to the support portion and disposed close to the copper-based member, a PN junction formed on the semiconductor substrate, and a side surface of the semiconductor substrate. An optical semiconductor device comprising: a PN junction end portion exposed to the PN junction end portion; and an insulating layer covering the PN junction end portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2413322A JPH04221864A (en) | 1990-12-21 | 1990-12-21 | Optical semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2413322A JPH04221864A (en) | 1990-12-21 | 1990-12-21 | Optical semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04221864A true JPH04221864A (en) | 1992-08-12 |
Family
ID=18521992
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2413322A Pending JPH04221864A (en) | 1990-12-21 | 1990-12-21 | Optical semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04221864A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011009346A (en) * | 2009-06-24 | 2011-01-13 | Shin-Etsu Chemical Co Ltd | Optical semiconductor device |
-
1990
- 1990-12-21 JP JP2413322A patent/JPH04221864A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011009346A (en) * | 2009-06-24 | 2011-01-13 | Shin-Etsu Chemical Co Ltd | Optical semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4347655A (en) | Mounting arrangement for semiconductor optoelectronic devices | |
US4224116A (en) | Display devices | |
US5532910A (en) | Hybrid integrated circuit and process for producing same | |
CN107195772B (en) | Hall sensor | |
KR20160046325A (en) | Hall sensor | |
US4209358A (en) | Method of fabricating a microelectronic device utilizing unfilled epoxy adhesive | |
US2989578A (en) | Electrical terminals for semiconductor devices | |
US4240098A (en) | Semiconductor optoelectronic device package | |
US5332695A (en) | Method of manufacturing semi conductor device mounted on a heat sink | |
US3869702A (en) | Stud mount for light emissive semiconductor devices | |
US3604989A (en) | Structure for rigidly mounting a semiconductor chip on a lead-out base plate | |
JPH04221864A (en) | Optical semiconductor device | |
US4380862A (en) | Method for supplying a low resistivity electrical contact to a semiconductor laser device | |
US3553828A (en) | Lead assembly structure for semiconductor devices | |
JPS6227544B2 (en) | ||
GB855381A (en) | Semiconductor device | |
JP2016157800A (en) | Lead frame substrate and method of manufacturing the same, and semiconductor device and method of manufacturing the same | |
GB2074793A (en) | Thin film circuit assembly | |
JPH0740576B2 (en) | Film carrier semiconductor device electrical test method | |
US3353073A (en) | Magnesium-aluminum alloy contacts for semiconductor devices | |
CA1153128A (en) | Electrical circuit assemblies | |
US3149396A (en) | Method of making semiconductor assemblies | |
JP2006237358A (en) | Semiconductor device housing package and watthour meter | |
JPH08102639A (en) | Piezoelectric oscillator | |
JPH077163A (en) | Diode |