JPH0422171A - Diffusion method of lifetime killer in semiconductor device - Google Patents

Abstract

PURPOSE:To easily diffuse a heavy metal at a low temperature and in a short time, to reduce the amount of the heavy metal and to easily control a lifetime by a method wherein, after the heavy metal has been diffused to a P-type region, it is then diffused to an adjacent N-type region. CONSTITUTION:A P-type base region 2 and N-type emitter regions 3 are formed on the surface of an N-type semiconductor substrate 1; an SiO2 film 4 is formed on the surface. Then, the SiO2 film 4 at the upper part of the regions 3 and windows 10, 10 for lifetime-killer diffusion use is removed; a heavy-metal film 5 of, e.g. Au, Pt or the like is applied to the surface by a vapor-deposition operation. Then, when a heat treatment is executed, e.g. at 800 to 900 deg.C for about one hour, a heavy metals diffused directly to the region 2 mainly from the windows 10. After that, the film 5 on the surface is removed by using aqua regia; a film 4 with which the surface of the regions 3 and the windows 10 is covered is formed; and a base electrode 6, an emitter electrode 7 and a collector electrode 8 are formed respectively in required parts. Thereby, a diffusion operation can be executed at a temperature which is by about 100 deg.C or lower as compared with conventional systems, the amount of a lifetime killer is reduced to about 1/4 as compared with the conventional systems and the lifetime can easily be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) In order to adjust the lifetime, which is the average lifespan of a semiconductor device, by recombination of minority carriers, a lifetime killer is often diffused into a semiconductor device. The present invention relates to a method for dispersing this lifetime killer.

(Prior Art) In order to adjust the lifetime of a semiconductor element, general materials such as Au and Pt are used as a lifetime killer and diffused into the semiconductor element. An example of NPN) lungis will be described below.

As shown in the schematic cross-sectional view of FIG. 3(a), a P-type base region 2 and an N-type emitter region 3 are sequentially formed on the surface of an N-type semiconductor substrate (which becomes an N-type collector region). Te5
102 film 4 is applied. This constitutes an NPN transistor.

Next, the lifetime killer diffusion part (N type machine lid area 3)
When the 5i02 pattern 4 on the upper part of the surface of the substrate is removed and a heavy metal 4 film 5 such as Au or Pi is coated on the entire surface by means such as vapor deposition, the result is as shown in FIG. 8(b).

This is further heat treated at, for example, 900°C to +oooc for about 1 hour to form the heavy metal. After diffusing li through the lid region 8 in the N-type process, the surface is treated with aqua regia to remove the heavy metal film 5, and the base electrode [6, emitter electrode 7] is applied to the required locations. By forming the collector electrode 8, etc., a solid NPN transistor as shown in FIG. 3(C) is obtained.

(Problem to be solved by the invention) Generally, phosphorus is used as an N-type impurity, but phosphorus is
It has the function of trapping heavy metals used as lifetime killers such as P and P, and acting as a getter, and the diffusion rate of heavy metals is significantly slower in the N-type region than in the P-type region. Therefore, when heavy metals are diffused into the P-type region below the N-type region or the N-type region further below the N-type region by penetrating the N-type region as in the past, the diffusion must be carried out at high temperature for a long time. It also requires large amounts of heavy metals.

Furthermore, as shown in the schematic cross-sectional view of FIG. 4, a left VCP type anode region is formed on the surface of the N type semiconductor substrate,
A diode is configured together with the N-type semiconductor substrate I, and Ishikata VC
In the case of a composite element comprising an NPN transistor similar to that shown in FIG. 3fa) in which a P-type base region 2 and an N-type emitter region 3 are formed, the following problem occurs. That is, when diffusing a lifetime killer such as such a composite element KAu'l'Pt, in the conventional method, PfJi
The lifetime killer will be diffused from both the anode region 9 and the N-type emitter region 3, but since the diffusion speed of heavy metals in the P-type region and the N-type region is significantly different, it is necessary to control the lifetime to the required lifetime. was extremely difficult.

(Means for Solving the Problems) In the present invention, when a semiconductor substrate has a first layer of an N-type region on the surface and a second layer of a KP-type region below or used, at least a second layer of a KP-type region is provided. The heavy metal was directly diffused into the P-type region of the two layers.

(Function) Heavy metals, which are lifetime killers, are first diffused into the P-type region, without passing through the N-type region, and then diffused into the adjacent N-type region. Therefore, before diffusion into the P-type region, heavy metals are difficult to be captured by impurities in the N-type region, so diffusion can be easily carried out at low temperature and in a short time, and
The amount of heavy metals can also be reduced. Furthermore, even in the case of a composite element, diffusion is first performed from the P-type region,
Diffusion variations caused by the difference in diffusion speed between the N-type region and the P-type region are reduced, and lifetime monitoring becomes easier.

(Example) An example of the present invention will be described using an NPN transistor.

First, as shown in FIG. 1(a) VC, an N-type semiconductor substrate 1
A P-type base region 2 and an N-type emitter region 3 are formed on the surface of the wafer, and a four-layer KSi02 film is formed on the surface thereof.

This corresponds to the conventional example shown in FIG. This part lacks an N-type region. Examples of the shape of this lifetime killer diffusion window IO will be described later in FIGS. 2(a), (b), and (c). Next, as shown in FIG. 1(b), the 5i02 film 4 above the N-type emitter region 3 and the lifetime killer diffusion window 10.10 is removed, and the surface is coated with, for example, Au or P. A heavy metal film 5 is deposited by vapor deposition or the like.This corresponds to FIG. 3(b)K.

Next, when a Japanese heat treatment is performed at, for example, 800° C. to 900° C. for one hour, the heavy metals are mainly diffused directly into the P-type base region 2 from the lifetime killer diffusion chamber IO. after that,
Remove the heavy metal film 5 on the surface with aqua regia and cover the surfaces of the N-type emitter region 3 and the lifetime killer diffusion window 10.
An i02 film 4 is formed, and base electrodes 6. When the emitter electrode 7 and the collector voltage vI1.8 are formed, the result is as shown in FIG. 1(c). This is the third
This corresponds to Figure fc). Although the main metal diffuses into the N-type region 3 from a part of the surface of the N-type emitter region 3, the main metal diffuses into the N-type semiconductor substrate 1 mainly from the P-type base region 2.
As a result, the diffusion rate of heavy metals becomes faster.

FIG. 2 ja) is a schematic plan view showing an example of the relationship between the lifetime killer diffusion window 10 and the N-type ivy region 3 (shaded area). In this figure, an appropriate number of lifetime killer diffusion windows 1 are placed inside the surface of the N-type emitter region 3.
0.10... are scattered.

FIG. 2(b) shows another example in which N-type emifter IU areas 3, 3 . A lifetime killer diffusion window 10 is formed around... This N-type emitter region 3,
3. ... are connected by appropriate means.

FIG. 2(C) shows another example, in which the lifetime killer diffusion windows 10 and 10 are viewed from the side of the N-type emitter region 3.
... is formed in a comb shape.

There are other methods, such as forming concentric circles.

(Effects of the Invention) As described above, in the present invention, when a surface VcN type region 75S of a P type region exists in a semiconductor element, lifetime killer diffusion to the P type region is directly diffused to the P type region. Impurities in the mold region do not act as getters, and diffusion can be performed at a temperature approximately 100° C. lower than in conventional methods. Further, the amount of lifetime killer is also about 174, which is the conventional amount. Furthermore, in the case of a composite element, the P of each element is
Since heavy metals are diffused into the mold region, the lifetime of each element can be easily controlled.

[Brief explanation of drawings]

Figures 1a) to 1) are schematic sectional views of each step of an embodiment of the present invention, Figures 2fal to (c) are schematic plan views showing the shapes of each part of the lifetime killer diffusion window, and 3 Figure 1m>~(C
) is a schematic sectional view of each conventional process, and FIG. 4 is a schematic sectional view for explaining lifetime killer diffusion into a composite element.

Claims (1)

[Claims] 1. A method for diffusing a lifetime killer in a semiconductor device, characterized by forming a P-type region and an N-type region on the surface of a semiconductor substrate, and diffusing the lifetime killer directly into at least the P-type region.