JPS6146047B2 - - Google Patents
Info
- Publication number
- JPS6146047B2 JPS6146047B2 JP7246980A JP7246980A JPS6146047B2 JP S6146047 B2 JPS6146047 B2 JP S6146047B2 JP 7246980 A JP7246980 A JP 7246980A JP 7246980 A JP7246980 A JP 7246980A JP S6146047 B2 JPS6146047 B2 JP S6146047B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- gold
- silver
- semiconductor wafer
- antimony alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 44
- 229910052751 metal Inorganic materials 0.000 claims description 44
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 39
- 239000010931 gold Substances 0.000 claims description 31
- 229910052737 gold Inorganic materials 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 27
- 229910001245 Sb alloy Inorganic materials 0.000 claims description 21
- 239000002140 antimony alloy Substances 0.000 claims description 21
- 229910052709 silver Inorganic materials 0.000 claims description 20
- 239000004332 silver Substances 0.000 claims description 20
- 238000007740 vapor deposition Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- KAPYVWKEUSXLKC-UHFFFAOYSA-N [Sb].[Au] Chemical compound [Sb].[Au] KAPYVWKEUSXLKC-UHFFFAOYSA-N 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000010894 electron beam technology Methods 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 19
- 239000000758 substrate Substances 0.000 description 12
- 229910001020 Au alloy Inorganic materials 0.000 description 8
- 239000003353 gold alloy Substances 0.000 description 8
- 229910052787 antimony Inorganic materials 0.000 description 6
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に関し、特に
キヤリヤのライフタイムキラーを拡散した半導体
ウエーハに対するオーミツク電極の形成方法の改
良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming an ohmic electrode on a semiconductor wafer in which a carrier lifetime killer is diffused.
トランジスタ、ダイオード、サイリスタ等の半
導体装置において、スイツチング速度を大きくす
るためにキヤリヤのライフタイムキラーを拡散す
ることは良く知られている。例えば、エピタキシ
ヤルプレーナ型スイツチングダイオードは第１図
に示すような構造を有する。図において、１は
N+型のサブストレートウエーハ、２はN-型のエ
ピタキシヤル成長層、３はＰ型領域、４はPN-接
合、５は酸化膜等の絶縁膜、６は金蒸着膜、７は
金・アンチモン合金蒸着膜、８は銀電極層、８は
銀のバンプ電極であり、全体にキヤリヤのライフ
タイムキラー１０が拡散されている。 In semiconductor devices such as transistors, diodes, and thyristors, it is well known to diffuse carrier lifetime killers in order to increase the switching speed. For example, an epitaxial planar switching diode has a structure as shown in FIG. In the figure, 1 is
N + type substrate wafer, 2 is an N - type epitaxial growth layer, 3 is a P type region, 4 is a PN - junction, 5 is an insulating film such as an oxide film, 6 is a gold vapor deposited film, 7 is gold An antimony alloy vapor deposited film, 8 a silver electrode layer, 8 a silver bump electrode, and carrier lifetime killer 10 is diffused throughout.
この種のダイオードは次のようにして製造され
ている。まず、Ｎ型不純物であるアンチモン
（Sb）を1016〜1017atoms/cm3程度の濃度にドープ
したN+型シリコンサブストレート１を用意する
（第２図）。このN+型サブストレート１上に、Ｎ
型不純物としてリン（Ｐ）を1014〜1015atoms/cm3
程度にドープしたN-型エピタキシヤル成長層２
を形成して、N+N-型半導体ウエーハ１１を製造
する（第３図）。この半導体ウエーハ１１の表裏
両面にそれぞれ絶縁膜５，１２を形成し、表面の
絶縁膜５に周知のフオトエツチングにより窓孔５
ａを形成し、この窓孔５ａからN-型エピタキシ
ヤル成長層２内にＰ型不純物としてボロン（Ｂ）
を1017atoms/cm3以上の濃度に選択拡散してＰ型領
域３およびPN-接合４を形成する（第４図）。次
に、裏面の絶縁膜１２を除去し、金蒸着膜１３を
形成して熱処理を施して、半導体ウエーハ１１中
にライフタイムキラーとして金１０を拡散する
（第５図）。こののち、N+型サブストレート１の
裏面を所定寸法だけ研磨除去して、半導体ウエー
ハ１１の厚さを所定寸法に調整し、さらに絶縁膜
５にコンタクト用の窓孔５ｂを形成する（第６
図）。次に、半導体ウエーハ１１の表面全体に金
蒸着膜６を形成するとともに、裏面全体に金・ア
ンチモン合金蒸着膜７を形成する。こののち、表
面の金蒸着膜６を所定パターンに形成し、裏面の
金・アンチモン合金蒸着膜７上にメツキにより銀
電極層８を形成する（第８図）。次に、この半導
体ウエーハ１１の裏面をワツクス１４によつて石
英板１５に貼り付け、メツキ液中で銀板をメツキ
電源の正極に、また銀電極層８をメツキ電源の負
極に接続して、表面の金蒸着膜６上に銀のバンプ
電極９を形成する（第９図）。しかるのち、ワツ
クス１４を溶解して半導体ウエーハ１１を石英板
１５から剥離し、図示一点鎖線個所から切断分離
する（第１０図）。すると、第１図のようなダイ
オードが得られる。 This type of diode is manufactured as follows. First, an N + type silicon substrate 1 doped with antimony (Sb), which is an N type impurity, to a concentration of about 10 16 to 10 17 atoms/cm 3 is prepared (FIG. 2). On this N + type substrate 1, N
Phosphorus (P) as type impurity is 10 14 to 10 15 atoms/cm 3
Moderately doped N - type epitaxial growth layer 2
An N + N - type semiconductor wafer 11 is manufactured by forming the N + N - type semiconductor wafer 11 (FIG. 3). Insulating films 5 and 12 are formed on the front and back surfaces of this semiconductor wafer 11, respectively, and window holes 5 are formed in the insulating film 5 on the front surface by well-known photoetching.
boron (B) as a P-type impurity is formed in the N - type epitaxial growth layer 2 from this window hole 5a.
is selectively diffused to a concentration of 10 17 atoms/cm 3 or higher to form a P-type region 3 and a PN - junction 4 (FIG. 4). Next, the insulating film 12 on the back surface is removed, a gold vapor deposited film 13 is formed, and heat treatment is performed to diffuse gold 10 as a lifetime killer into the semiconductor wafer 11 (FIG. 5). Thereafter, the back surface of the N + type substrate 1 is polished away by a predetermined dimension, the thickness of the semiconductor wafer 11 is adjusted to a predetermined dimension, and a contact window hole 5b is formed in the insulating film 5 (sixth
figure). Next, a gold vapor deposited film 6 is formed on the entire front surface of the semiconductor wafer 11, and a gold/antimony alloy vapor deposited film 7 is formed on the entire back surface. Thereafter, the gold vapor deposited film 6 on the front surface is formed in a predetermined pattern, and the silver electrode layer 8 is formed by plating on the gold/antimony alloy vapor deposited film 7 on the back surface (FIG. 8). Next, the back side of this semiconductor wafer 11 is attached to a quartz plate 15 with wax 14, and the silver plate is connected to the positive electrode of the plating power source in a plating solution, and the silver electrode layer 8 is connected to the negative electrode of the plating power source. A silver bump electrode 9 is formed on the gold vapor-deposited film 6 on the surface (FIG. 9). Thereafter, the wax 14 is melted, the semiconductor wafer 11 is peeled off from the quartz plate 15, and the semiconductor wafer 11 is separated from the quartz plate 15 by cutting along the dashed line shown in the figure (FIG. 10). Then, a diode as shown in FIG. 1 is obtained.
なお、表面のＰ型領域３上には金蒸着膜６を形
成するのに対し、裏面のN+型サブストレート１
の裏面には金・アンチモン合金蒸着膜７を形成す
るのは次の理由による。すなわち、表面のＰ型領
域３の不純物濃度は、前述のとおり1017atoms/cm3
以上あるので、金蒸着膜６で十分オーミツク接触
が得られる。一方、N+型サブストレート１の不
純物濃度は1017atoms/cm3以上にすると、ライフタ
イムキラーがゲツタリングされるため、所期のス
イツチング速度の増大が図れなくなるため、通常
1015〜1016atoms/cm3程度に抑えている。このた
め、N+型サブストレート１に対しては金のみで
は十分なオーミツク接触が得られず、Ｎ型不純物
であるアンチモン（Sb）を微量含む金・アンチ
モン合金蒸着膜７を形成し、金・アンチモン合金
蒸着膜７中のアンチモンをN+型サブストレート
１に浅く拡散することによつて十分なオーミツク
接触を得るようにしているのである。 Note that while the gold vapor deposition film 6 is formed on the P-type region 3 on the front surface, the N + type substrate 1 on the back surface is
The reason why the gold/antimony alloy vapor deposited film 7 is formed on the back surface of the substrate is as follows. That is, the impurity concentration of the P-type region 3 on the surface is 10 17 atoms/cm 3 as described above.
Because of the above, sufficient ohmic contact can be obtained with the gold vapor deposited film 6. On the other hand, if the impurity concentration of the N + type substrate 1 is 10 17 atoms/cm 3 or more, the lifetime killer will getter, making it impossible to increase the switching speed as expected.
It is kept to about 10 15 to 10 16 atoms/cm 3 . Therefore, sufficient ohmic contact cannot be obtained with gold alone to the N + type substrate 1, and a gold/antimony alloy vapor deposited film 7 containing a small amount of antimony (Sb), which is an N type impurity, is formed. By shallowly diffusing antimony in the antimony alloy vapor deposited film 7 into the N + type substrate 1, sufficient ohmic contact is obtained.
ところで、上述の製造方法においては、N+型
サブストレート１に対して金・アンチモン合金蒸
着膜７上に直接銀電極層８を形成しているが、銀
電極層８は銀の結晶構造が比較的粗く酸素を通し
やすく、一方、アンチモンは酸化されやすい性質
をもつ。このため、銀電極層８を通して金・アン
チモン合金蒸着膜７の表面が酸化され、電気抵抗
および熱抵抗が大きくなるという問題点があつ
た。 By the way, in the above-mentioned manufacturing method, the silver electrode layer 8 is formed directly on the gold/antimony alloy vapor deposited film 7 for the N + type substrate 1, but the silver electrode layer 8 has a comparatively different crystal structure of silver. It is rough and allows oxygen to pass through easily, while antimony has the property of being easily oxidized. Therefore, the surface of the gold/antimony alloy vapor deposited film 7 is oxidized through the silver electrode layer 8, resulting in a problem that electrical resistance and thermal resistance become large.
それゆえ、この発明の主たる目的は、キヤリヤ
のライフタイムキラーを拡散してなる半導体ウエ
ーハに対して、十分なオーミツク接触が得られ、
しかも電気抵抗および熱抵抗の小さいオーミツク
電極を形成し得る半導体装置の製造方法を提供す
ることである。 Therefore, the main object of the present invention is to obtain sufficient ohmic contact with a semiconductor wafer formed by diffusing a carrier lifetime killer.
Moreover, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form an ohmic electrode with low electrical resistance and low thermal resistance.
この発明は要約すると、キヤリヤのライフタイ
ムキラーを拡散してなる半導体ウエーハに、金・
アンチモン合金よりなる第１金属層と、金よりな
る第２金属層と、銀よりなる第３金属層とを順次
積層して形成することを特徴とするものである。 To summarize, this invention can be summarized by adding gold and
It is characterized in that it is formed by sequentially laminating a first metal layer made of an antimony alloy, a second metal layer made of gold, and a third metal layer made of silver.
この発明の上述の目的およびその他の目的と特
徴は、以下に図面を参照して行なう詳細な説明か
ら一層明らかとなろう。 The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.
この発明においても、第２図ないし第６図まで
の途中工程は従来と同様である。しかるに、この
発明においては、第１１図に示すように、絶縁膜
５にコンタクト用の窓孔５ｂを形成したのち、Ｐ
型領域３上に金を厚さ1000〜2000Å程度に蒸着し
て金蒸着膜６を形成するとともに、N+型サブス
トレート１の裏面に金・アンチモン合金を厚さ約
500〜1500Å程度に蒸着して第１金属層１６を形
成し、この第１金属層１６上に金を厚さ約1500〜
2000Å程度に蒸着して第２金属層１７を形成し、
この第２金属層１７上に銀を厚さ約１〜３μｍ程
度に蒸着して第３金属層１８を形成する。しかる
のち、従来と同様にして、表面の金蒸着膜６上に
銀のバンプ電極１９を形成し、図示一点鎖線個所
から切断分離する（第１２図）。すると第１３図
に示すようなダイオードが得られる。 In this invention as well, the intermediate steps from FIG. 2 to FIG. 6 are the same as in the prior art. However, in the present invention, as shown in FIG. 11, after forming the contact window 5b in the insulating film 5,
Gold is deposited on the mold region 3 to a thickness of approximately 1000 to 2000 Å to form a gold deposited film 6, and a gold/antimony alloy is deposited on the back surface of the N + type substrate 1 to a thickness of approximately 1000 to 2000 Å.
A first metal layer 16 is formed by vapor deposition to a thickness of about 500 to 1500 Å, and gold is deposited to a thickness of about 1500 to 1500 Å on this first metal layer 16.
A second metal layer 17 is formed by vapor deposition to a thickness of about 2000 Å,
A third metal layer 18 is formed on the second metal layer 17 by depositing silver to a thickness of about 1 to 3 μm. Thereafter, silver bump electrodes 19 are formed on the gold vapor-deposited film 6 on the surface in the same manner as in the conventional method, and the electrodes are cut and separated from the locations indicated by the dashed dot lines (FIG. 12). Then, a diode as shown in FIG. 13 is obtained.
第１４図および第１５図はこの発明の実施に用
いる蒸着装置の縦断面図および横断面図で、２０
は真空容器、２１は抵抗加熱式の金・アンチモン
合金の蒸着源、２２は電子銃、２３は蒸着皿で、
金２４を収容した凹部２３ａと銀２５を収容した
凹部２３ｂとを有し、図示時計方向に回転可能に
なつており、電子銃２２から電子線２６を照射し
て凹部２３ａまたは２３ｂ内の金２４または銀２
５を発着せしめるようになつている。２７はプラ
ネタリウムで、第７図に示すように、表面の絶縁
膜５に窓孔５ｂを形成し金蒸着膜６を形成した多
数の半導体ウエーハ１１がN+型サブストレート
１を下側に向けて取り付けられている。 FIGS. 14 and 15 are longitudinal and cross-sectional views of a vapor deposition apparatus used for carrying out the present invention.
2 is a vacuum container, 21 is a resistance heating type gold-antimony alloy vapor deposition source, 22 is an electron gun, and 23 is a vapor deposition plate.
It has a recess 23a that accommodates gold 24 and a recess 23b that accommodates silver 25, and is rotatable in the clockwise direction in the figure, and the gold 24 in the recess 23a or 23b is irradiated with an electron beam 26 from the electron gun 22. or silver 2
5 is now available for departure and arrival. 27 is a planetarium, and as shown in FIG. 7, a large number of semiconductor wafers 11 with window holes 5b formed in the insulating film 5 on the surface and gold evaporated films 6 formed thereon are placed with the N + type substrate 1 facing downward. attached.
上記の構成において、まず、真空容器２０内を
排気して十分な真空度にしたのち、抵抗加熱式の
蒸着源２１に通電して、金・アンチモン合金を完
全に飛ばし切つて、金・アンチモン合金よりなる
第１金属層１６を形成する。次に、金２４を収容
した凹部２３ａが真空容器２０の中心軸２６に一
致するように蒸着皿２３を回転し、電子銃２２か
ら電子線２６を発射して凹部２３ａ内の金２４に
照射して、第１金属層１６の上に金よりなる第２
金属層１７を形成する。こののち、蒸着皿２３を
図示時計方向に回転して、銀２５を収容した凹部
２３ｂを真空容器２０の中心軸２８に一致させ、
電子銃２２から電子線２６を発射して凹部２３ｂ
内の銀２５を照射して、第２金属層１７上に銀よ
りなる第３金属層１８を形成する。 In the above configuration, first, the inside of the vacuum container 20 is evacuated to a sufficient degree of vacuum, and then the resistance heating type evaporation source 21 is energized to completely remove the gold/antimony alloy. A first metal layer 16 is formed. Next, the deposition plate 23 is rotated so that the recess 23a containing the gold 24 coincides with the central axis 26 of the vacuum container 20, and the electron beam 26 is emitted from the electron gun 22 to irradiate the gold 24 in the recess 23a. Then, a second metal layer made of gold is formed on the first metal layer 16.
A metal layer 17 is formed. After that, the deposition plate 23 is rotated clockwise in the figure to align the recess 23b containing the silver 25 with the central axis 28 of the vacuum container 20,
The electron beam 26 is emitted from the electron gun 22 to form the recess 23b.
The third metal layer 18 made of silver is formed on the second metal layer 17 by irradiating the silver 25 inside.
なお、金・アンチモン合金よりなる第１金属層
１６のみを抵抗加熱式の蒸着源２１によつて形成
するのは、金・アンチモンの蒸気圧が相違するた
め、金・アンチモン合金に電子線を照射すると、
金とアンチモンの偏析が生じて、金・アンチモン
合金の組成が変化するためである。また、抵抗加
熱式の蒸着源２１も一回の通電加熱で全部の金・
アンチモン合金を完全に飛ばし切るようにするこ
とが望ましい。 Note that the reason why only the first metal layer 16 made of the gold-antimony alloy is formed using the resistance heating type vapor deposition source 21 is that the gold-antimony alloy is irradiated with an electron beam because the vapor pressures of gold and antimony are different. Then,
This is because segregation of gold and antimony occurs and the composition of the gold-antimony alloy changes. In addition, the resistance heating type evaporation source 21 can also remove all the gold and
It is desirable to completely remove the antimony alloy.
かくして、半導体ウエーハ１１に第１金属層１
６ないし第３金属層１８を形成すると、真空容器
２０を開いて、蒸着済み半導体ウエーハ１１を取
り出し、未蒸着半導体ウエーハ１１をセツトする
とともに、抵抗加熱式の蒸着源２１に再び所要量
の金・アンチモン合金を装填したのち、真空容器
２０を排気し、以下同様に蒸着していく。 Thus, the first metal layer 1 is formed on the semiconductor wafer 11.
After forming the metal layers 6 to 18, the vacuum chamber 20 is opened, the vapor-deposited semiconductor wafer 11 is taken out, the undeposited semiconductor wafer 11 is set, and the resistance heating type vapor deposition source 21 is again filled with the required amount of gold and metal. After loading the antimony alloy, the vacuum container 20 is evacuated, and vapor deposition is carried out in the same manner.
この発明は以上のように、金・アンチモン合金
よりなる第１金属層と、金よりなる第２金属層
と、銀よりなる第３金属層とを順次積層形成する
ことにより、金・アンチモン合金よりなる第１金
属層と銀よりなる第３金属層との間に、金よりな
る第２金属層を介在させたので、金・アンチモン
合金よりなる第１金属層の表面の酸化が防止で
き、電気抵抗および熱抵抗の小さい半導体装置が
得られる。また、金よりなる第２金属層を介在し
たことにより、金・アンチモン合金よりなる第１
金属層を従来よりも薄くでき、かつ従つて第１金
属層を従来よりも均質に形成でき、均一なオーミ
ツク接触の裏面電極が形成できるという効果を奏
する。 As described above, the present invention is made by sequentially laminating a first metal layer made of a gold-antimony alloy, a second metal layer made of gold, and a third metal layer made of silver. Since the second metal layer made of gold is interposed between the first metal layer made of gold and the third metal layer made of silver, oxidation of the surface of the first metal layer made of gold-antimony alloy can be prevented and A semiconductor device with low resistance and low thermal resistance can be obtained. In addition, by interposing the second metal layer made of gold, the first metal layer made of gold-antimony alloy
The metal layer can be made thinner than before, and the first metal layer can therefore be formed more uniformly than before, and a back electrode with uniform ohmic contact can be formed.
第１図は従来のエピタキシヤルプレーナ型ダイ
オードの断面図、第２図ないし第１０図は第１図
のダイオードの製造方法を説明するための各段階
における半導体ウエーハの断面図、第１１図ない
し第１３図はこの発明によるエピタキシヤルプレ
ーナ型ダイオードの製造方法を説明するための主
要な各段階における半導体ウエーハないしペレツ
トの断面図、第１４図および第１５図はこの発明
の実施に用いる蒸着装置の概略構成図で、第１４
図はその縦断面図、第１５図は第１４図の−
線に沿う横断面図である。
１０……キヤリヤのライフタイムキラー、１１
……半導体ウエーハ、１６……第１金属層、１７
……第２金属層、１８……第３金属層、１９……
バンプ電極。
FIG. 1 is a sectional view of a conventional epitaxial planar diode, FIGS. 2 to 10 are sectional views of a semiconductor wafer at various stages for explaining the method of manufacturing the diode shown in FIG. 1, and FIGS. Figure 13 is a cross-sectional view of a semiconductor wafer or pellet at each major stage to explain the method for manufacturing an epitaxial planar diode according to the present invention, and Figures 14 and 15 are schematic diagrams of a vapor deposition apparatus used to carry out the present invention. In the configuration diagram, the 14th
The figure is a vertical cross-sectional view, and Figure 15 is the - of Figure 14.
FIG. 10...Cariya's Lifetime Killer, 11
...Semiconductor wafer, 16...First metal layer, 17
...Second metal layer, 18...Third metal layer, 19...
Bump electrode.
Claims (1)
る半導体ウエーハの一主面に、金・アンチモン合
金よりなる第１金属層を形成し、この第１金属層
上に金よりなる第２金属層を形成し、この第２金
属上に銀よりなる第３金属層を形成してオーミツ
ク電極層を形成することを特徴とする半導体装置
の製造方法。 ２ 前記第１金属層ないし第３金属層を、蒸着に
よつて形成する、特許請求の範囲第１項記載の半
導体装置の製造方法。 ３ 前記第１金属層を抵抗加熱方式による蒸着で
形成し、第２金属層および第３金属層を電子線方
式による蒸着で形成する、特許請求の範囲第２項
記載の半導体装置の製造方法。 ４ 前記第１金属層ないし第３金属層を、同一の
真空装置内で形成する、特許請求の範囲第３項記
載の半導体装置の製造方法。[Claims] 1. A first metal layer made of a gold-antimony alloy is formed on one main surface of a semiconductor wafer obtained by diffusing a carrier lifetime killer, and a first metal layer made of gold is formed on the first metal layer. 1. A method for manufacturing a semiconductor device, comprising forming two metal layers, and forming an ohmic electrode layer by forming a third metal layer made of silver on the second metal layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first to third metal layers are formed by vapor deposition. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the first metal layer is formed by vapor deposition using a resistance heating method, and the second metal layer and the third metal layer are formed by vapor deposition using an electron beam method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first metal layer to the third metal layer are formed in the same vacuum apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7246980A JPS56169326A (en) | 1980-05-29 | 1980-05-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7246980A JPS56169326A (en) | 1980-05-29 | 1980-05-29 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56169326A JPS56169326A (en) | 1981-12-26 |
| JPS6146047B2 true JPS6146047B2 (en) | 1986-10-11 |
Family
ID=13490195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7246980A Granted JPS56169326A (en) | 1980-05-29 | 1980-05-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56169326A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6243123A (en) * | 1985-08-21 | 1987-02-25 | Rohm Co Ltd | Formation of ohmic contact in individual semiconductor device |
-
1980
- 1980-05-29 JP JP7246980A patent/JPS56169326A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56169326A (en) | 1981-12-26 |
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