JPH04220014A - 論理レベルを出力するための回路 - Google Patents
論理レベルを出力するための回路Info
- Publication number
- JPH04220014A JPH04220014A JP3065692A JP6569291A JPH04220014A JP H04220014 A JPH04220014 A JP H04220014A JP 3065692 A JP3065692 A JP 3065692A JP 6569291 A JP6569291 A JP 6569291A JP H04220014 A JPH04220014 A JP H04220014A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- switching stage
- circuit
- transistor
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000012544 monitoring process Methods 0.000 claims description 38
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000002277 temperature effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00376—Modifications for compensating variations of temperature, supply voltage or other physical parameters in bipolar transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4007212.6 | 1990-03-07 | ||
DE4007212A DE4007212A1 (de) | 1990-03-07 | 1990-03-07 | Integrierbare transistorschaltung zur abgabe logischer pegel |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04220014A true JPH04220014A (ja) | 1992-08-11 |
Family
ID=6401637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3065692A Withdrawn JPH04220014A (ja) | 1990-03-07 | 1991-03-05 | 論理レベルを出力するための回路 |
Country Status (5)
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4112310A1 (de) * | 1991-04-15 | 1992-10-22 | Siemens Ag | Signalpegelwandler |
US5323068A (en) * | 1992-11-17 | 1994-06-21 | National Semiconductor Corporation | Low power low temperature ECL output driver circuit |
DE4304262C1 (de) * | 1993-02-12 | 1993-10-07 | Siemens Ag | Multiplexeranordnung in Stromschaltertechnik |
JP2760732B2 (ja) * | 1993-06-08 | 1998-06-04 | 株式会社東芝 | Ecl出力バッファ回路 |
JP3000962B2 (ja) * | 1997-06-13 | 2000-01-17 | 日本電気株式会社 | 出力回路 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2519211A1 (fr) * | 1981-12-30 | 1983-07-01 | Radiotechnique Compelec | Etage de sortie pour circuit integre a reseau de portes de la technique ecl regule vis-a-vis des variations liees aux temperatures de fonctionnement |
JPS5981921A (ja) * | 1982-11-01 | 1984-05-11 | Hitachi Ltd | 高速論理回路 |
US4680480A (en) * | 1984-08-31 | 1987-07-14 | Storage Technology Corporation | Output driver circuit for LSI and VLSI ECL chips with an active pulldown |
US4745304A (en) * | 1985-05-03 | 1988-05-17 | Advanced Micro Devices, Inc. | Temperature compensation for ECL circuits |
JP2574859B2 (ja) * | 1988-03-16 | 1997-01-22 | 株式会社日立製作所 | Fet論理回路 |
JP2743401B2 (ja) * | 1988-10-06 | 1998-04-22 | 日本電気株式会社 | Ecl回路 |
US4897613A (en) * | 1988-10-27 | 1990-01-30 | Grumman Corporation | Temperature-compensated circuit for GaAs ECL output buffer |
US5030856A (en) * | 1989-05-04 | 1991-07-09 | International Business Machines Corporation | Receiver and level converter circuit with dual feedback |
-
1990
- 1990-03-07 DE DE4007212A patent/DE4007212A1/de active Granted
- 1990-12-21 EP EP19900125297 patent/EP0445421A3/de not_active Withdrawn
-
1991
- 1991-03-05 JP JP3065692A patent/JPH04220014A/ja not_active Withdrawn
- 1991-03-06 IE IE074891A patent/IE910748A1/en unknown
- 1991-03-07 US US07/665,782 patent/US5172015A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE4007212A1 (de) | 1991-09-12 |
EP0445421A3 (en) | 1991-11-06 |
DE4007212C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1991-12-19 |
EP0445421A2 (de) | 1991-09-11 |
IE910748A1 (en) | 1991-09-11 |
US5172015A (en) | 1992-12-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980514 |