JPH0421998A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent erroneous read when reading out stored contents after erasing by detecting a threshold voltage by impressing a voltage to the control electrode of a memory cell when erasing the memory cell, and stopping an erasing operation based on the detected voltage. CONSTITUTION:A prescribed control voltage VREF is impressed to the control gates of all EPROM cells 10. In that state, by monitoring a bit line voltage and controlling timing for stopping erasing, the memory cell is prevented from being depressed by the high voltage for erasing to be impressed between a source and a drain, and the EPROM cell 10 can be effectively prevented from being excessively erased. In a read mode, the data is read out while detecting 1 and 0 according to a current value between the source and drain generated by impressing the prescribed voltage to the control gate of the cell 10. In the case of erasing, since depression is blocked, the current between the source and drain in the case of read flows based on an electric charge Q of the floating gate of the cell 10 corresponding to the value of the voltage impressed to the control gate.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems Embodiment (a) An embodiment of the first invention (first embodiment) Figure 1) (b) An embodiment of the second invention (Figs. 3 and 4) (C) Other embodiments of the first and second invention Effects of the invention [Summary] Electrical writing The present invention relates to semiconductor memory devices that can be erased and erased, and in particular to semiconductor memory devices that can prevent over-erasing of memory cells, and that prevents over-erasing of memory cells and preventing erroneous reading without increasing the number of elements in the memory cells. In order to provide a semiconductor memory device having a memory cell whose memory contents can be updated by electrical means, when erasing the memory contents of the memory cell, the control electrode of the memory cell is a memory control means for applying a predetermined voltage to the memory cell; a potential detection means for detecting a threshold voltage of the memory cell in a voltage application state by the memory control means; and an erase voltage for stopping an erase operation based on the detected threshold voltage. and a control means.

[Industrial application field]

The present invention relates to a semiconductor memory device that can be electrically written and erased, and more particularly to a semiconductor memory device that can prevent over-erasing of memory cells.

In recent years, semiconductor memory devices that can erase memory contents all at once have been developed, including EPROM, which erases data by irradiation with ultraviolet light, and EAR, which erases electrically.
OM, EEPROM.

There are various types such as F 1 a s hEPROM. E above
Although PROMs are written electrically, they are erased using ultraviolet light, which is inconvenient in terms of operation, as they require an ultraviolet device.

As mentioned above, various types of semiconductor memory devices are being developed in which writing and erasing are performed electrically on the EPROM, but since the erasing mode is also electrically performed, it is not possible to use other modes (for example, read mode). There is a need for a semiconductor memory device that eliminates this electrical influence.

[Conventional technology]

Conventionally, there is a semiconductor memory device of this type using a floating gate type EEPROM cell, which is shown in FIG. FIG. 5 shows a schematic configuration diagram of a conventional semiconductor memory device.

In the figure, the conventional semiconductor memory device has word lines WLk-WL connected to each control gate of EEPROM cells T-T1[111m-Tkn-TIn arranged in a matrix, and bit lines BL--Tn connected to each drain terminal. BL is connected, and the power supply ■PP is applied to each n source terminal during erasing, and the ground voltage is applied during writing, and the word line WLk of the memory array 1 is connected to the memory array 1 based on the output of the X decoder.
-X driver 6 to select and activate either WL.
and the data line (bit line) based on the output of the Y decoder.
The configuration includes a Y driver 7 that selects a Y driver 7, and a sense amplifier 8 that detects the potential level of a data line (bit line) outputted via the Y driver 7 and outputs data.

Next, the operation of the conventional device will be explained based on the above configuration. First, in the erase mode, each E of memory array 1
The word lines WLk-WL connected to the control gates of EPROM cells T-TIIl11-m Tkn="In are maintained in the ov state by the X driver 6. In this state, each EEPROM cell T-T
, ~ High km on each source terminal of Tkn-TIn
Applying a voltage of 1 m PP and setting each drain terminal in a floating state, the threshold voltage (V, ) of the cell is lowered by drawing electrons from the floating gate to the source terminal using the F-N channel phenomenon. Erase the memory contents.

In the write mode, information is written by changing the threshold voltage (lh) of the memory cell by injecting electrons excited by the avalanche phenomenon into the floating gate.

In the read mode, information is read by determining whether the memory cell is "0" or "1" based on the value of the charge Q in the floating gate.

In this way, the conventional floating gate type EEPROM
A semiconductor memory device using cells has one memory cell (ce
ll) is composed of one transistor, which is different from conventional EF
It has the same degree of integration as ROM.

[Problem to be solved by the invention]

Since the conventional semiconductor memory device is configured as described above, when performing electrical bulk erasing, the threshold voltage (lh) of the memory cell becomes too low and depletion (D) occurs.
cpletion), and when multiple unselected memory cells are connected on the same bit line when reading multiple depleted memory cells, the current is equivalent to the sum of the currents flowing through each memory cell. Current flows through the bit line, resulting in a sense amplifier erroneously detecting the bit line even though it is not selected.

To solve this problem, the erase time can be increased and the threshold voltage of the memory cell can be changed very gradually.
It is conceivable that the threshold level may be detected externally each time in several stages. This method requires a very long erasing time and creates a new problem, requiring a complicated method of external inspection.

Furthermore, even if the memory cell is single, the logic value “1.”0 will change depending on the voltage application state to the control gate.
When detecting in association with the word line, even if the word line is not activated, current will flow because the memory cell transistor is depleted.
The problem was that errors occurred one after another.

In addition, there is another conventional semiconductor memory device shown in FIG. 6, and the other conventional device in the same figure has a selection transistor T (~Tln1, ml~T-T) and a memory cell transistor k.
nl 1nl T (~T 1 ~ T −T ) are combined into a set of km2 1m2 kn2 In2, and these two combined transistors constitute one memory cell. Other conventional devices do not have the problem of false detection of sense amplifiers due to depletion that occurs in the conventional device shown in FIG. It had

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that prevents over-erasing of memory cells and prevents erroneous reading without increasing the number of elements in the memory cells. .

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the first invention.

In the figure, a semiconductor memory device according to a first aspect of the present invention is a semiconductor memory device having a memory cell 10 whose memory contents can be updated by electrical means, when the memory contents of the memory cell 10 are erased. 10
a memory EF cell control means 20 for applying a predetermined control voltage (1) to a control electrode of the memory cell; and the memory cell control means.

The potential detection means 30 detects the threshold voltage of the memory cell 10.
and erase voltage control means 40 for stopping the erase operation based on the detected threshold voltage.

FIG. 2 shows a diagram explaining the principle of the second invention.

In the figure, the semiconductor memory device according to the second aspect of the present invention is constructed by connecting a plurality of memory cells 11, 12, . . . , whose memory contents can be updated by electrical means, to the same bit line. In the semiconductor memory device, a control voltage at a level that makes the memory cells in the erased state conductive is applied to each memory cell 11.12, . . . when erasing the memory contents of the plurality of memory cells 11.12, . memory cell control means 21.22 for applying voltage to the control electrode;
..., and when erasing the memory contents of the memory cells 11, 12, ..., the source of each memory cell 11, 12, ...
Potential detection means 3 for detecting the potential applied between the drains
0, and erase voltage power supply control means 40 for stopping the erase operation of each memory cell 11, 12, . . . based on the detected potential of the potential detecting means 30.

[Effect]

In the first invention, when erasing the memory contents of a memory cell, a predetermined voltage is applied to the control electrode of the memory cell, a threshold voltage of the memory cell is detected, and the erasing operation is stopped based on this threshold voltage. This makes it possible to prevent depletion of the memory cell due to over-erasing without providing a special element for preventing depletion in the memory cell, and prevents erroneous reading when reading the stored contents after erasing.

In the second aspect of the present invention, a control voltage that maintains conductivity of the memory cell after erasing is applied to the control electrode of the memory cell when erasing the memory contents, and the potential between the source and drain of the memory cell is detected. Erase operation is stopped based on the potential. By stopping the erase operation based on a predetermined source-drain potential in this way, depletion of memory cells due to over-erasing is prevented, and read errors due to unselected memory cells at the time of read are prevented. .

〔Example〕

(a) An embodiment of the first invention An embodiment of the first invention will now be described with reference to FIG. 1, which is a diagram illustrating the principle of the first invention.

In the figure, the semiconductor memory device according to this embodiment performs a memory operation by storing electrons in a floating gate sandwiched between a control gate and a channel region between a source and a drain, and a part of a tunnel insulating film under the floating gate. EEPR that writes and erases data via
OM cell 10 and a memory EF that applies a predetermined control voltage V to the control electrode of the EEPROM cell 10 when the EEPROM cell 10 is erased; The above EF includes a potential detecting means 30 for detecting the threshold voltage of the EEPROM cell 10, and the above EE based on the detected threshold voltage.
The configuration includes a power supply control means 40 that controls the voltage applied to the source terminal of the PROM cell 10.

The erase mode of the device of this embodiment is performed as follows.

First, a predetermined control voltage V 1 is applied to the control gates of all EPROM cells 10 . By monitoring the bit line EF voltage with this applied EF control voltage V and controlling the erase stop timing, memory cell damage caused by the high erase voltage applied between the source and drain can be controlled. Preventing privation,
Over-erasing of the EEPROM cell 1o can be effectively prevented.

In the read mode, by applying a predetermined voltage to the control gate of the EEPR, 0M cell 1o, logical values "1" and "0" are detected and read based on the current value between the source and drain generated in response to this applied voltage. Since depletion is prevented during the above erasing, the current value between the source and drain during reading is based on the charge QF at the floating gate of the EEPROM cell 10 corresponding to the applied voltage value of the control gate. Since over-erasing is thus prevented during erasing, there will be no read errors during reading.

(b) An embodiment of the second invention FIG. 3 is a circuit configuration diagram of an embodiment of the second invention.

In the figure, the semiconductor memory device according to the present embodiment includes an EEPROM cell Tkm-Tl connected to the bit line BL -BL and the word line WL, ~n W L
Activates and selects the memory array 1 formed by arranging a plurality of Tkn"""In in a matrix and the word lines WLh to WL of the memory array 1, and erases a specific voltage at the time of erasing. A row decoder 2 which outputs a control voltage EF for the memory array 1 is connected to the bit lines BL-BL of the memory array 1 via a gate circuit 5 controlled by the output n of the column decoder.
The potential level of the bit line BL −BL is m
II. A bit line level detection circuit 3 that detects and outputs a 5TER signal, and a bit line level detection circuit 3 that detects and outputs a 5TER signal, and a
, each EEPROM cell T −T , ~T
The configuration includes a source control circuit 4 that controls the voltage applied to the source of kn-TIIl by km 1m.

Further, transfer gates T11 to Tl are provided between the bit lines BL to BL of the memory array 1.
n are connected, and these transfer gates T11 to Tln
When the bit line connection signal ER' is input to the gate terminal of the bit line level detection circuit 3, all the bit lines BL-BL are connected to the bit line level detection circuit 3 by a total amount n.

Next, the operation of the device of this embodiment based on the above configuration will be described in the third section above.
The explanation will be given with reference to FIG. 4 along with the drawings.

FIG. 4 is an operation timing diagram in this embodiment.

First, when an erase command signal is input from the outside, the erase operation is started at time t1, which is the same time as the rise of the erase command signal. In this erase operation, before the erase signal ER rises and at the same time as the erase command signal rises (time 11), the reset clock signal φ is input to the bit line level detection circuit 3 to turn on the NMo8T31. Further, an OR circuit (not shown) calculates a logical sum condition for each of the reset clock signal φ and erase signal ER, and outputs a bit line connection signal ER'. This bit line connection signal ER' is input to the gate terminals of the transfer gates T11 to TIn, and all transfer gates T11 to TIn are input to the gate terminals of the transfer gates T11 to TIn.
1n is in a conductive state, all bit lines BL
-BL is grounded (GND) through the gate circuit 5 and the NMO8T3 in the ON state, and all EEPROM cells T-T, ~Tkm~k connected to all the bit lines BL-BL
m 1m Reset T to O■. The level detection circuit 3 outputs the 5TER signal as an "H" level (V, H).

After this reset, the erase signal ER rises (time t
2) Since the erase signals ER and ER turn off both PMO8T21 and NMo5T22 in the row decoder 2, the row decoder 2 no longer responds to address signals.

Also, in the row decoder 2, erase signals ER, ER
Both PMO8T23 and NMo8T24 are turned on, and the series circuit (PMO8T2゜PMO8T -N
Voltage applied to MO3T-NMo8T26)■
is divided at a predetermined voltage division ratio determined by the rated ratio of PMO8T25 and PNMOST 26, and the erase control voltage V determined by this voltage division ratio is
is applied to the word line WL. Note that EF 2 is also generated by other row decoders and applied to all word EF lines. The setting standard for the erasing control voltage V will be described later.

Further, the erase signal ER and the 5TER signal are respectively input to the source control circuit 4, and the source control circuit 4 outputs a high voltage to the source of each EEPROM cell T-T, ~Tkn~km 1m Tln of the memory array 1 at time t2. Apply voltage vPP. By applying this high voltage vPP, the potential at point A of the source control circuit 4 falls, and the potential at point B of the memory array 1 decreases to v
Raise it to PP level.

The above high voltage vPP is continuously applied, and any EE
PROM cell T-T, ~ Tkn-TInkm
When Im releases electrons from the floating gate and becomes ON as the threshold voltage decreases (time t3), the potentials of the bit lines BLII1 to BL of the memory array 1 gradually rise. This bit line BL -BL
When the rise in the potential of LE reaches a predetermined potential n level (hereinafter referred to as the erase stop judgment level) (time t), the NMO8T32 is turned on, and the input to the NOT circuit 32 is set to the "L" level and the NAND
The output of the 5TER signal is stopped via the circuit 33 (
time t5).

When the 5TER signal goes to the "L" level (V, L), the potential at point A of the source control circuit 4 is raised again to the PP level, and the vPP output to the upper side of the memory array is stopped. Point B is set to 0v (GND) level.

Since point B of this memory array 1 becomes QV (GND), each EEPROM cell "km-Tl1n'~T
NMO8T where the source side of kn~TIn is in the ON state with point B
Since each source potential becomes 0.times.4, the erase operation is automatically terminated at this point (time t5).

After the above erase operation is automatically completed, the erase command signal from the outside falls (time t6), and at the same time, the word line W
L -WL becomes a potential corresponding to each mode of 0■ or 5■, and the bit line BL -
BL also has a potential corresponding to each mode.

n In this way, even though the erase command signal from the outside maintains the rising state, the bit line level detection circuit 3
Since the erase operation is automatically terminated based on the 5TER signal output from the EEPRoM cell T-
T1~Tkll~km1m Depregnation of TIn is prevented, and over-erasing can be prevented.

Furthermore, REF is set as the setting standard for the above erasing control voltage V. explain about.

Now, EEPROM cells Tkm-TI□, ~ TkIl
The reason why ~T is depleted and causes erroneous reading is that too many electrons are extracted from the floating gates of unselected EEPROM cells in the read mode. From this, it is necessary to satisfy the following formula.

WL ” CR'V (=0■)+VFGE thO...Equation-1 Here, CR is the capacitance ratio between the control gate and the floating gate, and ■, is the word line WL.

~WL potential (=control gate potential), ■
FGE is the floating gate potential after erasing, V
indicates the threshold voltage of the EEPROM cell. Nath.

Oh, in the above formula-1, VWL is not selected, so 0v
, and V ≦V.

FGE IhO Furthermore, since the selected EEFROM cell in the read mode needs to be at a potential that can be determined to be at a conductive level (ON state), the following equation needs to be satisfied.

CR-V +V ≧V ---Formula-2
WL FGRthO From the above formula-1 and formula-2, V-C-V ≦V ≦V thORWL FGE lh.

...Formula-3 becomes.

In addition, the erase stop judgment level ■ is as follows: BLE become.

v = C・V +V -V BLE RREF FGE lh.

...Formula-4 From the above formula-4, V = V - C fist ■ + ■ FGE BLE RREF lh.

...Equation-5 Substituting the above Equation-5 into Equation-3, v −c −V ≦V −
c -v+hORWL BLE
RREF+■ ≦■ IhOlhQ ...Formula-6 Rearranging the above formula-6, V, -1-V /C≧V ≧V /C
WL BLE RREF BLE R
...Equation-7 Set ``REF'' so that the above-mentioned Equation-7 is satisfied.

For example, the setting of ① is set in the PMOS T2 in the row decoder 2 of the semiconductor memory EF device of this embodiment.
5. It can be determined by the ratio of mutual conductance gm between T and NMO8T XT.

As a specific example, the potential of the word line = 3.5V, the erase stop determination level V = 2.1. V, control EL - capacitance ratio of ru gate and floating gate CRO17
Then, the following condition is required.

6.5≧V ≧3 REF In other words, when the erase control voltage ■ is 3■ or more, REF This means that it is 6.5v or less.

In addition, the write mode is set to the selected bit line BL (
~BL) and word line WL.

A high voltage PP is applied to each of n (~WL), and information is written with the source side of each EEPROM of the memory m array 1 set as Ov.

Furthermore, the read mode is set to the selected word line WL (
〜WL, o) is activated, and each bit line BL (〜
The potential of BL) is detected by the sense amplifier 31 in the bit line level detection circuit 3 and information is read out.

In this read mode, with the erase control voltage V applied to all word lines as described above, information is erased by applying a high voltage to each memory cell, and this erase operation is performed at the erase stop judgment level. (2) Since the automatic stop is performed, each EL memory cell will not be depleted, and erroneous reading in the sense amplifier 31 can be prevented and accurate reading can be performed.

(C) Other embodiments of the first and second inventions In the above embodiment, a plurality of bit lines BL to BL are selected by the gate circuit 5, and by detecting the potential of the selected bit lines, Although the erase operation is configured to be stopped, the potential of each of the plurality of bi-soto lines BL - BL is detected, and it is determined whether each of the detected potentials has reached the erase stop judgment level ■BEL, It is also possible to adopt a configuration in which the erasing operation is stopped based on this determination result.

In addition, in the above-mentioned embodiment, the erase operation is configured to be stopped when any of the detected potentials first reaches the erase stop judgment level vBEL, when it reaches the last time, or when it reaches the erase stop judgment level vBEL. You can also do it.

In addition, in the above embodiment, the pin lines BL-BL of the memory cell array 1 are connected to the bit line level detection circuit 3 via the gate circuit 5, and the bit lines BL-BL are connected between the bit lines BL-BL. Transfer game-1- operates based on signal ER'
Although the configuration is such that the bit lines BL to BL are connected to each other, it is also possible to arbitrarily select any one of the bit lines BL to BL and connect it to the gate circuit 5.

With this configuration, memory cells connected to any selected bit line BL-BL can be erased at once when the erase signal is input.

Furthermore, the memory cells in each of the above embodiments may be EEP
Although the configuration is formed using ROM, EAROMSFlas
The present invention can also be applied to hEEPRO'M and other memory cells in which stored information is erased electrically.

〔Effect of the invention〕

As explained above, in the first aspect of the present invention, when erasing a memory cell, a voltage is applied to the control electrode of the memory cell, the threshold voltage of this memory cell is detected, and the erasing operation is stopped based on this threshold voltage. Since this structure is adopted, it is possible to prevent deregion of the memory cell due to over-erasing without increasing the number of elements in the memory cell, and it is possible to prevent erroneous reading when reading the stored contents after erasing.

In the second aspect of the present invention, a control voltage that maintains conductivity of the memory cell after erasing is applied to the control electrode of the memory cell when erasing the memory contents, and the potential between the source and drain of the memory cell is detected. Since the erase operation is stopped based on the potential, depletion of memory cells due to over-erasing is prevented, and read errors due to unselected memory cells during read can be prevented.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the first invention, FIG. 2 is a diagram explaining the principle of the second invention, FIG. 3 is a configuration diagram of an embodiment of the second invention, and FIG. 4 is a diagram explaining the principle of the second invention.
FIG. 5 shows a schematic configuration diagram of a conventional semiconductor memory device, and FIG. 6 shows a memory array configuration diagram of another conventional semiconductor memory device. 1...Memory array 2...Row decoder 3...Bit line level detection circuit 4...Source control circuit 5...Gate circuit 6...X driver 7...Y driver 8.31, ...Sense up

Claims (1)

[Scope of Claims] 1. In a semiconductor memory device having a memory cell (10) whose memory content can be updated by electrical means, when the memory content of the memory cell (10) is erased, the memory cell (10) memory cell control means (for applying a predetermined control voltage (V_R_E_F) to the control electrode of
20), and a control voltage (V_
The above memory cell (10) in the R_E_F) application state
A semiconductor memory device comprising: potential detection means (30) for detecting a threshold voltage; and erase voltage control means (40) for stopping an erase operation based on the detected threshold voltage. 2. The above control voltage (V_R_E_F) is V_W_L+(V_B_L_B/C_R)≧V_R_E
2. The semiconductor memory device according to claim 1, wherein _F≧V_B_L_E/C_R−V_W_L: Word line selection voltage during reading V_B_L_E: Erase stop determination level C_R: A value that satisfies a capacitance ratio between a control gate and a floating gate. 3. In a semiconductor memory device configured by connecting a plurality of memory cells (11, 12,...) to the same bit line, whose memory contents can be updated by electrical means, a memory cell in a state where erasure has been completed. The plurality of memory cells (11, 12,...
) when erasing the memory contents of each memory cell (11, 12,...)
Memory cell control means (2
1, 22,...) and the above memory cells (11, 12,...)
a potential detection means (30) for detecting the potential applied between the source and drain of each memory cell (11, 12,...) when erasing the memory contents; A semiconductor memory device comprising erase voltage control means (40) for stopping erase operation of memory cells (11, 12, . . . ). 4. The potential detection means (30) detects the potential for each bit line of the plurality of bit lines, and the erase voltage control means (40) stops the erase operation based on each detected potential. 4. The semiconductor memory device according to claim 3. 5. The potential detection means (30) detects the potential for each bit line of the plurality of bit lines, and the detected potential is intermediate between the time when each detected potential reaches the first specific potential and the last time it reaches the specific potential. 4. The semiconductor memory device according to claim 3, wherein the erase voltage control means (40) stops the erase operation based on the detected potential at the time.