JP2000076882A - Semiconductor storage device and voltage bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device, by which a bit-line discharge time is shortened and a read time can be shortened. SOLUTION: A bit-line side selector gate line SG1 and a word line are started up and a source-line side selector gate SG2 is started up when a current flows towards a source line from a bit line in the read of a NAND type EEPROM, and the source-line side selector gate SG2 and the word line are started up and the bit-line side selector gate SG1 is started up when the current is flowed towards the bit line from the source line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a voltage bias circuit, and more particularly, to an electrically rewritable nonvolatile semiconductor memory device, and a sense amplifier and a row decoder circuit in the nonvolatile semiconductor memory device. And a voltage bias circuit for applying a voltage higher than a power supply voltage to a predetermined node.

[0002]

2. Description of the Related Art In recent years, as one type of nonvolatile semiconductor memory device (EEPROM) capable of electrically overwriting,
An ND cell type EEPROM has been proposed. This EEP
In a ROM, a plurality of memory cells having an n-channel MOSFET structure in which, for example, a floating gate and a control gate are stacked as a charge storage layer are connected in series by sharing their sources and drains with adjacent ones. Are connected to a bit line as one unit.

FIGS. 20 (a) and 20 (b) show one of the memory cell arrays in a conventional NAND type EEPROM, respectively.
FIG. 2 is a pattern plan view of one NAND cell part and its equivalent circuit diagram. FIGS. 21 (a) and 21 (b) correspond to FIG.
It is sectional drawing along the AA 'line and the BB' line of the pattern shown to 0 (a). A p-type semiconductor substrate (in this example, a p-type silicon substrate 11-
1, an n-type well region 11-2 is formed, and a p-type well region 11-3 is formed in the n-type well region 11-2. However, a p-type silicon substrate may be used.)
1, a memory cell array including a plurality of NAND cells is formed. Focusing on one NAND cell, in this example, eight memory cells M _{1 to} M ₈ are connected in series to form one NAND cell. Each of the memory cells M _{1 to} M ₈ has a floating gate 14 (14 ₁ , 14 ₂ , 14) on a substrate 11 via a gate insulating film 13.
_3, ..., 14 ₈₎ is formed, the control gate 16 (16 ₁ through the insulating film 15 on the floating gate 14, 16 _2,
16 _3, ..., 16 ₈₎ are formed by laminating. The n-type diffusion layers 1 serving as the source and drain of these memory cells
In 9, memory cells are connected in series in such a manner as to be shared between adjacent ones.

[0004] First and second select transistors S ₁ and S ₂ are provided on the drain side and the source side of the NAND cell, respectively. These selection transistors S ₁ , S
₂ is provided with a floating gate, a first selection is formed at the same time as the control gate gate 14 _9, 16 _9, and the second selection gate 14 _10, 16 ₁₀ of the memory cell. The selection gate 14 ₉ and 16 ₉ are electrically connected by unillustrated region,
The select gates 14 ₁₀ and 16 ₁₀ are also electrically connected in a region (not shown) and function as gate electrodes of the select transistors S ₁ and S ₂ , respectively. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which a bit line 18 is provided. The control gates 16 of the NAND cells are commonly arranged as control gate lines CG ₁ , CG ₂ ,..., CG ₈ . These control gate lines become word lines. Select gate 14 _9, 16 ₉ and 14 _10, 16 ₁₀ are also respectively arranged in a row direction successively selected gate lines SG _1, SG _2.

FIG. 22 shows an equivalent circuit diagram of a memory cell array in which NAND cells as described above are arranged in a matrix. The source line is connected to a reference potential wiring such as Al or polysilicon via a contact, for example, at one place for every 64 bit lines. This reference potential wiring is connected to a peripheral circuit. The control gate and the first and second select gates of the memory cell are arranged continuously in the row direction. Usually, the set of memory cells connected to the control gate is 1
Called page, one set of drain side (first select gate)
A set of pages sandwiched by the selection gates on the source side (second selection gate) is called one NAND block or simply one block. One page is composed of, for example, 256 bytes (256 × 8) memory cells. Writing is performed almost simultaneously on the memory cells for one page. 1
The block includes, for example, 2048 bytes (2048 × 8) memory cells. Memory cells for one block are erased almost simultaneously.

In the above configuration, data writing is performed sequentially from the memory cell farthest from the bit line. 0 V ("0" write) or power supply voltage Vcc ("1" write) is applied to the bit line according to data. The select gate connected to the bit line has a power supply voltage Vcc,
The select gate connected to the source line is at 0V. At this time,
0 V is transmitted to the channel of the cell where “0” is written. Since the selection gate connected to the bit line is turned off by writing “1”, the channel of the memory cell to which “1” is written becomes Vcc−Vthsg (Vthsg is the threshold voltage of the selection gate) and floats. Alternatively, when the threshold voltage of the memory cell closer to the bit line than the memory cell to be written has a positive voltage Vthcell, the channel of the memory cell is Vcc-Vthce.
ll. Thereafter, the boosted write voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell.
And an intermediate potential Vpass (= about 10 V) is applied to the control gates of the other unselected memory cells. As a result, when the data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate because the channel potential is 0 V, and electrons are tunnel-injected from the substrate into the floating gate, so that the threshold voltage becomes positive. Go to When the data is "1", the floating channel has an intermediate potential (about 6 V) due to capacitive coupling with the control gate, and no electrons are injected.

On the other hand, data erasure is performed almost simultaneously in block units. That is, all the control gates of the block to be erased are set to 0 V, and the boosted potential VppE (2) is boosted to the p-type well region 11-3 and the n-type well region 11-2.
(Approximately 0 V). The control gate of the block that does not perform erasing is changed from the floating state to the p-type well region
-3 is boosted to the VppE level by capacitive coupling. Thereby, in the memory cell of the block to be erased, electrons of the floating gate are released to the p-type well region 11-3, and the threshold voltage moves in the negative direction. In the block where erasing is not performed, the control gate and the p-type well region 11-3
Since both are VppE, no erasure is performed.

In a data read operation, a bit line is floated after being precharged to a power supply voltage Vcc,
The control gate of the selected memory cell is set to 0 V, the control gates of the other memory cells and the selection gate are set to the power supply voltage Vcc.
(For example, 3 V), by setting the source line to 0 V and detecting whether or not a current flows in the selected memory cell on the bit line. That is, if the data written in the memory cell is "0" (threshold voltage Vth> 0 of the memory cell), the memory cell is turned off, so that the bit line maintains the precharge potential, but "1" (memory cell Threshold voltage V
If th <0), the memory cell is turned on and the bit line drops from the precharge potential by ΔV. By detecting these bit line potentials with a sense amplifier, data in a memory cell is read.

In the above-described conventional reading method, the bit line is set to a reduced power supply voltage Vdd (for example, 2.5 V) inside the chip.
After precharging to V), the bit line is discharged to 0.5 V or less in the case of "1" read, and maintains Vdd in the case of "0" read. The bit line discharge time Tbl at the time of reading “1” is Tbl = Tbl = bit line capacitance Cbl, bit line amplitude Vbl, and memory cell current Icell.
Cbl × Vbl / Icell. NAND type EEP
In the ROM, since the memory cells are connected in series, there is a problem that the memory cell current Icell is small, and as a result, the bit line discharge time Tbl is long and the read is long. Assuming that the bit line capacitance is, for example, 3 pF and the current flowing through the memory cell at the time of reading “1” is 0.5 μA, the bit line discharge time is 3 pF × (2.5V−0.5V) /
0.5 μA = 12 μsec.

Further, the conventional NAND flash memory has the following problem at the time of reading. For example, FIG.
(A), when data is read from the memory cell M5 of (b), the control gate lines CG ₅ is ground, the selection gate line S
G ₁ , SG ₂ , control gate lines CG ₁ , CG ₂ , CG ₃ ,
Setting the _{CG 4, CG 6, CG 7} , CG 8 to the power supply voltage Vcc. Or timing for biasing the selection gate lines and control gate lines all at the same time biasing, or after first control gate lines CG ₁ ~CG ₈ and the select gate line SG ₂ was set to the power supply voltage Vcc, and the selection gate lines SG ₁ Bias to power supply voltage Vcc. When the memory cell M5 is turned on, float also the control gate lines CG ₅ by capacitive coupling between the channel and the control gate. For example, if the channel is charged from 0V to 1.2V, the control gate lines CG ₅ 0.
After floating to about 5V, the RC time constant of the control gate (1μ
After about (sec), it returns to 0V. As described above, when the control gate floats to about 0.5 V due to capacitive coupling noise between the channel and the control gate, the "0" cell, which should have been turned off, is also turned on, causing a problem of erroneous reading.

By the way, the NAND type EEPROM described above is used.
M and the like, at the time of reading and writing, the voltage VH higher than the power supply voltage Vcc is applied to a predetermined node Na of the sense amplifier or the row decoder.
Must be applied. A conventional voltage bias circuit for biasing the node Na is configured, for example, as shown in FIG. This voltage bias circuit includes transistors Q1, Q2, Q3, an inverter INV1, and a high voltage switch SW1, and selectively supplies a power supply voltage Vcc, a ground voltage Vss, and a high voltage VH higher than the power supply voltage Vcc to a node Na. To be applied. The high voltage switch SW1 includes transistors Q4 to Q7 and a capacitor C. In FIG. 23, H
The transistors Q3 to Q6 labeled N are connected to the power supply voltage Vc.
This is a high voltage (high breakdown voltage) enhancement type n-channel transistor to which a voltage higher than c can be applied. Since the threshold voltages of these transistors Q3 to Q6 are about 0.6V, they are turned off when 0V is applied to the gates. On the other hand, transistors Q2 and DHN
Q7 is a high-voltage depletion-type n-channel transistor. The threshold voltage of these transistors Q2 and Q7 is -1V, and the gate and drain are connected to the power supply voltage V
When it is set to cc, the power supply voltage Vcc can be transferred to the source.
When the gates of the transistors Q2 and Q7 are set to 0V, the source and drain voltages are turned off under the condition of the power supply voltage Vcc. Transistor Q1 is a low-voltage p-channel transistor to which a voltage equal to or lower than power supply voltage Vcc is applied. The transistor Q2 connected in series to the transistor Q1 is for preventing a high voltage from being applied to the transistor Q1.

In the above configuration, when the node Na is grounded, the voltage V3 applied to the gate of the transistor Q3 is the power supply voltage Vcc, and the voltage V1 applied to the input terminal of the inverter INV1 and the gate of the transistor Q2 is the ground voltage Vss. , And the voltage V2 applied to one end of the current path of the transistor Q7 may be set to the ground voltage Vss. Also,
When the voltages V1 and V3 are set to the ground voltage Vss, the voltage V2 is set to the power supply voltage Vcc, and the clock signal CLK is applied to one electrode of the capacitor CB1, the high voltage VH is applied to the node Na via the high voltage switch SW1. When the voltage V1 is set to the power supply voltage Vcc and the voltages V2 and V3 are set to the ground voltage Vss, the node Na is biased to the power supply voltage Vcc.

However, in the conventional voltage bias circuit as shown in FIG. 23, when changing the node Na from the high voltage VH to the power supply voltage Vcc, the voltage V3 is first changed to the power supply voltage Vcc so that the node Na is connected to the transistor. Discharge via Q3. Thereafter, the node Na is set to the transistor Q by setting the voltage V1 to the power supply voltage Vcc.
1 and the power supply voltage Vcc via Q2. As described above, when changing the node Na from the high voltage VH to the power supply voltage Vcc, since it is grounded and then charged to the power supply voltage Vcc, it takes time, and there is a problem that current consumption increases.

On the other hand, in order to discharge node Na directly from high voltage VH to power supply voltage Vcc, voltage V1 is changed to power supply voltage Vc.
When it is set to c, VH is applied to the source (p-type semiconductor region) of the transistor Q1, and the pn junction diode between the power supply voltage Vcc and the substrate (n-type semiconductor region) is turned on. As a result, there is a problem that latch-up occurs.

[0015]

As described above, the conventional semiconductor memory device has a problem that the bit line discharge time is long and the read time is long because the memory cell current is small.

In addition, when the potential of the control gate floats due to capacitive coupling noise between the channel and the control gate, there is a problem that the memory cell, which should have been turned off, is turned on and erroneous reading is performed.

Further, in the conventional voltage bias circuit, when a predetermined node for applying a bias voltage is changed from a high voltage to a power supply voltage, it takes a long time to charge the power supply voltage after being grounded, and current consumption is reduced. There was a problem of increasing.

Furthermore, when a predetermined node is to be discharged directly from a high voltage to a power supply voltage, a pn junction diode between the source of the transistor and the substrate is turned on, causing a problem of latch-up.

The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a semiconductor memory device capable of shortening the bit line discharge time and shortening the read time.

A second object of the present invention is to provide a semiconductor memory device capable of preventing erroneous reading even if the potential of the control gate floats due to capacitive coupling noise between the channel and the control gate.

A third object of the present invention is to provide a voltage bias circuit capable of shortening the time required to change a predetermined node for applying a bias voltage from a high voltage to a power supply voltage and reducing current consumption. .

A fourth object of the present invention is to provide a voltage bias circuit capable of preventing latch-up even when a predetermined node is directly discharged from a high voltage to a power supply voltage.

[0023]

According to the present invention, there is provided a semiconductor memory device comprising: a memory cell section including at least one nonvolatile memory cell; a bit line connected to one end of the memory cell section; A first transistor connecting the first node, a second transistor for setting the first sense node to a predetermined potential, and a third transistor for detecting the potential of the first sense node; Sometimes, setting the gate electrode of the first transistor to the first clamp voltage sets the bit line to the first precharge potential, and then sets the gate electrode of the first transistor to the second clamp potential. By doing
The first sense node is sensed by the third transistor.

The second clamp potential is lower than the first clamp potential.

[0025] The substrates of the first, second and third transistors contain impurities of the same polarity.

Further, the semiconductor memory device of the present invention has a memory cell portion including at least one memory cell, a first selection transistor connecting the memory cell portion and a first signal line, A second signal line connected thereto, and in the operation of flowing a current from the second signal line to the first signal line via the memory cell portion, after applying a predetermined voltage to the gate of the memory cell. And applying a predetermined voltage to the gate of the first selection transistor so that the first selection transistor is turned on.

Further, the semiconductor memory device of the present invention has a memory cell portion including at least one memory cell, a first selection transistor connecting the memory cell portion to a first signal line, and a memory cell portion. A second selection transistor for connecting a second signal line, wherein the second selection transistor is turned on in an operation of flowing a current from the second signal line to the first signal line via the memory cell unit. After applying a predetermined voltage to the gate of the second selection transistor so as to be in a state, a predetermined voltage is applied to the gate of the first selection transistor so that the first selection transistor is turned on. It is characterized in that it is applied.

Further, according to the semiconductor memory device of the present invention, there is provided a memory cell portion including at least one memory cell, a first selection transistor connecting the memory cell portion to a first signal line, A second selection transistor for connecting a second signal line, wherein the second selection transistor is turned on in an operation of flowing a current from the second signal line to the first signal line via the memory cell unit. Applying a predetermined voltage to the gate of the second selection transistor, and applying a predetermined voltage to the gate of the memory cell so that the first selection transistor is turned on. A predetermined voltage is applied to a gate of the first selection transistor.

A semiconductor memory device according to the present invention includes a memory cell section including a plurality of memory cells connected in series to each other, a first selection transistor connecting the memory cell section to a first signal line, And a second selection transistor connecting the first signal line to the second signal line, and in the operation of flowing a current from the second signal line to the first signal line via the memory cell unit, the second selection transistor Is turned on, a predetermined voltage is applied to the gate of the second selection transistor, a read voltage is applied to a selected memory cell in the memory cell section, and a non-selected memory cell in the memory cell section is After applying a predetermined voltage to the gate of the unselected memory cell so as to be turned on, the first selection transistor is turned on so that the first selection transistor is turned on. It is characterized by applying a predetermined voltage to the gate.

Still further, in the semiconductor memory device according to the present invention, the memory cell section including at least one memory cell, a first selection transistor connecting the memory cell section to a first signal line, and the memory cell section And a second selection transistor for connecting the second signal line, and the second selection transistor is turned on so that the second selection transistor is turned on when reading data stored in the memory cell. After applying a predetermined voltage to the gate of the transistor and applying a predetermined voltage to the gate of the memory cell, a predetermined voltage is applied to the gate of the first selection transistor so that the first selection transistor is turned on. It is characterized in that a voltage is applied.

The first signal line is a source line, and the second signal line is a bit line.

Alternatively, the first signal line is a bit line, and the second signal line is a source line.

A voltage bias circuit according to the present invention includes a first switch circuit provided between a first voltage terminal and a first node, and a first switch circuit provided between the first voltage terminal and the first node. And a second switch circuit.

Further, the voltage bias circuit of the present invention has a first
A first switch circuit disposed between the first voltage terminal and the first node for discharging a charge of the first node to the first voltage terminal; and a first switch circuit disposed between the first voltage terminal and the first node. And a second switch circuit that charges the electric charge of the first node from the first voltage terminal.

Further, the voltage bias circuit of the present invention has a first
A first switch circuit disposed between the first voltage terminal and the first node; a second switch circuit disposed between the first voltage terminal and the first node; A second voltage terminal to which a second voltage higher than the first voltage applied to the voltage terminal is applied, and a third switch circuit provided between the first node. Features.

Furthermore, the voltage bias circuit of the present invention
A first switch circuit disposed between a first voltage terminal and a first node; a second switch circuit disposed between the first voltage terminal and the first node; A third switch circuit disposed between a second voltage terminal to which a second voltage higher than the first voltage applied to the first voltage terminal is applied and the first node; A third voltage terminal to which a third voltage lower than the first voltage is applied, and a fourth switch circuit disposed between the first node and the third node.

The first switch circuit discharges the charge of the first node to the first voltage terminal, and the second switch circuit charges the charge from the first power supply terminal to the first node. Charge.

The first switch circuit operates during a period other than a standby period, and the second switch circuit operates during a standby period.

The first switch circuit is an n-channel type M
An OS transistor, wherein the second switch circuit includes
It is characterized by including a channel type MOS transistor.

[0040] The first voltage is a power supply voltage.

The first voltage is a power supply voltage, and the second voltage is a ground voltage.

[0042]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a NAND cell type EEPROM for explaining a semiconductor memory device according to an embodiment of the present invention.
The NAND type EEPROM includes a memory cell array 1 for storing data, a sense amplifier / latch circuit 2 for writing and reading data, a row decoder 3 for selecting a word line, a column decoder 4 for selecting a bit line,
It includes an address buffer 5, an I / O sense amplifier 6, a data output buffer 7, a substrate potential control circuit 8, and the like. In addition, a booster circuit (not shown) for generating a read voltage, a write voltage, and an erase voltage is provided.

The memory cell array 1 shown in FIG.
The configuration is the same as that of the conventional NAND type EEPROM shown in FIGS. 21 (a) and 21 (b), and FIGS. 21 (a) and 21 (b) and FIG.

The sense amplifier / data latch circuit 2 and the row decoder 3 are configured as shown in FIGS. 2 and 3, respectively. That is, in the sense amplifier / data latch circuit 2 shown in FIG. 2, two bit lines BL0 and BL1 share one sense amplifier in order to reduce inter-bit line capacitive coupling noise. The bit line BL
20 (a) and (b) and FIG.
One end of the select transistor in the NAND cell shown in FIGS. These bit lines BL
One ends of current paths of n-channel transistors Tr1, Tr2, Tr3, Tr4 are connected to both ends of 0 and BL1, respectively. The signal BLCU0 is supplied to the gate of the transistor Tr1, the signal BLTR0 is supplied to the gate of the transistor Tr2, the signal BLCU1 is supplied to the gate of the transistor Tr3, and the signal BLTR1 is supplied to the gate of the transistor Tr4. The above transistor T
The other ends of the current paths of r1 and Tr3 are commonly connected,
The signal BLCRL is input. The above transistor Tr
The other ends of the current paths of Tr2 and Tr4 are commonly connected, and n
It is connected to one end of the current path of the channel transistors Tr5 and TrN1. The signal BLCD is supplied to the gate of the transistor Tr5, and the signal BLCRAMP is supplied to the gate of the transistor TrN1. A first input terminal of the latch circuit LA and the transistor Tr5 are connected to the other end node N1 of the current path of the transistor Tr5.
6, and one end of the current path of Tr7 are respectively connected. The latch circuit LA includes p-channel transistors Tr8 to Tr8.
Tr11 and n-channel transistors Tr12, Tr1
3 is comprised. The latch circuit LA receives the signal S supplied to the gates of the transistors Tr8 and Tr9.
The operation is controlled in response to the AP. This latch circuit LA
Is connected to one end of a current path of the n-channel transistor Tr14. The signal BLSEN0 is supplied to the gate of the transistor Tr14. The other ends of the current paths of the transistors Tr7 and Tr14 are connected to one end of the current path of the transistor TrN3. The other end of the current path of the transistor TrN3 is grounded, and has a gate (sense node Nsen).
In (se), the other end of the current path of the transistor TrN1 is connected. A current path of an n-channel transistor TrN2 is connected between the sense node Nsense and the power supply Vdd, and a signal BLPRE is supplied to a gate of the transistor TrN2. A source and a drain are commonly connected between the sense node Nsense and the ground Vss, and an n-channel transistor TrN4 serving as a capacitor is connected.

Further, one end of the current path of the n-channel transistor Tr15, the gate of the n-channel transistor Tr16, and one end of the current path of the n-channel transistor Tr17 are connected to the node N2. The other end of the current path of the transistor Tr15 is grounded, and a signal SAPRST is supplied to the gate. The signal FLAG is supplied to one end of the current path of the transistor Tr16. A current path of an n-channel transistor Tr18 is connected between the other end of the current path of the transistor Tr16 and the ground, and a signal VERIFY is supplied to a gate of the transistor Tr18. The above transistor Tr6
The gate of Tr17 is connected to a common column selection signal line CSL, and the other ends of the current paths of these transistors Tr6 and Tr17 are connected to input / output signal lines IO and IOn.

The row decoder 3 shown in FIG. 3 includes block address selection circuits 20-1, 20-2,... Provided for each of the blocks 1, 2,. The block address is determined by the block address selection circuit 20-
, 20-2,..., And output signals RDECI1,
RDECI2,... Are supplied to each block. Focusing on block 1, the output signal RDECI1 of the block address selection circuit 20-1 is supplied to one input terminal of the NAND gate 21-1, one end of the current path of the transistor Tr20, and the input terminal of the inverter 22-1. You. The signal OSCRD is supplied to the other input terminal of the NAND gate 21-1. The output terminal of the NAND gate 21-1 has one electrode of the capacitor C1 formed by connecting the source and drain of the transistor in common and the inverter 23.
-1 input terminal. The output terminal of the inverter 23-1 is connected to one electrode of a capacitor C2 formed by commonly connecting the source and drain of the transistor. One end of the current path of the n-channel transistors Tr21 and Tr22 and the gate of the transistor Tr22 are connected to the other electrode of the capacitor C2.
The signal VRDEC is supplied to the other end of the current path of the transistor Tr21, and the gate is connected to the other electrode of the capacitor C1. Further, the transistor Tr22
Is connected to the other electrode of the capacitor C1. The signal VRDEC is supplied to one end of the current path of the n-channel transistor Tr23, and the other end and the gate of the current path of the transistor Tr23 are connected to the other electrode of the capacitor C1.

One end of the current path of the transistor Tr24 is connected to the other end of the current path of the transistor Tr20, and the signal BSTON is supplied to the gate. The other end of the current path of the transistor Tr24, the other end of the current path of the transistor Tr23, and the n-channel transistors TrSG1, TrCG1 to TrCG16, TrS
The gate of G2 is connected. The above transistor TrSG
The signal SGD is supplied to one end of one current path, and the other end of the current path is connected to the select gate line SG1 in the adjacent block 2.
Connected to. One end of the current path of the n-channel transistor Tr25 is connected to the select gate line SG1, and the output signal RD of the inverter 22-1 is connected to the gate.
ECI1B is supplied. Further, the transistor Tr
25, an n-channel transistor T
One end of the current path of r26 is connected. The output signal RDECI2B of the inverter 22-2 is supplied to the gate of the transistor Tr26, and the signal S is supplied to the other end of the current path.
GDS is provided. The above transistors TrCG1 to TCG
Signals CGN1 to CGN are provided at one end of the current path of rCG16.
16 is supplied to the control gate line CG at the other end of the current path.
1 to CG16 are respectively connected. The signal SGS is supplied to one end of the current path of the transistor TrSG2, and the other end of the current path is connected to the selection gate line SG2. One end of the current path of the n-channel transistor Tr27 is connected to the selection gate line SG2, and the signal RDECI1B is supplied to the gate and the signal SGDS is supplied to the other end of the current path.

Block 2 has basically the same configuration as block 1.

In FIGS. 2 and 3, transistors Tr1 to Tr4, Tr21 and Tr2 labeled HN
3, Tr25 to Tr27, TrSG1, TrCG1 to T
rCG16 and TrSG2 are respectively the power supply voltage Vcc
It is a high voltage (high breakdown voltage) enhancement type n-channel transistor to which a higher voltage can be applied. These transistors have a threshold voltage of about 0.6 V, and are turned off when 0 V is applied to the gate. On the other hand, HND
Transistors Tr20, Tr25, C1,
C2 is a high voltage depletion type n-channel transistor. The threshold voltage of HND is -1 V, and when the gate and the drain are set to the power supply voltage Vcc, the power supply voltage Vcc can be transferred to the source. When the gate of the HND is set to 0V, the source / drain voltage is turned off under the condition of the power supply voltage Vcc. Transistor Tr22 labeled HNI
Is an intrinsic transistor whose threshold voltage is near 0V. In addition, transistors Tr5 to Tr1
8, TrN1 to TrN4 are low voltage transistors to which a voltage equal to or lower than the power supply voltage Vcc is applied.

FIG. 4 shows the NA shown in FIGS.
FIG. 3 is a cross-sectional view schematically showing a well configuration of an ND type EEPROM. This NAND type EEPROM has a high-voltage n-channel transistor section 11A, a low-voltage n-channel transistor section 11B, a low-voltage p-channel transistor (p-channel MOS transistor) section 11C, and a memory cell section 11D. The high-voltage n-channel transistor section 11A to which a voltage higher than the power supply voltage is applied is formed in the p-type silicon substrate 11. The low-voltage n-channel transistor portion 11B is formed in the p-type well region, and the low-voltage p-channel transistor portion 11C is formed in the n-type well region. The memory cell portion 11D is formed in a p-type well region in an n-type well region formed in a p-type silicon substrate. The n-type well region and the p-type well region in the memory cell section 11D are set to the same potential.

Next, the read operation will be schematically described with reference to FIGS. 5A to 5D, Vdd is an in-chip power supply voltage (2.5 V) generated by stepping down an externally applied power supply voltage in the chip. The transistor TrN1 is a clamp transistor whose gate is set to a voltage lower than the power supply voltage Vdd during bit line precharge and sense. The transistor TrN2 is a transistor connected between the power supply Vdd and the sense node Nsense for charging the bit line, and the transistor TrN3 is a sense transistor. The transistor TrN4 is connected to the sense node Nsens
It functions as a stabilizing capacitor for preventing e from fluctuating due to coupling noise.

First, as shown in FIG. 5A, the bit line is floated after being precharged to 1V. Thereafter, the charge of the bit line is discharged via the memory cell (FIG. 5B). At the time of bit line discharge, the signal BLC
LAMP is set to 0 V, signal BLPRE is set to 3.8 V, and the sense node Nsense is charged to the power supply voltage Vdd. After the bit line discharge, the signal BLCLAMP is set to 1.5V. Since the bit line for reading “1” is 0.5 V or less, the transistor TrN1 conducts, and the sense node Nsens
e becomes 0.5 V or less (FIG. 5C). As a result, the sense transistor TrN3 is turned off.

On the other hand, the bit line for reading “0” is set to 0.
Since it is higher than 5 V, the transistor TrN1 is turned off,
The sense node Nsense maintains the power supply voltage Vdd (FIG. 5D). As a result, the sense transistor TrN3 turns on. As described above, in this embodiment, the sense node N is discharged only by discharging the bit line by 0.5 V from 1 V to 0.5 V.
Sense swings from 2.5V to 0.5V. As a result, the bit line amplitude can be reduced from the conventional 2V to 0.5V, so that the bit line discharge time is reduced to 1/4 of the conventional, and the reading speed is increased.

The precharge transistor TrN2
May be a p-channel transistor, but is more preferably an n-channel transistor. That is, when the transistor TrN2 is a p-channel type, the sense node Ns
This is because it is necessary to wire the sense not only to the n-channel transistor region but also to the p-channel transistor region. Since the capacitance of the sense node Nsense is sufficiently smaller than the bit line capacitance (for example, 1/100), coupling noise is likely to be received from an adjacent wiring or an upper or lower wiring. Accordingly, the wiring of the sense node Nsense is short, and if there is no other signal line in the periphery, stable reading can be performed. Therefore, when the precharge transistor TrN2 is of a p-channel type, the wiring becomes long, and thus the precharge transistor TrN2 is susceptible to noise. In addition, as shown in FIGS. 5 and 2, when the sense system is formed only of n-channel transistors, the layout can be performed without providing another wiring around the sense node Nsense. On the other hand, when a p-channel transistor is used for the transistor TrN2, as can be seen from FIG. 2, the sense node Nsen
“se” passes through the n-channel transistor regions (the transistors Tr12 and Tr13 and the transistors Tr7 and Tr14 whose sense activation signals BLSEN0 and BLSEN1 are supplied to the gate) constituting the latch circuit LA, and passes through the precharge transistor Tr in the p-channel transistor region.
10, since it is necessary to input to Tr11, it becomes easy to receive noise. For example, at the time of sensing, one of the sense activation signals BLSEN0 and BLSEN1 is activated, so that the sense node Nsense outputs the signal BLSEN.
0, BLSEN1.

Next, the read operation of the NAND type EEPROM of the present invention will be described in more detail with reference to the timing chart of FIG. In the figure, gnd is the ground potential. FIG. 6 is a timing chart when data is read from the memory cell MCELL16 in the circuit shown in FIG. In the standby state, the signals BLCU0, BCU
LCU1 is the power supply voltage Vdd and grounds the bit line. Read at time RCLK0 booster circuit activation signal LI
MVRDn becomes “L” level, and the read booster circuit starts operating. The VSG booster circuit activation signal LIMVSGn also goes low, and the VSG booster circuit also starts operating. Then, VSGHH (about 7 V) is generated by the VSG booster circuit.

Selected block (for example, block 1 in FIG. 3)
Then, the block selection signal RDECI1 is changed to the power supply voltage Vdd.
And transferG1 is Vrea of VRDEC.
The potential is raised from dH (a voltage higher than Vread, about 6 V). As a result, the control gates CG1, C
G2,..., CG16 are signals CGN1, CGN2,.
The potential becomes N16. In the unselected block 2, the block selection signal RDECI2 becomes the ground voltage Vss, and
nsferG2 becomes the ground voltage Vss. As a result, the control gate of block 2 becomes floating. The selection gate SG3 in the unselected block 2 is grounded from SGDS. In another unselected block (not shown) that does not share the drain side select gate (SG1 in FIG. 3) with the selected block 1, both select gates in the block are grounded.

At time RCLK1, SG1, CG1, and CG
, CG15 become Vread (3.5V). The selected control gate CG16 is at 0V. Time RCL
The signal BLCLAMP becomes Vclamp (2 V) at K2, and the precharge of the selected bit line BL0 starts. The selected bit line BL0 is precharged to 1V, and the unselected bit line BL1 is grounded via BLCRL. Thus, the memory cells of the block selected during the bit line precharge (for example, MCELL1, 2, 3,..., 15, 1)
The channel or drain of 6) is charged. As described in the prior art, the memory cells of the selected block (e.g., MCELL1, MCELL2, MCELL3,
, MCELL15, MCELL16) are charged, so that CG1, CG2,.
The potential of CG16 rises. However, since SG2 is at the ground potential, no current flows through the memory cell, so that erroneous reading unlike the related art does not occur. At time RCLK3, the signal BLSEN0 becomes the power supply voltage Vcc, and the node N1 of the latch in the circuit shown in FIG.
Is reset to "H" level.

After the end of the bit line precharge, at time RCL
At K4, the select gate line SG2 is biased to Vread, and the bit line discharge starts. As described above, the select gate lines SG1, the control gate lines CG1, CG2,.
CG16 has a predetermined potential (Vrea) at the time of RCLK4.
d or 0V). As described above, by selectively charging the selection gate line SG1 and the control gate, and starting the selection gate line SG2 after the coupling noise disappears, stable reading without erroneous reading can be performed.

During the discharge of the bit line, the signal BLCL
AMP is grounded in order to prevent a leak current from the sense node Nsense to the bit line. Also, during reading, the unselected bit line BL1 is grounded to reduce capacitive coupling noise between bit lines. Also, the signal BL
The reason why TR0 and BLCU1 are set to VSGHH (about 7 V) is to reduce the on-resistance of the transistor selected by these signals BLTR0 and BLCU1. Further, the reason why the signal BLTR0 slowly rises for 1.5 μsec is to prevent the drop of the in-chip power supply Vdd by gradually precharging the bit lines.

By the time RCLK5, sense node Nse
nse is charged to the power supply voltage Vcc, the signal BLCLAMP becomes 1.5 V at time RCLK6, and the sense node Nsense is charged to the power supply voltage Vcc. At time RCLK6, the signal BLCLAMP becomes 1.5 V, and Charge is transferred to the bit line. Then, at time RCLK7, the signal BLSEN1
Rises to the "H" level, thereby causing the sense node Nse
The potential of nse is sensed. As a result, if "0" is read (Nsense is at "H" level), N2
Becomes “L” level, and when “1” is read (Nse
If nse is at "L" level, N2 will be at "H" level.

Thereafter, at time RCLK8, CSL goes to "H".
Level, and the data of the latch is output to IO and IOn. The recovery operation starts at time RCLK9.
At time RCLK9, the discharge of the bit line, control gate, and select gate to the ground voltage starts. Then, at time RCLK1
At 0, the signals LIMVRDn and LIMVSGn become "H" level, and the booster circuit stops. At time RCLK11, the node in the row decoder is discharged.

After the reading is completed, the signal BLCU0 is also set to BL.
When the power supply voltage Vdd of CU1 is also set, all the bit lines are grounded.

FIG. 7 is a timing chart of the negative threshold read mode. In FIG. 7, the memory cell M of FIG.
The case where CELL16 is selected is shown. In reading the negative threshold, signals BLCD, BLSEN0, BLT
By setting R0 to “H” level, the source line is set to the power supply voltage Vdd after the selected bit line is precharged to 0V.
To The selected control gate is set to Vsel, and the unselected gates are set to Vread (3.5 V). For example, Vsel
Is 0V. When the memory cell has a negative threshold voltage, the absolute value of the threshold is output to the bit line. For a predetermined Vsel, the potential of the bit line is Vsel
+ | Vth |, the negative threshold value of the memory cell can be measured by changing Vsel from outside the chip. The absolute value of the negative threshold voltage is output to the selected bit line BL0. The unselected bit line BL1 is biased from BLCRL to the power supply voltage Vcc to reduce bit line coupling noise. At time RCLK8, signal B
When LSEN1 goes to “H” level, the potential of the bit line is sensed.

In reading the negative threshold value, first, at time RC
After biasing SG2 and the control gate to LK1, at time R
The select gate line SG1 is biased to Vread at CLK5. This is because the drain or the channel of the memory cell is charged from the source line side contrary to the normal read operation shown in FIG. That is, as shown in FIG. 7, the select gate lines SG2, control gate lines CG1, CG2,.
The CG 16 has returned to a predetermined potential at the time of RCLK5. As described above, in the negative threshold reading, the selection gate line SG2 and the control gate are charged first, and after the coupling noise disappears, the selection gate line SG1 is raised to perform stable reading without erroneous reading. Can be. Since the negative threshold voltage can be measured by using the method shown in FIG. 7, the method can also be used in an erase verify mode for checking whether erasure has been performed sufficiently.

FIG. 8 is a timing chart showing a write operation. FIG. 8 shows a case where the memory cell MCELL16 is selected. When writing is performed, the node N1 of the latch LA in FIG. When writing is not performed, the node N1 of the latch LA in FIG. 2 becomes "H" level. The write data is obtained by changing the signal BCLD to Vsg (4 V).
Is transferred to the selected bit line BL0.
In the case of “0” write, the memory cell is set to 0 from the bit line.
V is set and writing is performed. In the case of "1" writing, the bit line is set to the power supply voltage Vdd. As shown by the solid line in FIG. 8, by setting the select gate line SG1 to Vsg and the control gate line to Vread (4.5 V),
Power supply voltage Vd from the bit line to the channel for writing “1”
d may be transferred. Alternatively, as shown by a dotted line in FIG. 8, the control gate line may be biased from 0V.
After the bit line is charged, the selected control gate line CG16 is set at Vpgm (20 V) and the non-selected control gate line C from time PCLK4.
G1, CG2,..., CG15 are set to Vpass (10 V). In the case of "0" writing, electrons are injected into the floating gate from the 0V channel. In the case of "1" writing, the select gate TrSG1 is turned off, so that the channel rises to about 8 V due to capacitive coupling with the control gate. as a result,
No electrons are injected into the memory cell for “1” write.

In FIG. 8, the memory cell connected to the non-selected bit line BL1 is such that the bit line BL1 is changed from BLCRL to the power supply voltage V.
When set to cc, writing is not selected.
The reason why BLTR0 and BLCU1 take 1.5 μs and rise slowly in FIG. 8 is to prevent the drop of the in-chip power supply Vdd by gradually charging the bit lines.

FIG. 9 shows another writing method. In FIG. 9, the potential (about 3.5 V) higher than the power supply voltage Vdd is transferred from the source line to the memory cell by setting the source line and the selection gate line SG2 to 4.5V. The source line potential is applied to all the memory cells in the selected block.

The operation timing can be variously modified. As shown by the solid line in FIG. 9, the control gate may rise from 0 V at time PCLK4. Alternatively, as shown in FIG. 9, a high potential of about 3.5 V may be transferred from the source to the channel for writing “1” by setting the control gate to Vread (4.5 V). By transferring a potential higher than the power supply voltage Vdd from the source line to the memory cell as shown in FIG. 9, the channel potential of the memory cell to which "1" is written can be increased, and the erroneous writing characteristics can be improved.

After the channel of the memory cell is boosted to about 9 V by capacitive coupling with the control gate, the channel at time PCLK6
When the select gate line SG1 becomes the power supply voltage Vdd, the write data of the bit line is transferred. That is,
The memory cell connected to the unselected bit line BL1 and "1"
The channel of the memory cell to be written keeps 9V,
The channel of the memory cell into which “0” is written is discharged to 0V.

FIG. 10 is a timing chart of the write verify read. The write data is set in the latch of FIG. 2, and when “1” is written (when write is not selected),
Is at "H" level,
When "0" is written (when writing is selected), the node N1 is at "L" level. The write verify mode is almost the same as the read in FIG. The difference is that the selected control gate CG16 is not at 0 V but at the verify voltage V
vrfy (0.5 V) and the reset operation of the latch LA of the sense amplifier (time RCLK in FIG. 7).
4 is no operation to make the signal BLSEN0 become “H” level). As a result of the verify read, if "0" write is insufficient, the node N1 of the latch goes to "L" level and is rewritten. In the case of sufficient "0" writing and "1" writing, N1 becomes "H" level, and writing is not performed. Detection of whether or not writing has been sufficiently performed in all columns is performed as follows. First, the signal FL
After precharging AG to the power supply voltage Vcc, at time RC
The signal VERIFY is set to “H” level at LK8. As a result, if there is a column with insufficient writing even in one column,
The signal FLAG becomes the ground voltage Vss, and it is detected that there is a column for which writing is insufficient.

After writing, an over-program verify read may be performed. FIG. 11 is a timing chart. In the over-program verify read, it is detected whether or not the memory cell is excessively written. That is, the control gate lines CG1, CG2,.
Read is performed by setting to "ead". Vread:
8V. As a result, the control gate lines CG1, CG2,
.., It is detected whether the threshold voltage of the memory cell selected by CG16 is 2.8 V or more. Vread is set lower than 3.5 V at the time of normal reading.
This is to provide a margin for power supply voltage fluctuation, temperature fluctuation, processing fluctuation, and the like. The presence or absence of an excessively written memory cell somewhere in all columns is determined at time RC.
It is detected when the signal VERIFY becomes “H” level at LK8.

FIG. 12 is a timing chart of the erase verify read. Control gate lines CG1, CG2,..., CG
16 is set to 0 V and reading is performed. As a result, it is detected whether or not the threshold voltage of the memory cell selected by the control gate lines CG1, CG2,. Further, in order to provide a margin for power supply voltage fluctuation, temperature fluctuation, processing fluctuation, and the like, the bit line precharge potential is increased from 1 V of the lead to 1.3 V, and the bit line discharge time (from time RCLK4 to time RCL in FIG. 12).
(Time to K5) is shorter than the lead. Whether or not there is a memory cell with insufficient erasure in any of the columns is detected when the signal VERIFY becomes “H” level at time RCLK8.

In the above embodiment, the NAND
Although the description has been made by taking the type EEPROM as an example, the present invention
R type, AND type (A. Nozoe: ISSCC, Dig
est of Technical Papers,
1995), DINOR type (S. Kobayashi:
ISSCC, Digest of Technica
l Papers, 1995), NAND type, Virt
ual GroundArray type (Lee, et a
l. : Symposium on VLSICircu
it's, Digest of Technical
(Papers, 1994), etc., and may be applied to a mask ROM, an EPROM or the like without being limited to a flash memory.

In FIGS. 2 and 5, sense node Ns
A capacitance (transistor) TrN4 is connected to this sense node Nsense in order to reduce capacitive coupling noise from surrounding wiring and the like to the sense. If a desired capacitance can be obtained by the wiring capacitance of the sense node Nsense, it is needless to say that the capacitance TrN4 is not required.

Next, a voltage bias circuit according to an embodiment of the present invention will be described.

FIG. 13 shows a voltage bias circuit according to the present invention. This voltage bias circuit includes transistors Q11-Q
19 and capacitors CB2 and CB3. The current path of transistor Q11 is connected between power supply Vcc and node Na. One end of the current path of the transistor Q12 is connected to the power supply Vcc, and the gate is connected to the gate of the transistor Q11. One end and the gate of the current path of the transistor Q13 are connected to the other end of the current path of the transistor Q12, and the other end of the current path is connected to the gate of the transistor Q11. At the connection point of the current paths of the transistors Q12 and Q13,
One electrode of the capacitor CB2 is connected, and the clock signal CLK1 is supplied to the other electrode of the capacitor CB2. One end of the current path of the transistor Q14 is connected to the gate of the transistor Q11, the gate is grounded, and the voltage V1 is applied to the other end of the current path. This circuit constitutes a high-voltage switch SW2.

The current path of the transistor Q16 is
Connected between high voltage VH and node Na. One end of the current path of the transistor Q17 is connected to the high voltage VH, and the gate is connected to the gate of the transistor Q16. One end and the gate of the current path of the transistor Q18 are connected to the other end of the current path of the transistor Q17, and the other end of the current path is connected to the gate of the transistor Q16. One electrode of a capacitor CB3 is connected to a connection point between the current paths of the transistors Q17 and Q18, and a clock signal CLK2 is supplied to the other electrode of the capacitor CB3. One end of the current path of the transistor Q19 is connected to the gate of the transistor Q16,
The gate is grounded, and the voltage V2 is applied to the other end of the current path. This circuit constitutes a high-voltage switch SW3.

The current path of the transistor Q15 is connected between the node Na and the ground, and the voltage V3 is applied to the gate of the transistor Q15.

In the above configuration, when the node Na is grounded, the voltage V3 is set to the power supply voltage Vcc and the voltage Vcc.
1, V2 may be set to the ground voltage Vss. Also, the voltage V
1, V3 is ground voltage Vss, and voltage V2 is power supply voltage Vcc.
Then, when the clock signal CLK2 is applied to the capacitor CB3, the high voltage VH is applied to the node Na via the high voltage switch SW1. The voltage V1 is set to the power supply voltage Vcc, the voltages V2 and V3 are set to the ground voltage Vss, and the capacitor CB2 is set.
, The node Na is biased to the power supply voltage Vcc. High voltage V at node Na
When discharging from H to the power supply voltage Vcc, the clock signal CLK1 may be applied by setting the voltage V1 to the power supply voltage Vcc, and setting the voltages V2 and V3 to the ground voltage Vss. FIG.
In the meantime, Vcc may be a power supply voltage in a chip which is stepped down from an external power supply voltage.

As described above, according to the voltage bias circuit of the present invention, a high-speed bias circuit with low current consumption can be realized.

As shown in FIG. 23, when biasing node Na to power supply voltage Vcc through high voltage switch SW1, clock signal CLK1 is input to continue driving capacitor CB1. Since the current consumption when driving this capacitor is about 50 μA, it is negligibly small compared to the entire chip current (about 10 mA) consumed during operations such as reading and writing. Also, a circuit that generates a clock (such as a ring oscillator) consumes current. However, the standby state (standby state)
In such a case, it is necessary to reduce the current consumed by the entire chip to about 5 μA, so that it is not desirable to operate the high-voltage switch circuit during standby. The circuit shown in FIG. 14 solves this problem.

In FIG. 14, a path via a p-channel transistor is added as a charging path for power supply voltage Vcc. That is, the current paths of transistors Q20 and Q21 are provided in series between power supply Vcc and node Na, and voltage V4 is applied to the gate of transistor Q20 by inverter INV.
2, and the voltage V4 is supplied to the gate of the transistor Q21. Since the other configuration is the same as that of the circuit shown in FIG. 13, the same components are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the above configuration, during standby, the voltages V1, V2, and V3 are set to the ground voltage Vss and the voltage V4.
To the power supply voltage Vcc, the transistor Q2
The node Na can be charged to the power supply voltage Vcc via 0 and Q21. Transistor Q21 has node Na at power supply voltage V
Since the current is not consumed after reaching cc, the current during standby can be reduced. In FIG. 14, when the node Na is grounded, the voltage V3 is set to the power supply voltage Vcc and the voltages V1, V2, V4
May be set to the ground voltage Vss. In addition, the voltages V1 and V
3, V4 is ground voltage Vss, voltage V2 is power supply voltage Vcc
When the clock signal CLK2 is applied to the capacitor CB3, the high voltage VH is applied to the node Na via the high voltage switch SW3. When discharging node Na from high voltage VH to power supply voltage Vcc, voltage V1 is changed to power supply voltage Vcc.
The clock signal CLK1 may be applied to the capacitor CB2 by setting cc and the voltages V2, V3, and V4 to the ground voltage Vss. Further, when the power supply voltage Vcc is applied to the node Na during operations such as reading, writing, and erasing other than during standby,
The voltage V1 is changed to the power supply voltage Vcc and the high voltage switch SW2
May be charged via the power supply voltage Vcc.
To charge via the transistor Q20,
The voltages V1 and V4 may both be the power supply voltage Vcc. As described above, according to the present invention, it is possible to realize a bias circuit that is high-speed and consumes less current during standby.

FIG. 15 is a block diagram showing a configuration example of a NAND cell type EEPROM for explaining a semiconductor memory device to which the above-described voltage bias circuit is applied. This NAND cell type EEPROM includes memory cell arrays 1A and 1B, sense amplifiers and data latches 2 for writing and reading data, row decoders 3A and 3B for selecting word lines, column decoders 4 for selecting bit lines, and an address buffer. 5, an I / O sense amplifier 6, a data output buffer 7, a substrate potential control circuit 8, bit line precharge circuits 9A and 9B, a step-down circuit 10, and the like. This NAND type EE
The PROM is an open bit line system, and the memory cell arrays 1A and 1B are divided into two, and the row decoders 3A and 3B and the bit line precharge circuit 9
A and 9B are provided. In addition, the external power supply voltage Vcc
And two types of pads PD1 and PD2 for receiving
The power supply voltage Vcc1 applied to the pad PD1 is stepped down by the step-down circuit 10 to generate an in-chip power supply voltage Vdd, and the sense amplifier / data latch 2, the row decoders 3A and 3
B, column decoder 4, address buffer 5, and I /
The O-sense amplifiers 6 are respectively supplied as power. Further, the external power supply voltage Vcc2 supplied to the pad PD2 is supplied as a power supply to each of the data output buffer 7, the substrate potential control circuit 8, and the bit line precharge circuits 9A and 9B. Vcc1 and Vcc
2 is a common terminal Vcc outside the chip.

FIG. 16 is a circuit diagram showing a configuration example of the memory cell array 1A in the circuit shown in FIG.
As shown in the figure, NAND cells are arranged in a matrix, and the first selection transistor of each NAND cell is a bit line BL0A, BL1A, BL2A, BL3A, B
, And the second selection transistor is connected to the source line. The source lines are commonly connected to a reference potential wiring. The first and second select gates in each NAND cell MC are connected to the bit lines BL0A, B0B.
The selection gate lines SG1 and SG2 arranged in a direction intersecting L1A, BL2A, BL3A, BL4A,... Are connected for each row (or column), and the control gate of the memory cell in each NAND cell is connected to the selection gate. Control gate lines CG1 to CG8 arranged in parallel with the lines SG1 and SG2 are connected for each row (or column).

Various variations are conceivable for the configuration of the memory cell section.
ND type EEPROM (H. Kume et al .; I
EDM Tech. Dig. , Dec. 1992, p
p. 991-993), DINOR type and the like. Further, the present invention is not limited to the EEPROM, but is also effective for a so-called EPROM or mask ROM.

FIG. 17 shows bit lines BL2A, BL2A,
FIG. 4 is a circuit diagram showing a configuration example of a sense amplifier / data latch circuit 2 to which a BL3A is connected. SS3A, S in FIG.
S4A is biased by the voltage bias circuit shown in FIG. However, in this case, what is described as Vcc in FIG. 14 is the step-down power supply Vdd in the chip. That is, during standby, SS3A and SS4A supply the power supply voltage V via the p-channel transistors Tr20 and Tr21 in FIG.
dd.

FIG. 18 shows a configuration example of the bit line precharge circuits 9A and 9B in the circuit shown in FIG. This circuit has an inverter circuit configuration operated by the power supply voltage Vcc2, and inverts the input signal PREA to generate the signal BLPREA.

Next, a writing procedure when writing to the memory cell MC1 in the circuit shown in FIG. 16 will be described below. FIG. 19 is a timing chart of this write operation. As shown in FIG. 17, in this embodiment, two bit lines are shared by one sense amplifier. Therefore, one bit line is selected from the two bit lines. For example, when writing to MC1, the memory cells MC2 and MC3 in FIG. 16 are not selected for writing. The write data of the memory cell MC1 is supplied from the bit line BL2A, and the memory cells MC2 and MC3 are supplied with the bit line BL1.
A and BL3A apply a write non-selection potential.

The data to be written into the memory cell MC1 in FIG. 16 is latched in the sense amplifier circuit (SA1 in FIG. 17). That is, in the case of "0" write, the node N1
Is 0V, N2 is Vdd, and in the case of "1" write, the node N1 is at Vdd and N2 is at 0V.

When entering the write operation, SS3A is first set to VH at time t1. VH is the bit line BL3A, BL
For example, the voltage may be 6 V so that 1 A can be charged to the power supply voltage Vdd (for example, 2.5 V). On the other hand, bit line precharge activation signal PREA attains "L" level, and signal BLPREA is charged to power supply voltage Vdd. As a result, the bit lines BL1A and BL3A are charged to the power supply voltage Vdd. The bit line BL2A is set to reflect the write data of the sense amplifier SA1. In the case of “0” writing, BL2A is set to 0V. In the case of "1" writing, the bit line BL2A is charged to the power supply voltage Vdd.

At time t2, control gates CG1, CG2,
..., CG8 is boosted. The selected control gate CG1 has V
pgm (about 20 V), non-selection control gates CG2, CG
, CG8 are boosted to Vpass (about 10V). As a result, the memory cell MC1 for writing "1" and the channels of the memory cells MC2, MC3 which are not selected to be written have an intermediate potential (about 8V) control gate CG1 at Vpp. (20
V), these memory cells are not written, but the channel of the memory cell for writing “0” is 0
Since V and the control gate are Vpp (about 20 V), electrons are injected from the substrate to the floating gate, and "0" writing is performed. After the end of writing, SS3A is charged from high voltage VH to power supply voltage Vdd via high voltage switch 2 in FIG. SS4A may be charged to the power supply voltage Vdd via the p-channel transistor in FIG. 14, or may be charged to the power supply voltage Vdd via the high voltage switch SW2. In the standby state after the end of writing, the voltages V1, V2,
By setting V3 to the ground voltage Vss and V4 to the power supply voltage Vdd, the node Na is biased to the power supply voltage Vdd. The reason why SS3A and SS4A are set to the power supply voltage Vdd during standby is to ground the bit line to 0V via the signal BLPREA even in a standby state after the end of writing. The reason why it is preferable to ground the bit line during standby (standby) is as follows. The bit line to which read data is output needs to be grounded to 0 V before performing a read operation. For example, when reading is performed immediately after the end of writing, there is a possibility that erroneous reading may occur if charges remain on the bit line. In the method in which SS3A and SS4A are grounded to 0 V during standby, writing must be completed after the bit line is sufficiently discharged until the bit line is discharged to 0 V, and the writing time increases. Alternatively, since the bit line needs to be discharged after the read command is input, the read time increases. As in the present invention, SS3
In the method in which A and SS4A are set to the power supply voltage Vdd during standby and the bit line is grounded, for example, the bit line can be grounded even while a read command is input, so that the write time or read time can be reduced.

[0094]

As described above, according to the present invention,
A nonvolatile semiconductor memory device capable of shortening the bit line discharge time and shortening the read time can be obtained.

Further, a semiconductor memory device which can prevent erroneous reading even if the potential of the control gate floats due to capacitive coupling noise between the channel and the control gate can be obtained.

Further, it is possible to obtain a voltage bias circuit that can reduce the time required to change a predetermined node to which a bias voltage is applied from a high voltage to a power supply voltage and also reduce current consumption.

Furthermore, a voltage bias circuit that can prevent latch-up even when a predetermined node is directly discharged from a high voltage to a power supply voltage can be obtained.

[Brief description of the drawings]

FIG. 1 is for describing a semiconductor memory device according to an embodiment of the present invention, and is a NAND cell type EEPR.
FIG. 2 is a block diagram illustrating a schematic configuration of an OM.

FIG. 2 is a circuit diagram showing a configuration example of a sense amplifier and data latch circuit in the circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration example of a row decoder in the circuit shown in FIG. 1;

FIG. 4 is a sectional view schematically showing a well configuration of the NAND type EEPROM shown in FIG. 1;

FIG. 5 is a NAND type EEPROM shown in FIGS. 1 to 4;
This is for describing the read operation of M.
(A) shows the bit line precharge, (b) shows the bit line discharge, (c) shows the "1" readout, and (d) shows the "0" readout in order to explain the relation of potential application. Figure.

FIG. 6 is a timing chart for explaining a read operation of the NAND type EEPROM.

FIG. 7 is a timing chart for explaining a negative threshold read mode of the NAND type EEPROM.

FIG. 8 is a timing chart for explaining a write operation of the NAND type EEPROM.

FIG. 9 is a timing chart for explaining another write operation of the NAND type EEPROM.

FIG. 10 is a timing chart for explaining a write verify mode of the NAND type EEPROM.

FIG. 11 is a timing chart for explaining an over program verify read operation of the NAND type EEPROM.

FIG. 12 is a timing chart for explaining an erase verify read operation of the NAND type EEPROM.

FIG. 13 is a diagram showing a voltage bias circuit according to an embodiment of the present invention.

FIG. 14 is a diagram showing another voltage bias circuit according to the embodiment of the present invention.

15 is a diagram for explaining a semiconductor memory device to which the voltage bias circuit shown in FIG. 14 is applied;
FIG. 2 is a block diagram illustrating a configuration example of an ND cell type EEPROM.

16 is a circuit diagram showing a configuration example of a memory cell array in the circuit shown in FIG.

17 is a diagram showing a configuration example of a sense amplifier / data latch circuit to which bit lines are connected in FIG. 16;

18 is a diagram showing a bit line precharge circuit in the circuit shown in FIG.

FIG. 19 is a timing chart showing a write procedure when writing to the memory cell of FIG. 16;

20A and 20B are diagrams for explaining a conventional semiconductor memory device. FIG. 20A is a plan view of a pattern of one NAND cell part of a memory cell array in a NAND type EEPROM, and FIG. 20B is an equivalent circuit diagram thereof.

21A is a cross-sectional view of the pattern shown in FIG. 20A, FIG. 21A is a cross-sectional view taken along line AA ′, and FIG. 21B is a cross-sectional view taken along line BB ′.

FIG. 22 is an equivalent circuit diagram of a memory cell array in which the NAND cells shown in FIGS. 20 and 21 are arranged in a matrix.

FIG. 23 is a circuit diagram showing a conventional voltage bias circuit.

[Explanation of symbols]

1, 1A, 1B: memory cell array, 2: sense amplifier / latch circuit, 3, 3A, 3B: row decoder, 4: column decoder, 5: address buffer, 6: I / O sense amplifier, 7: data output buffer, 8 ... substrate potential control circuit, 9A, 9B ... bit line precharge circuit, 10 ...
Step-down circuit, Q11-Q19 ... transistor, CB2, C
B3: Capacitor, SW2, SW3: High voltage switch.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/788 H01L 29/78 371 29/792 (72) Inventor Tomoharu Tanaka 580-1 Horikawacho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture No. F-term in Toshiba Semiconductor System Technology Center (reference) 5B025 AA00 AB01 AC01 AD10 AD12 AE05 AE06 AE08 5F001 AA25 AB08 AC02 AD12 AD41 AD44 AD53 AE03 AE30 AF10 AG40 5F083 EP02 EP23 EP76 ER03 ER09 ER14 GA03 LA04 LA05 LA08 LA09 LA12

Claims (18)

[Claims] A memory cell unit including at least one nonvolatile memory cell; a bit line connected to one end of the memory cell unit; a first transistor connecting the bit line to a first node; A second transistor for setting a first sense node to a predetermined potential; and a third transistor for detecting a potential of the first sense node, wherein a gate electrode of the first transistor is connected to a first electrode during reading. By setting the bit line to the first precharge potential, and then setting the gate electrode of the first transistor to the second clamp potential, thereby setting the first sense node to the first precharge potential. A semiconductor memory device characterized by sensing with a third transistor. 2. The semiconductor memory device according to claim 1, wherein said second clamp potential is lower than said first clamp potential. 3. The semiconductor memory device according to claim 1, wherein the substrates of the first, second, and third transistors include impurities of the same polarity. 4. A memory cell unit including at least one memory cell; a first selection transistor connecting the memory cell unit to a first signal line; and a second signal line connected to the memory cell unit In the operation of flowing a current from the second signal line to the first signal line via the memory cell portion, after applying a predetermined voltage to the gate of the memory cell,
So that the first selection transistor is turned on,
A semiconductor memory device, wherein a predetermined voltage is applied to a gate of the first selection transistor. 5. A memory cell section including at least one memory cell, a first selection transistor connecting the memory cell section to a first signal line, and connecting the memory cell section to a second signal line. A second selection transistor, wherein in the operation of flowing a current from the second signal line to the first signal line via the memory cell portion, the second selection transistor is turned on.
After applying a predetermined voltage to the gate of the second selection transistor, applying a predetermined voltage to the gate of the first selection transistor so that the first selection transistor is turned on. Semiconductor storage device. 6. A memory cell portion including at least one memory cell, a first selection transistor connecting the memory cell portion to a first signal line, and connecting the memory cell portion to a second signal line. A second selection transistor, wherein in the operation of flowing a current from the second signal line to the first signal line via the memory cell portion, the second selection transistor is turned on.
Applying a predetermined voltage to the gate of the second selection transistor, and applying a predetermined voltage to the gate of the memory cell, so that the first selection transistor is turned on. A predetermined voltage is applied to the gate of the semiconductor memory device. 7. A memory cell unit including a plurality of memory cells connected in series to each other, a first selection transistor connecting the memory cell unit to a first signal line, and a memory cell unit and a second signal. And a second selection transistor for connecting a line, wherein in the operation of flowing a current from the second signal line to the first signal line via the memory cell portion, the second selection transistor is turned on. To
Applying a predetermined voltage to the gate of the second selection transistor, applying a read voltage to a selected memory cell of the memory cell unit, and turning on an unselected memory cell of the memory cell unit; A semiconductor, wherein a predetermined voltage is applied to the gate of the first selection transistor so that the first selection transistor is turned on after a predetermined voltage is applied to the gate of the unselected memory cell. Storage device. 8. A memory cell unit including at least one memory cell, a first selection transistor connecting the memory cell unit to a first signal line, and connecting the memory cell unit to a second signal line. A second selection transistor, so that when reading data stored in the memory cell, the second selection transistor is turned on.
Applying a predetermined voltage to the gate of the second selection transistor, and applying a predetermined voltage to the gate of the memory cell, so that the first selection transistor is turned on. A predetermined voltage is applied to the gate of the semiconductor memory device. 9. The semiconductor memory device according to claim 4, wherein said first signal line is a source line, and said second signal line is a bit line. 10. A first switch circuit disposed between a first voltage terminal and a first node, and a second switch disposed between the first voltage terminal and the first node. A voltage bias circuit, comprising: 11. A first switch circuit, disposed between a first voltage terminal and a first node, for discharging a charge of the first node to the first voltage terminal; and a first voltage terminal. And between the first node and
A second switch circuit configured to charge the first voltage terminal to the first node. 12. A first switch circuit disposed between a first voltage terminal and a first node, and a second switch disposed between the first voltage terminal and the first node. A circuit, and a third switch disposed between the first node and a second voltage terminal to which a second voltage higher than the first voltage applied to the first voltage terminal is applied. A voltage bias circuit, comprising: 13. A first switch circuit disposed between a first voltage terminal and a first node, and a second switch disposed between the first voltage terminal and the first node. A circuit, and a third switch disposed between the first node and the second voltage terminal to which a second voltage higher than the first voltage applied to the first voltage terminal is applied. A third circuit to which a third voltage lower than the first voltage is applied;
And a fourth switch circuit disposed between the first voltage node and the first node. 14. The first switch circuit according to claim 1, wherein
And discharging the electric charge of the first node to the first voltage terminal, and the second switch circuit charges the electric charge from the first power supply terminal to the first node.
14. The voltage bias circuit according to 2 or 13. 15. The voltage bias according to claim 10, wherein the first switch circuit operates during a period other than a standby period, and the second switch circuit operates during a standby period. circuit. 16. The semiconductor device according to claim 10, wherein the first switch circuit includes an n-channel MOS transistor, and the second switch circuit includes a p-channel MOS transistor. A voltage bias circuit as described. 17. The voltage bias circuit according to claim 10, wherein the first voltage is a power supply voltage. 18. The voltage bias circuit according to claim 13, wherein the first voltage is a power supply voltage, and the third voltage is a ground voltage.