JP2000236078A - Nonvolatile semiconductor memory storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory storage on which the boosting voltage of the conducting layer formed on a control gate can be fully transmitted to the channel of a selective memory cell and the affection of disturb can be reduced. SOLUTION: A conductive layer 18 is formed on the control gate of each memory cell on a memory column via an insulating film 17, and the conductive layer 18 is connected to an impurity region 11-1 located between a bit line side selective transistor 21 and its adjacent memory cell M1 via a contact 24. When a write-in operation is performed, high programming voltage is applied to a selective word line, path voltage is applied to other work line, a power source voltage VCC is applied to the gate of the selective transistor 21. The boosting voltage of the conductive layer 18 is applied to a non-selective memory cell, and as the memory cell located between the selective memory cell and the bit line has a negative threshold voltage in erasing state, the high-speed transmission of boosting voltage can be accomplished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device which reduces a write disturbance by increasing a channel voltage of a non-write memory cell.

[0002]

2. Description of the Related Art In a so-called NAND type nonvolatile memory in which a plurality of memory cells are connected in series between a bit line and a source line, a positive high voltage is applied to a control gate of a memory cell to be written at the time of programming. (Hereinafter referred to as programming voltage) V _pgm
Set the drain, source and channel regions of the memory cell to 0
Hold at V. As a result, a high voltage is applied to the tunnel insulating film of the memory cell to be written, and electrons are injected into the floating gate by FN tunneling, so that the threshold voltage of the memory cell increases and the threshold of the memory cell in the erased state is increased. Value voltage. At the time of reading, when a predetermined read voltage is applied to the control gate of the selected memory cell, the sense amplifier detects the current flowing through the memory cell, thereby detecting the threshold voltage of the selected memory cell and storing the data according to the threshold voltage. The data is read.

In the above-described programming operation, of the other memory cells connected to the same selected word line, a memory cell that does not perform writing (hereinafter, an unselected memory cell) receives a write disturbance. Ideally, it is desirable to keep the threshold voltage of the unselected memory cells in the erased state, but since the programming voltage V _pgm is applied to the control gate at the time of programming, the source of the unselected memory cells, If the drain and channel regions cannot be held at a sufficiently high voltage, FN
Since tunneling occurs and electrons are injected into the floating gate, its threshold voltage increases somewhat.

For this reason, 0V is usually applied to the drain, source and channel regions of the unselected memory cells by some method.
And an intermediate voltage between the programming voltage V _pgm and the so-called inhibit (inhibit) voltage V _inh . This prohibition voltage V _inh can be applied directly from the bit line. However, to drive a bit line with a large parasitic capacitance at high speed, the load of the booster circuit is large and the driving circuit requires high driving capability. Is difficult. In addition, since it is necessary to design a circuit in consideration of the withstand voltage of a sense amplifier connected to a bit line, a method of boosting the channel voltage of an unselected memory cell by a method such as self-boost or local self-boost at present is generally used. Has been adopted.

In a boosting method such as self-boost and local self-boost, a channel voltage is boosted according to a coupling ratio between a control gate-floating gate capacitance, a floating gate-channel capacitance, and a channel-well capacitance of an unselected memory cell. Things. The coupling ratio of this capacitance is defined as the channel boost ratio (Channel boos
This is referred to as “t ratio”, and the channel voltage of the non-selected memory cell is boosted to a required prohibition voltage during programming, so that a high boosting rate is required.

As the density and capacity of a semiconductor memory device increase, the gate length of a memory cell decreases. by this,
Since the channel boosting rate is also low, the channel voltage of the non-selected memory cell cannot be sufficiently boosted at the time of programming, which may cause disturbance.

In order to improve the channel boosting rate, there has been proposed a method in which an electrode is disposed on a control gate via an insulating film, and the electrode is connected to a source / drain of a memory cell. FIG. 3 is a simplified cross-sectional view showing a configuration of a nonvolatile semiconductor memory device in which an electrode is provided on a control gate.

As shown in FIG. 3, impurity regions 11-1, 11-2,.
−m + 1 is formed. The region sandwiched between these impurity regions is the channel forming region 12- of the memory cell.
1, 12-2, ..., 12-m. Tunnel insulating films 13-1, 13-2,
, 13-m are formed and floating gate 14- is electrically insulated thereon as a charge storage mechanism.
, 14-2, ..., 14-m are formed. Further, on each floating gate, an interlayer insulating film 15-1,
Control gate 1 through 15-2,..., 15-m
6-1, 16-2,..., 16-m are respectively formed. Thereby, a memory column in which m memory cells are connected in series is formed. One of the memory columns is connected to the source of the selection transistor 21, and is connected to the bit line 19 (BL) via the selection transistor 21. The other end of the memory column is connected to the drain of the selection transistor 22 and to the source line 23 (SL) via the selection transistor 22.

The control gates 16-1, 16-2,
.., 16-m, via an insulating layer 17 and a conductive layer 18
Are formed. The conductive layer 18 is formed of, for example, polysilicon. As shown in FIG.
8 is connected, for example, via a contact 24 to source / drain regions between memory cells forming a memory column. In FIG. 3, the conductive layer 18 is connected to an impurity region 11-3 serving as a source / drain region of a memory cell.

At the time of programming, the voltage of the conductive layer is boosted by capacitive coupling between the conductive layer 18 and the control gate. Then, since the boosted voltage is applied to the source / drain regions of the memory cell, the voltage of the channel region of the memory cell that receives the write disturbance is boosted higher than in the case where the conductive layer 18 is not provided. That is, the conductive layer 18 is further formed on the control gate.
Is formed, the channel boosting rate is improved, the channel voltage of the non-selected memory cells is boosted at the time of programming, and the influence of disturb can be reduced.

[0011]

In the above-mentioned nonvolatile semiconductor memory device, the conductive layer 18 is connected to the source / drain region of the memory cell in the middle of the memory column. There is a disadvantage that the boosted voltage of 18 is not sufficiently transmitted to the non-selected memory cells receiving the disturbance.

During programming, unselected memory cells that are connected to the selected word line and maintain the threshold voltage in the erased state receive disturbance. For example, when the memory cell on the bit line side from the short-circuit point between the conductive layer 18 and the memory column is connected to the selected word line, the memory cell is connected between the unselected memory cell connected to the selected word line and the short-circuit point. In some cases, the arranged memory cells have already been written and the threshold voltage is set high. For example, in FIG. 3, when the word line to which the control gate of the memory cell M1 is connected is selected, during programming, the boosted voltage of the conductive layer 18 is applied to the memory cell M1 via the channel formation region of the memory cell M2. (Impurity region 11-2). When the memory cell M2 has already been written and its threshold voltage is kept at a high level, the boosted voltage of the conductive layer 18 cannot be sufficiently transmitted to the source and channel formation region of the memory cell M1. Further, even if this boosted voltage is transmitted to memory cell M1, the time required for the transmission is long. As a result, during programming, the memory cell M
One channel cannot be boosted to a sufficient voltage, and the threshold voltage of the memory cell M1 rises due to the influence of the disturbance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to enable a boosted voltage of a conductive layer formed on a control gate to be sufficiently transmitted to a memory cell receiving a write disturbance and to increase a boosted voltage. It is an object of the present invention to provide a nonvolatile semiconductor memory device which can reduce the influence of disturbance by shortening the voltage transmission time.

[0014]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises a plurality of memory cells each having a charge storage layer and a control gate for controlling transfer of charges to and from the charge storage layer. Are arranged in a matrix, the memory cells of each column are connected in series, one of the memory cell columns is connected to the bit line, the other is connected to the source line, and the memory cells of the memory cells arranged in the same row are connected. A non-volatile semiconductor memory device in which a control gate is connected to one word line, comprising a conductive layer formed on the control gate of each memory cell via an insulating layer, The layer is connected to an impurity region of a memory cell arranged closest to the bit line in the memory cell column.

In the present invention, preferably, a first selection transistor is connected between one of the memory cell columns and the bit line, and a control terminal of the first selection transistor is connected to the control terminal during programming. For example, a power supply voltage is applied.

Further, in the present invention, preferably, a second selection transistor is connected between the other of the memory cell columns and the source line, and a selection terminal of the second selection transistor is used for programming. It is kept at a reference potential, for example, a ground potential.

Further, in the present invention, preferably, the first
And a contact formed between the conductive layer and an impurity region between the select transistor and a memory cell adjacent to the first select transistor in the memory cell column.

[0018]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention. As shown in FIG. 1, the nonvolatile semiconductor memory device of the present invention
This is a D-type non-volatile memory, and is composed of a plurality of memory cells arranged in a matrix. The memory cells in each column are connected in series between the bit line and the source line CSL, and the memory cells in each row are connected to the same word line. Memory cells connected to one word line constitute one memory page. Typically, programming is done on a page-by-page basis.

In the NAND type nonvolatile memory shown in FIG. 1, in addition to the memory cell array, a control circuit 100, a decoder 101, a column selection circuit 102, a sense amplifier 10
3 and an input / output circuit (I / O circuit) 104 are provided. The control circuit 100 generates a control signal for controlling the operation of each part of the nonvolatile memory, and outputs the control signal to each partial circuit.

The decoder 101 includes a plurality of word lines WL1
To WLm, a word line WL specified by the address signal ADR is selected, and a predetermined voltage is applied to the selected word line. For example, at the time of reading, a read voltage V _RD is applied to a selected word line, and a voltage is applied to all other unselected word lines such that non-selected memory cells are sufficiently turned on.
On the other hand, at the time of programming, a programming voltage V _pgm is applied to a selected word line, and a pass voltage V _pass intermediate between the programming voltage V _pgm and the ground potential GND is applied to other unselected word lines.

The column selection circuit 102 selects a predetermined number of bit lines from n bit lines BL1 to BLn.
Here, n is, for example, 512. The bit line selected at the time of reading is connected to the sense amplifier 103, and the potential of these selected bit lines is
Is detected by The threshold voltage of the selected memory cell can be determined from each bit line potential, storage data corresponding to the threshold voltage is read, and output to the outside through the I / O circuit 104. On the other hand, at the time of programming, write data input from the outside is input via the I / O circuit 104. The column selection circuit 102 inputs the write data input from the I / O circuit 104 to the selected bit lines.

The sense amplifier 103 determines the threshold voltage of the selected memory cell by detecting the current of the selected bit line or the bit line potential at the time of reading, and outputs data according to the threshold voltage. The I / O circuit 104 outputs data read by the sense amplifier 103 to the outside at the time of reading, and inputs write data from the outside to the column selection circuit 102 at the time of programming.

As described above, based on the control of the control circuit 100, the peripheral circuits of the memory cell array perform predetermined operations, and perform erasing, programming, and reading on the memory cell array. Hereinafter, a method of generating and preventing a disturbance in programming will be described with reference to a cross-sectional view of a memory column.

FIG. 2 shows a simplified sectional view of one memory column. As shown, m memory cells M1, M2, M2
, Mm are connected in series between the bit line BL and the source line SL to form a memory column. Each memory cell is formed with a floating gate formed on a channel forming region sandwiched between a source and a drain made of an impurity region via a tunnel insulating film, and formed on the floating gate via an interlayer insulating film. It is composed of a control gate. The floating gate is electrically insulated from the surroundings, and the charge accumulated therein is held semipermanently. Therefore, by applying an appropriate bias voltage to the control gate and the channel formation region of each memory cell by erasing or programming, a high voltage is applied to the tunnel oxide film and FN
By tunneling, electrons are extracted or injected into the floating gate of each memory cell, so that the threshold voltage of each memory cell can be set to a predetermined voltage value.

As shown in FIG. 2, impurity regions 11-1, 11-2,..., 11- (m + 1) forming source / drain regions of a memory cell at predetermined intervals in a surface region of a substrate 10.
Are formed. The region sandwiched between these impurity regions is the channel forming region 12-1,
, 12-m. The tunnel insulating films 13-1, 13-2,...
13-m are formed, and floating gates 14-1, 14 as a charge storage mechanism electrically insulated thereon are formed.
, 14-m are formed. Further, the interlayer insulating films 15-1, 15 are formed on each floating gate.
−2,..., 15-m through the control gate 16−
, 16-m are formed respectively. Thereby, m memory cells M1, M2, M3,.
A memory string in which Mm are connected in series is formed. One of the memory columns is connected to the source of the selection transistor 21 and is connected to the bit line 19 (BL) via the selection transistor 21 and the bit contact 20. The other end of the memory column is connected to the drain of the selection transistor 22 and to the source line (23) SL via the selection transistor 22.

The control gates 16-1, 16-2,
.., 16-m, via an insulating layer 17 and a conductive layer 18
Are formed. The conductive layer 18 is formed of a conductor such as polysilicon. As shown in FIG. 2, for example, the conductive layer 18 is connected via a contact 24 to an impurity region 11-1 between the memory cell M1 and the select transistor 21.

Hereinafter, the programming operation in the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIGS. Here, it is assumed that the word line to which the memory cell M3 is connected is the selected word line. Memory cell M3 is an unselected memory cell that receives write disturb during a programming operation. At the time of programming, the power supply voltage V _CC is applied to the bit line BL,
The power supply voltage V _CC is applied to the gate of the selection transistor 21, and a voltage of 0 V is applied to the gate of the selection transistor 22. In addition, a high programming voltage V _pgm is applied to the selected word line, and a pass voltage V _pass intermediate between the programming voltage V _pgm and 0 V is applied to non-selected word lines other than the selected word line.

The threshold voltage of the selection transistor 21 is V
_Assuming that the voltage is _th1, the voltage of the source of the selection transistor 21, that is, the voltage of the impurity region 11-1 is (V _CC -V _th1 ). The memory cells M1, M2, M3,..., Mm shown in FIG.
Among them, the control gate of the memory cell M3 is connected to the selected word line, the programming voltage V _pgm is applied at the time of programming, the control gates of the other memory cells are connected to the unselected word line, and the pass voltage V _pass is applied.

When the control gate of the memory cell M3 is held at the programming voltage V _pgm , the channel voltage V _{ch is determined} by the coupling ratio of the control gate-floating gate capacitance, floating gate-channel capacitance, and channel-well capacitance. Is boosted. Further, the control gate voltage increases due to capacitive coupling between the conductive layer 18 and the control gate.
Accordingly, the potential of the conductive layer 18 is boosted. The conductive layer 18 is connected to the selection transistor 21 through the contact 24.
Connected to the impurity region 11-1 between the memory cell M1 and the memory cell M1, the boosted voltage of the conductive layer 18 is transmitted to the source / drain and channel region of each transistor forming the memory column. Therefore, the memory cell M3
, The channel voltage V _ch further rises, and the channel voltage V _ch approaches the programming voltage V _pgm applied to the control gate, so that the occurrence of write disturbance in the memory cell M3 can be prevented.

In the NAND type nonvolatile memory shown in FIG. 1, programming is performed in page units from the source line side to the bit line side. Therefore, each memory cell on the bit line BL side from the memory cell connected to the selected word line remains in the erased state, and the threshold voltage becomes a negative voltage. For example, in FIG.
Is selected, the memory cells M1 and M2 on the bit line BL side are unwritten, and their threshold voltages are negative voltages in an erased state, for example, -2 to -4V. Therefore, in a state where the pass voltage V _pass is applied to the control gates of the memory cells M1 and M2, the boosted voltage of the conductive layer 18 is easily transferred from the impurity region 11-1 to the memory via the memory cells M1 and M2. Drain region 11-3 and channel formation region 1 of cell M3
2-3.

As described above, according to the present embodiment, m memory cells M1, M2,
, Mm are connected to the bit line BL via the selection transistor 21 and to the source line SL via the selection transistor 22. A conductive layer 18 is formed on a control gate of each memory cell via an insulating film 17, and the conductive layer 18 is connected via a contact 24 to a bit line side select transistor 21 and an adjacent memory cell M
1 is connected to the impurity region 11-1 located between the first region and the first region.
During programming, a positive high voltage programming voltage V _pgm is applied to the selected word line, and V
_Since the pass voltage V _pass intermediate between _pgm and 0 V is applied and the power supply voltage V _CC is applied to the gate of the selection transistor 21, the boosted voltage of the conductive layer 18 is transmitted to the unselected memory cells, and Since the memory cell between the memory cell and the bit line is in an erased state and the threshold voltage is a negative voltage, the transfer of the boosted voltage can be realized at high speed, the channel region of the selected memory cell is held at a high voltage, Disturbance can be prevented.

[0032]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the boosted voltage of the conductive layer formed on the control gate is quickly applied to the channel region of the non-selected memory cell during programming. There is an advantage that the transmission can be performed and occurrence of disturbance in the non-selected memory cell can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a NAND nonvolatile memory according to the present invention.

FIG. 2 is a simplified sectional view of a memory column of a NAND nonvolatile memory according to the present invention.

FIG. 3 is a simplified sectional view of a memory column showing an example of a conventional NAND type nonvolatile memory.

[Explanation of symbols]

10 ... substrate, 11-1, 11-2, ..., 11-m, 11
− (M + 1)... Impurity regions, 12-1, 12-2,.
12-m ... channel forming region, 13-1, 13-2,
..., 13-m ... tunnel insulating films, 14-1, 14-2,
..., 14-m ... floating gate, 15-1, 15
−2,..., 15-m... Interlayer insulating film, 16-1, 16−
2, ..., 16-m ... control gate, 17 ... insulating film, 18 ... conductive layer, 19 (BL) ... bit line, 20 ... bit contact, 21, 22, ... select transistor, 23
(SL): source line, 24: contact, 100: control circuit, 101: decoder, 102: column selection circuit, 1
03 ... sense amplifier, 104 ... I / O circuit, V _CC ... power supply voltage, GND ... ground potential.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA25 AB08 AB09 AB20 AC02 AC06 AD12 AD41 AD44 AD51 AD53 AE02 AE30 AF06 AF10 AG40 5F083 EP02 EP23 EP30 EP76 ER03 ER09 GA22 GA30 KA05 LA03 LA04 LA05 LA07 LA10 MA01 MA19

Claims (8)

[Claims] A plurality of memory cells each having a charge storage layer and a control gate for controlling transfer of charges to and from the charge storage layer are arranged in a matrix, and memory cells in each column are connected in series. A nonvolatile semiconductor memory device in which one of a cell column is connected to a bit line, the other is connected to a source line, and a control gate of a memory cell arranged in the same row is connected to one word line. A conductive layer formed on the control gate of each of the memory cells via an insulating layer, wherein the conductive layer is disposed closest to the bit line in the memory cell column. Nonvolatile semiconductor memory device connected to the impurity region of FIG. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a first select transistor is connected between one of said memory cell columns and said bit line. 3. The nonvolatile semiconductor memory device according to claim 2, wherein at the time of writing, a power supply voltage is applied to a control terminal of said first selection transistor. 4. A contact formed between an impurity region between the first select transistor and a memory cell in the memory cell row adjacent to the first select transistor and the conductive layer. 3. The nonvolatile semiconductor memory device according to claim 2, comprising: 5. The nonvolatile semiconductor memory device according to claim 1, wherein a second select transistor is connected between the other of said memory cell columns and said source line. 6. The nonvolatile semiconductor memory device according to claim 5, wherein a control terminal of said second selection transistor is held at a reference potential during writing. 7. A memory page is constituted by a plurality of memory cells connected to the word line, and data is written from the source line side to the bit line side.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the operation is sequentially performed for each of said memory pages. 8. The nonvolatile memory according to claim 1, further comprising a write control means for applying a high voltage to a selected word line and applying a voltage between said high voltage and a reference potential to a non-selected word line in said writing. Semiconductor storage device.