JPH04219978A - Composite-type semiconductor device - Google Patents

Abstract

PURPOSE:To increase a blocking operation by a method the characteristics of a unit in an electrostatic induction thyristor are set such that wherein a voltage which can be blocked between an anode and a cathode at room temperature when the gate and the cathode are short-circuited is set to a prescribed value or higher. CONSTITUTION:A bias circuit 6 is constituted by connecting a diode 3 as a bias means in the forward direction between a gate 10G at an SI thyristor 10 and a source 2S at a MOSFET 2. The SI thyristor 10 is constituted of SI thyristor units having such characteristics as a voltage which can be blocked between an anode and a cathode when the gate and the cathode are short- circuited is at 0.7V or higher and 10V or lower at room temperature at an anode current of 10mA. Thereby, the voltage of the SI thyristor can be controlled by using the MOSFET whose ON-resistance is low, and a total loss can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a composite semiconductor device combining a static induction thyristor and a MOSFET.

0002

2. Description of the Related Art In recent years, in the field of power semiconductors, there has been an increasing demand for devices that can handle higher frequencies in order to improve the efficiency and reduce noise of applied equipment. Electrostatic induction thyristors (hereinafter referred to as SI thyristors) are recognized to have superior high frequency characteristics compared to other power semiconductors. However, S
I-thyristors have the disadvantage that a large current must be drawn from the gate at turn-off, making the gate circuit more complex than other semiconductors. Therefore, by connecting the cathode of the SI thyristor to the drain of the n-channel MOSFET, and the gate of the SI thyristor to the source of the n-channel MOSFET (cascode connection), high-speed S
A report that an I thyristor can be easily driven as a voltage-controlled device (B.J. BaligaSolid-S
t. Electron 25, No. 5, PP345-
353, 1982).

4 to 7 show equivalent circuits of this type of conventional composite semiconductor device. In FIG. 4, 1 is a static induction thyristor (SI thyristor), 2 is a MOSFET, and the cathode of SI thyristor 1 is MOSFET2 for 1K
The drain 2D of the SI thyristor 1 is connected to the gate 1G of the SI thyristor 1, and the source 2S of the MOSFET 2 is connected to the gate 1G of the SI thyristor 1.
Thyristor 1 and MOSFET 2 are connected in cascode (cascade). 1A is the anode of SI thyristor 1, 2
G is the gate of the MOSFET. Also, in Figure 5, 3 is S
This is a diode connected between the gate 1G of the I thyristor 1 and the source 2S of the MOSFET 2. Furthermore, in FIG. 6, 4 is the gate 1G of the SI thyristor 1 and the MOSFE.
This is a Zener diode connected between the source 2S of T2.

0004

[Problem to be solved by the invention] MO as shown in FIG.
SI thyristor 1 only turns on and off by turning on and off SFET2.
In the cascode connection method in which the SI thyristor 2 is turned on and off (no special gate current is applied to turn the SI thyristor on and off), when no reverse bias is applied to the gate of the SI thyristor 2, the forward characteristic is similar to that of a diode. A fully normally-on SI thyristor is required that exhibits the following characteristics.

When using a device that exhibits characteristics that are normally off or intermediate between normally on and off, such as blocking a certain amount of voltage when no gate bias is applied, in a cascode connection as shown in FIG. becomes significantly worse or does not turn on at all, requiring gate current to turn on. However, a completely normally-on type SI thyristor has a smaller anode voltage that can be blocked with the same gate reverse voltage than a normally-off type SI thyristor.

Normally, in a normally-on type SI thyristor, it takes 100V to block an anode voltage of 1000V.
Requires a gate voltage of V or higher. For this reason, MOSFE
The withstand voltage of T must also be 100V or higher. MOSF
Since the on-resistance of ET is proportional to the 2.5th power of the breakdown voltage, MO
Increasing the withstand voltage of SFET will increase the steady loss during cascode connection. Therefore, in order to increase the withstand voltage of the cascode-connected device in Figure 4, MO
It is also necessary to increase the withstand voltage of SFET, so 100
It is practically difficult to configure a device with a voltage of 0 V or higher using the cascode connection shown in FIG. 4 due to loss.

On the other hand, as shown in FIG.
A diode 3 is connected in the forward direction between the gate 1G of the MOSFET 2 and the source 2S of the MOSFET 2, and a cascode connection in which a Zener diode 4 is inserted in the reverse direction as shown in Fig. 6 is also considered. When turned on, the built-in voltage of the diode 3 or the Zener voltage of the Zener diode 4 is applied to the SI thyristor 1 as an on-gate voltage, so it is close to normally off. Therefore, cascode connection can now be applied to SI thyristors that can block large anode voltages with a small gate reverse bias. However, even with this configuration, although forward bias can be applied between the gate and cathode of the SI thyristor 1 at turn-on, it is impossible to supply a sufficient gate current. For this reason, the devices shown in FIGS. 5 and 6 had problems in that the turn-on characteristics were significantly worse than in the case of a single SI thyristor, and the on-voltage was increased.

For this reason, as shown in FIG. 7, a MOSFET 5 is further connected between the anode and cathode of the SI thyristor 1 to form a composite semiconductor device with a four-terminal structure, but the circuit configuration is complicated. .

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a low-loss composite semiconductor device that enables high-speed switching operation in a cascode-connected SI thyristor and MOSFET. It is.

0010

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for converting the cathode of an electrostatic induction thyristor into a MOS.
The anode of the electrostatic induction thyristor is connected to the drain of the FET as a first electrode, and the gate of the electrostatic induction thyristor is connected to the source of the MOSFET as a second electrode taken out to the outside. In a composite semiconductor device in which the gate is the third electrode, a bias circuit is connected between the gate of the electrostatic induction thyristor and the source of the MOSFET, and the electrostatic induction thyristor has characteristics such that the thyristor alone has characteristics similar to that of the gate.
A voltage that can be blocked between the anode and the cathode when a short circuit occurs between the cathodes is 0.7 V or more and 10 V or less at room temperature when the anode current is 10 mA.

[0011]

[Operation] In a composite semiconductor device in which an SI thyristor and a MOSFET are connected in cascode, the voltage of the SI thyristor is controlled by a MOSFET with low on-resistance, and
Reduce total loss.

0012

Embodiments Examples of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows a composite semiconductor device according to an embodiment of the present invention. In the three-terminal composite semiconductor device according to this embodiment, the anode 10 of the SI thyristor 10
A is the first electrode 5A, the cathode 10K of the SI thyristor 10 is connected to the drain 2D of the MOSFET 2, and the gate 10G of the SI thyristor 10 is connected to the MOSFET 2.
A second electrode 5B connected to the source 2S of and taken out to the outside.
At the same time, the gate 2G of the MOSFET 2 is connected to the third
In the electrode 5C of the SI thyristor 10, a diode 3 is connected in series in the forward direction as a bias means between the gate 10G of the SI thyristor 10 and the source 2S of the MOSFET 2 to form a bias circuit 6. Characteristics of a single thyristor The voltage that can be blocked between the anode and cathode when the gate and cathode are short-circuited is at room temperature (25°C) when the anode current is 10 mA.
The voltage is 0.7V or more and 10V or less.

When a voltage is applied so that the first electrode 5A side has a positive potential and the second electrode 5B side has a negative potential, a voltage is applied between the gate 10G and the cathode 10K in the direction that the gate 10G has a negative potential. When no signal is applied, it is in a conductive state (it is a normally-on type element, and it is in a conductive state when no signal is applied to the gate).

On the other hand, when a voltage is applied between the gate 10G and the cathode 10K in such a direction that the gate 10G has a negative potential, a part of the anode current passes through the gate region and is swept out of the gate electrode, and the channel part has a high resistance with little charge. A depletion layer (space charge layer) is formed, resulting in a blocking state.

That is, in order to turn on the SI thyristor 10, the reverse voltage applied to the gate 10G is removed, and a diode current flows through the channel, turning it on. It also turns off (turns off) the anode current in the conducting state.
(blocked state), a reverse voltage is applied to the gate 10G to block the channel with a high resistance depletion layer.

The MOSFET 2 and the SI thyristor 10 are turned on and off at a predetermined period, and a main current flows from the first electrode 5A through the SI thyristor 1 and the MOSFET 2.

In a normally-on type SI thyristor, when the gate and cathode of the SI thyristor are short-circuited, the voltage-current characteristic between the anode and the cathode exhibits the forward direction characteristic of a diode. In other words, the voltage that can be blocked between the anode and cathode when the gate and cathode are shorted (VDR
(abbreviated as MS) is approximately 0.6V. In addition, normally-on type SI thyristors usually require a gate bias of 100V or more to block the 1000V anode-cathode voltage. The ratio of this anode-cathode voltage to the gate bias required to maintain this voltage is called blocking gain (μ). (in this example μ
is 10 or less. ) As the SI thyristor moves from a normally-on type to a normally-off type, VDRMS increases and μ also increases. When completely normally off, VDRMS becomes equal to the maximum voltage (breakdown voltage) obtained by applying a reverse bias to the gate and cathode. Further, the value of μ is also 200 or more.

FIG. 2 shows a composite semiconductor device according to another embodiment of the present invention. In this embodiment, the gate 10G of the SI thyristor 10 and the source 2 of the MOSFET 2
A bias circuit 8 is formed by connecting Zener diodes 4 in series in the opposite direction between S and S.

[0020] SI thyristors with various gate spacing (channel width) and gate depth were manufactured as prototypes, and the above VDR
FIG. 3 shows the relationship between MS and .mu. and the ratio of turn-off time when a single SI thyristor and this SI thyristor are connected in cascode as shown in FIG. 2 with respect to VDRMS. As is clear from Fig. 3, the cascode connection as shown in Fig. 2 using an SI thyristor with VDRMS exceeding 50V at an anode current of 10 mA will no longer turn on, and the ratio of the turn-on time of a single SI thyristor to that of a cascode connection is becomes 0.

[0021] If VDRMS at an anode current of 10 mA is 10 V or less, the turn-on time during cascode connection is 1.2 times or less than when using a single SI thyristor. On the other hand, the turn-off time becomes about 0.5 to 0.7 times faster when a cascode connection as shown in FIG. 2 is used compared to a single SI thyristor. Therefore, the total switching loss becomes lower in the cascode connection when the above-mentioned VDRMS becomes 10V or less.

[0022] Also, VDRMS at room temperature is 0.7V.
If it is above, μ can be set to 10 or more,
It becomes possible to voltage control an SI thyristor of 1000V or more using a MOSFET with a relatively low on-resistance of 100V or less.

[0023]

As described above, the present invention improves the characteristics of a single electrostatic induction thyristor such that the voltage VDRMS that can be blocked between the anode and cathode at room temperature when the gate and cathode are short-circuited is 0.7V or more. By doing so, it becomes possible to increase blocking in to 10 or more. This makes it possible to convert high voltage SI thyristors of 1000V or more into MOSFETs with low on-resistance of 100V or less.
It becomes possible to control the voltage.

Furthermore, by setting VDRMS at room temperature to 10 V or less, the turn-on time can be suppressed to 1.2 times or less compared to the case of a single electrostatic induction thyristor. On the other hand, in the case of cascode connection, the turn-on time is dI/dt of the current drawn from the gate of the electrostatic induction thyristor.
is steeper than that of a single electrostatic induction thyristor, so 3
The improvement is approximately 0 to 50%. Therefore, the total loss is superior to the cascode connection, and the voltage control type is 20KH.
A composite device that can operate at z or higher can be realized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a composite semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a composite semiconductor device according to another embodiment of the present invention.

FIG. 3 is a characteristic diagram of the composite semiconductor device in FIG. 2;

FIG. 4 is a circuit diagram of a conventional composite semiconductor device.

FIG. 5 is a circuit diagram of a conventional composite semiconductor device.

FIG. 6 is a circuit diagram of a conventional composite semiconductor device.

FIG. 7 is a characteristic diagram of a conventional composite semiconductor device.

[Explanation of symbols]

2...MOSFET, 2D...drain, 2S...source, 2
G... Gate, 3... Diode, 4... Zener diode, 5A... First electrode, 5B... Second electrode, 5C... Third electrode, 8... Bias circuit, 10... Electrostatic induction thyristor,
10A...anode, 10K...cathode, 10G...gate.

Claims (3)

[Claims] [Claim 1] The cathode of the electrostatic induction thyristor is MO
The anode of the electrostatic induction thyristor is connected to the drain of the SFET as a first electrode, and the gate of the electrostatic induction thyristor is connected to the source of the MOSFET as a second electrode taken out to the outside. In a composite semiconductor device having a gate as a third electrode, a bias circuit is connected between the gate of the electrostatic induction thyristor and the source of the MOSFET, and the characteristics of the electrostatic induction thyristor alone are gate and cathode. 1. A composite semiconductor device characterized in that the voltage that can be blocked between an anode and a cathode when short-circuited between them is 0.7 V or more and 10 V or less at room temperature when the anode current is 10 mA. 2. The composite semiconductor device according to claim 1, wherein the bias circuit includes a diode connected in series in the forward direction between the gate of the electrostatic induction thyristor and the source of the MOSFET. 3. The composite semiconductor device according to claim 1, wherein the bias circuit includes a Zener diode connected in reverse series between the gate of the electrostatic induction thyristor and the source of the MOSFET.