JPH04167562A - Composite type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a composite type semiconductor device which is high in operation speed and low in power loss by a method wherein an electrostatic induction thyristor and a MOSFET are cascade-connected, and a bias circuit provided with a capacitor is connected between the source of the MOSFET and the gate of the SI thyristor. CONSTITUTION:The anode of an SI thyristor 1 is made to serve as a first electrode 5A, the cathode 1K of the SI thyristor 1 is connected to the drain 2D of a MOSFET 2, the gate 1G of the SI thyristor 1 is connected to the source 2S of the MOSFET 2 and made to serve as a second electrode 5B which is led outside, and the gate of the MOSFET 2 is made to a third electrode 5C. A resistor 6 serving as a bias means is connected between the gate 1G of the SI thyristor 1 and the source 2S of the MOSFET 2, a capacitor 7 is connected to the resistor 6 in parallel to constitute a bias circuit 8. By this setup, a composite type semiconductor device high in switching operation speed and low in power loss can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor device, and particularly to a composite semiconductor device that combines a static induction thyristor and a MOSFET.

B9 Summary of the Invention The present invention provides an electrostatic induction thyristor (Sl thyristor) and an M
In a composite semiconductor device consisting of OSFETs connected in cascode (cascade connection), by connecting a bias circuit with a capacitor between the source of the MOSFET and the gate of the Sl thyristor, a composite semiconductor device with high speed operation and low loss can be created. Get the equipment.

C1 Prior Art In recent years, in the field of power semiconductors, there has been an increasing demand for devices that can handle higher frequencies in order to improve the efficiency and reduce noise of applied equipment. Electrostatic induction thyristors (hereinafter referred to as Sl thyristors) are recognized to have superior high frequency characteristics compared to other power semiconductors. However, the Sl thyristor has the disadvantage that it is necessary to draw a large current from the gate at turn-off, making the gate circuit more complex than other semiconductors. Therefore, it has been reported that a high-speed Sl thyristor can be easily driven as a voltage-controlled device by connecting the cathode of the Sl thyristor to the train of an n-channel MOSFET and the gate of the Sl thyristor to the source of the n-channel MOSFET (cascode connection). B, J, BaligaSolid-St,
Electron 25. No, 5. P P
345-353.1982).

Figures 5 to 7 show equivalent circuits of this type of conventional composite semiconductor device. In Figure 5, 1 is a static induction thyristor (Sl thyristor), 2 is a MOSFET, and
The drain 2D of the MOSFET 2 is connected to the cathode IK of the thyristor I, the source 2S of the MOSFET 2 is connected to the gate IG of the Sl thyristor 1, and the Sl thyristor I and the MOSFET 2 are connected in cascode.

IA is the anode of Sl thyristor 1, 2G is MOSFE
This is the gate of T. Further, in FIG. 6, 3 is a diode connected between the gate IG of the Sl thyristor 1 and the source 28 of the MOSFET 2. Furthermore, in Figure 7, 4 is the same <
Sl thyristor l gate lG and MOSFET2 (7)
This is a Zener diode connected between 7 and 2S.

D1 Problems to be Solved by the Invention A configuration in which the Sl thyristor 1 is turned on and off only by turning on and off the MOSFET 2 (no special gate current is passed to turn the Sl thyristor on and off) as shown in FIG. In the cascode connection method, the Sl thyristor 2 is required to be a completely normally-on type Sl thyristor that exhibits forward characteristics similar to those of a diode when no reverse gate bias is applied.

When using a device that exhibits characteristics that are normally off or intermediate between normally on and off, such as blocking a certain amount of voltage when no gate bias is applied,
In a cascode connection as shown in FIG. 5, the on-characteristics deteriorate significantly or the device does not turn on at all, and a gate current is required to turn it on. However, a completely normally-on type Sl thyristor has a smaller anode voltage that can be blocked with the same gate reverse voltage than a normally-off type Sl thyristor.

Normally, normally on type Sl thyristor is 1000V.
It requires a gate voltage of 100V or more to block the anode voltage of . For this reason, the withstand voltage of the MOSFET must also be 100V or higher. Since the on-resistance of a MOSFET is proportional to the 2.5th power of the withstand voltage, increasing the withstand voltage of the MOSFET increases the steady-state loss during cascode connection. Therefore, in order to increase the withstand voltage of the cascode-connected device shown in Figure 5, it is necessary to increase the withstand voltage of the MOSFET, and for this reason, it is not practical from the standpoint of loss to configure devices with a voltage of 1000 V or more using the cascode-connected device shown in Figure 5. It was extremely difficult.

On the other hand, as shown in FIG.
A diode 3 connected in the forward direction between G and the source 28 of MOSFET 2, and a cascode connection in which a Zener diode 4 is inserted in the reverse direction as shown in Fig. 7 are also considered, but in these cases, the turn-on At times, the built-in voltage of the diode 3 or the Zener voltage of the Zener diode 4 is applied to the Sl thyristor l as an on-gate voltage, so it is close to normally off. Therefore, cascode connection can now be applied to Sl thyristors that can block large anode voltages with a small gate reverse bias. However, even with this configuration, there is a problem that the turn-on time is relatively long.

Another problem is the anode current/voltage waveform and MOS at turn-on in the case of cascode connection shown in Figure 7.
An example of the voltage waveform applied between the drain and source of the MOSFET is shown in Fig. 8. The voltage Vos applied between the drain and source of the MOSFET increases once at the early stage of turn-off, and then remains at a nearly constant value. It comes to show. This voltage jump at the initial stage of turn-off is determined by the inductance between the gate of the Sl thyristor and the source of the MOSFET and the dI/dt of the current flowing therebetween, and the faster the MOSFET is operated, the larger the value of the surge voltage becomes. To prevent the MOSFET from being destroyed by this surge voltage during cascode connection, the MOS
It is necessary to increase the withstand voltage of the FET. This results in a large loss in the device, similar to the case of the cascode connection shown in Figure 5, so it is practically difficult to configure a device of 100V or more using the method shown in Figures 6 and 7. Ta.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a low-loss composite semiconductor device that enables high-speed switching operation in a device in which an Sl thyristor and a MOSFET are connected by male cord. .

80 Means for Solving the Problems In order to achieve the above object, the present invention connects the cathode of an electrostatic induction thyristor to the drain of a MOSFET, uses the anode of the electrostatic induction thyristor as a first electrode, and The gate of the induction thyristor is connected to the source of the MOSFET and used as a second electrode to be taken out to the outside.
In a composite semiconductor device in which the gate of the MOSFET is used as a third electrode, a bias circuit having a capacitor is connected between the gate of the electrostatic induction thyristor and the source of the MOSFET.

MOSF generated at turn-off of a composite semiconductor device consisting of an F1 acting Sl thyristor and a MOSFET connected in cascode.
The surge voltage of the ET is absorbed by the capacitor, and a gate current is supplied from the capacitor to the gate of the Sl thyristor when turned on.

G. Examples Examples of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows a reactivation type semiconductor device according to the first embodiment of the present invention. In the three-terminal post-combination type semiconductor device according to the first embodiment, the anode IA of the Sl thyristor 1 is used as the first electrode 5A. , the cathode IK of the Sl thyristor 1 is connected to the drain 2D of the MOSFET 2, and the gate IG of the Sl thyristor 1 is connected to the source 2S of the MOSFET 2 to serve as a second electrode 5B taken out to the outside.
In the case where the gate 2G of the MOSFET 2 is the third electrode 5C, the gate IG of the Sl thyristor 1 and the MOSFET
A resistor 6 is connected between the source 28 of the SFET 2 as a biasing means, and a capacitor 7 is connected in parallel to the resistor 6 to form a bias circuit 8.

When a voltage is applied so that the first electrode 5A side has a positive potential and the second electrode 5B side has a negative potential, the gate IG
When no voltage is applied between the gate IG and FIK in the direction where the gate has a negative potential, it is in a conductive state (it is a normally-on type element, and it is in a conductive state when no signal is applied to the gate)
.

On the other hand, when a voltage is applied between the gate IG and the cathode IK in such a direction that the gate IG has a negative potential, part of the anode current passes through the gate region and is swept out of the gate electrode, and a depletion layer of high resistance with little charge is created in the channel region. (space charge layer) is formed and enters a blocking state.

That is, to turn on the S, I thyristor l, remove the reverse voltage applied to the gate lG, and a diode current will flow through the channel, turning it on. Furthermore, in order to turn off (block) the anode current in the conductive state, a reverse voltage is applied to the gate IG to block the channel with a high-resistance depletion layer.

MO8R-ET2 and SI thyristor 1 are turned on and off at a predetermined period, and SI thyristor 1 and M are connected from the first electrode 5A to
The main current flows through OSFET2. At this time, the capacitor 7 of the bias circuit 8 is charged. When the Sl thyristor 1 is turned off, the charge in the capacitor 7 is discharged through the resistor 6, the gate IG becomes a positive potential, and the Sl thyristor 1 is turned on again. Voltage V between the drain 2D and source 28 of MOSFET 2 when the Sl thyristor 1 is turned off. S suddenly rises and its peak voltage VD
SP is generated, but this peak voltage vosp is absorbed by the capacitor 7.

FIG. 2 shows a composite semiconductor device according to a second embodiment of the present invention, in which the gate IG of the SI thyristor I and the MOSFET
A diode 3 is connected in series in the forward direction and a capacitor 7 is connected between the source 28 of the ET2. S
When the thyristor 1 is turned off in the evening, the charge in the capacitor 7 is discharged through the diode 3, and the built-in voltage of the diode 3 is applied as a gate signal to the gate IG of the SI thyristor 1, so that the thyristor 1 is turned on again. The peak voltage Vo between the drain 2D and source 25 that occurs when the SI thyristor l is turned off
sp is absorbed by capacitor 7.

FIG. 3 shows a composite semiconductor device according to a third embodiment of the present invention. In this third embodiment, a Zener diode 4 is connected in series in the opposite direction between the gate IG of the Sl silice 1 and the source 28 of the MOSFET 2. A bias circuit 8 is formed by connecting the capacitor 7 and the capacitor 7. S
When the l thyristor 1 is turned off, the charge stored in the capacitor is discharged through the zener diode 4, and the zener voltage turns on the sl thyristor 1 again.

FIG. 4 shows a capacitor 7 based on the embodiment shown in FIG.
The magnitude of the surge voltage when the capacitance of
Voltage V between the drain 2D and source 28 of FET2. This is a measurement example shown with the ratio of .

As is clear from FIG. 4, it can be seen that as the capacitor capacity increases, the value of the surge voltage Vosp decreases.

In this example, when the capacitor capacity is 0.005 μF, the surge voltage can be reduced by about 20%. When the capacitor capacity becomes 0.04μF, the surge voltage VDSP
and the voltage Vo applied between the drain and source in the off state
The ratio of s becomes 1, and no surge voltage is observed.

On the other hand, increasing the capacitor capacity increases the loss of the capacitor itself. Generally, the capacitance of a capacitor, ■ is the voltage applied to the capacitor, and f is the operating frequency. ) If the conventional method of increasing the withstand voltage of the MOSFET to above the surge voltage without using a capacitor is used, the steady loss of the MOSFET increases as described above. The increment of this loss is I-XΔV7. Although expressed as x duty, the present invention can reduce the steady loss by this amount. (Here I,
is the on-state current, ΔV? is the increment of the ON voltage of the MOSFET. Furthermore, according to the present invention, since a gate current is supplied from the capacitor at turn-on, turn-on is improved compared to conventional methods, and turn-on loss is reduced by 10% or more. In the end, the increase in loss due to the inclusion of the capacitor is offset by the reduction in steady loss, or even more so.

Note that even if a non-inductive resistor for vibration prevention is connected in series with the capacitor 7 shown in FIGS. 1 to 3, the same effects as in each of the above embodiments can be obtained.

By using the cascode connection shown in Figures 2 and 3 and using the optimal value of 0.01μF to 0.04μF for the capacitor capacitance, it is possible to suppress the generation of surge voltage and the loss of the capacitor itself. It becomes possible to realize cascode connection of Sl silis with low loss.

H1 Effects of the Invention The present invention is as described above, and by connecting a bias circuit including a capacitor between the gate of the Sl thyristor and the gate of the MOSFET, it is possible to suppress the surge voltage that occurs when turning off the cascode connection, and to reduce the steady-state loss. It is possible to realize a composite semiconductor device with a small size.

Furthermore, according to the present invention, since the charge charged in the capacitor flows to the gate as a gate current when turned on, cascode connection is also possible for normally-off type Sl thyristors, which are difficult to operate with conventional cascode connection. . Generally, a normally-off type Sl thyristor has the ability to block a large anode-cathode voltage with a smaller gate voltage than a normally-on type Sl thyristor. Therefore, by applying the cascode-connected, normally-off type Sl thyristor of the present invention, a cascode-connected Sr thyristor with high withstand voltage can be easily constructed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a composite semiconductor device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a composite semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a composite semiconductor device according to a second embodiment of the present invention. A circuit diagram of a composite semiconductor device according to an example, FIG. 4 is a characteristic diagram of the composite semiconductor device of FIG. 3, FIG. 5 is a circuit diagram of a conventional composite semiconductor device, and FIG. 6 is a diagram of another conventional composite semiconductor device. circuit diagram of semiconductor device,
FIG. 7 is a circuit diagram of yet another conventional composite semiconductor device,
FIG. 8 is a characteristic diagram of the composite semiconductor device of FIG. 7. ■... Electrostatic induction thyristor, IA... Anode, 1
K...Cathode, IG-, gate, 2-MOSFET
. 2D... Drape 2S, -, Source, 2G...
・Gate, 3... Diode, 4... Zener diode, 5A... First electrode, 5 B 1 second electrode, 5c... Third electrode, 6... Resistor, 7...・Capacitor, 8...bias circuit. Figure 1 Example Figure 2 Figure 3 Example Example Figure 4 Condenser capacitance (μF)

Claims (4)

[Claims] (1) The cathode of the electrostatic induction thyristor is connected to the drain of the MOSFET, the anode of the electrostatic induction thyristor is used as the first electrode, and the gate of the electrostatic induction thyristor is connected to the source of the MOSFET to take out the first electrode to the outside. 2 electrode, and the gate of the MOSFET is the third electrode.
What is claimed is: 1. A composite semiconductor device in which a bias circuit having a capacitor is connected between the gate of the electrostatic induction thyristor and the source of the MOSFET. (2) The composite semiconductor device according to claim 1, wherein the bias circuit includes a resistor connected in parallel to the capacitor. (3) The composite semiconductor device according to claim 1, wherein the bias circuit includes a diode connected in parallel to the capacitor. (4) The composite semiconductor device according to claim 1, wherein the bias circuit includes a Zener diode connected in parallel to the capacitor.