JPH03183210A - High dielectric voltage semiconductor switch - Google Patents

High dielectric voltage semiconductor switch

Info

Publication number
JPH03183210A
JPH03183210A JP33970490A JP33970490A JPH03183210A JP H03183210 A JPH03183210 A JP H03183210A JP 33970490 A JP33970490 A JP 33970490A JP 33970490 A JP33970490 A JP 33970490A JP H03183210 A JPH03183210 A JP H03183210A
Authority
JP
Japan
Prior art keywords
thyristor
resistor
fet
mos
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33970490A
Other languages
Japanese (ja)
Other versions
JPH0611105B2 (en
Inventor
Yoshitaka Sugawara
良孝 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP33970490A priority Critical patent/JPH0611105B2/en
Publication of JPH03183210A publication Critical patent/JPH03183210A/en
Publication of JPH0611105B2 publication Critical patent/JPH0611105B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To realize the reduction of a chip occupying area and the reduction of power loss by constituting the switch so that a p-type and an n-type MOS transistors(TRs) provided with main circuits connected in parallel are provided and a common drive signal is inputted to the gates of these p-type and n-type MOS TRs. CONSTITUTION:When an ON signal from a drive circuit connected to a gate terminal G becomes large, and the inter-source-drain current of an MOS-FET increases, and voltage between both ends of a resistor 4 becomes over about 0.6V, a thyristor 1 is turned on. On the other hand, when the anode potential of the thyristor is lower than ON signal potential, an n-channel MOS-FET 5 is turned on, and the current having linear voltage dependency flows through the resistor 3. When the voltage of both ends of the resistor 4 becomes over about 0.6V by these currents, since the thyristor is turned on, ON-driving can be executed surely. Thus, an ON-resistor which has less number of fundamental constituent elements, and in addition, is small in a large current area because a main output part is the thyristor can be realized within the area smaller than the MOS-FET.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高耐圧半導体スイッチに係り、特に入出力間
が電気的に絶縁され、且つ出力部がオン時に低電流域で
は線形の電圧依存性をもつ高耐圧半導体スイッチに関す
る。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a high-voltage semiconductor switch, and in particular, the input and output are electrically isolated, and when the output section is on, linear voltage dependence is achieved in the low current range. This article relates to high-voltage semiconductor switches with high voltage characteristics.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置は電磁リレーの代替品として
通信分野等で強く要望されており1例えばMOS−FE
Tから構成される容量結合型の集積回路が知られている
。(ISSCCDigest of Technica
lPapers、P、238−239.Feb、198
1又は米国特許4,170,740号参照)。
Conventionally, this type of semiconductor device has been strongly requested in the communication field as a substitute for electromagnetic relays.
A capacitively coupled integrated circuit composed of T is known. (ISSCCDigest of Technica
lPapers, P, 238-239. Feb, 198
1 or U.S. Pat. No. 4,170,740).

この回路構成は第3図に示すようにむっている。This circuit configuration is as shown in FIG.

この回路は入出力間が容量で結合されているので直流的
に絶縁されており、この結果、入力開動回路部に対し出
力部が電位的にフローテング状態にあっても確実に出力
部の駆動が可能となる。また出力部がMOS−FETで
構成されているのでオン駆動された場合に出力部の通電
電流は線形の電圧依存性を示すようになる。この結果出
力部がバイポーラ素子で構成された半導体装置に比べ出
力側電源の省電力化を計ることができる。すなわちバイ
ポーラ素子の通電電流は非線形の電圧依存性を示し、低
電流域では非線形性が特に著しいので線形に近い電圧依
存性を得るためには一定の直流バイアス電流を流さなけ
ればならないが、MOS−FETの場合この電流が不要
となるためである。
In this circuit, the input and output are coupled by capacitance, so they are isolated in terms of direct current.As a result, even if the output section is in a potential floating state with respect to the input open circuit section, the output section is reliably driven. becomes possible. Further, since the output section is constituted by a MOS-FET, when the output section is turned on, the current flowing through the output section exhibits linear voltage dependence. As a result, it is possible to save power on the output side compared to a semiconductor device in which the output section is composed of bipolar elements. In other words, the current flowing through a bipolar element exhibits nonlinear voltage dependence, and the nonlinearity is particularly significant in the low current range, so a constant DC bias current must be passed in order to obtain a nearly linear voltage dependence. This is because this current is not necessary in the case of a FET.

上記回路はこのような特徴があるため本装置は1チツプ
にIC化が可能な電磁リレーの代替装置として広い応用
が可能なものである。
Because the circuit described above has such characteristics, the present device can be widely applied as a substitute device for electromagnetic relays that can be integrated into a single chip.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、 (1)  出力部がMOS−FETなのでオン抵抗が大
きく、大電流通電時の電力損失が大きい。
However, (1) since the output section is a MOS-FET, the on-resistance is large and the power loss when large current is applied is large.

(2)  回路構成素子数が多いためrc化した場合の
チップの占有面積が大きい。特に入出方間結合用の容量
は15pF程度であり大きな面積を要する。また出力部
のオン抵抗を小さくするにはFETのチャネル幅とチャ
ネル長さを大きくする必要があり、チップ面積が大きく
なってしまう。
(2) Since the number of circuit components is large, the chip occupies a large area when converted to RC. In particular, the input-output coupling capacitance is about 15 pF, which requires a large area. Furthermore, in order to reduce the on-resistance of the output section, it is necessary to increase the channel width and channel length of the FET, which increases the chip area.

(3)容量結合なので交流信号でないと駆動できない。(3) Since it is capacitively coupled, it cannot be driven unless it is an AC signal.

という欠点を有するものであった。It had the following drawbacks.

本発明の目的は、入出力間が電気値に絶縁され、出力部
がフローテング状態でも駆動が可能であり、且つ出力部
がオン時の通電電流が低電流域では線形の電圧依存性を
示すが、大電流域では低いオン抵抗となるチップ占有面
積の小さい高耐圧半導体スイッチを提供するにある。
The purpose of the present invention is to insulate the input and output to an electrical value, to be able to drive even when the output section is in a floating state, and to make the current flowing when the output section is on exhibit linear voltage dependence in a low current range. However, it is an object of the present invention to provide a high voltage semiconductor switch that has a low on-resistance in a large current range and occupies a small chip area.

〔課題を解決するための手段〕[Means to solve the problem]

このような目的を達成するため本発明は、絶縁ゲート形
電界効果素子例えばMOS−FET等のゲート端子と主
端子がゲート酸化膜で電気的に絶縁されていること、バ
イポーラ素子がMOS−FETに比べ小面積でオン抵抗
を小さくする上で有利であること、nチャネルMOS−
FETとnチャネルMOS−FETでは駆動する際主端
子の電位に対するゲート端子の電位が逆極性であること
に着目し、p’nチャネルMO3−FETとバイポーラ
素子さらに抵抗を組合わせるようにしたものである。
In order to achieve such an object, the present invention provides that the gate terminal and main terminal of an insulated gate field effect element such as a MOS-FET are electrically insulated by a gate oxide film, and that a bipolar element is replaced with a MOS-FET. N-channel MOS-
Focusing on the fact that when driving an FET and an n-channel MOS-FET, the potential of the gate terminal is opposite to the potential of the main terminal, we combined a p'n-channel MO3-FET, a bipolar element, and a resistor. be.

すなわち、順電圧印加時に主として順電圧を阻止する接
合と逆電圧印加時に主として逆電圧を阻止する接合とを
それぞれ少なくとも1ヶ以上有し、それらの接合が直列
に主端子間に接続されてなるバイポーラ素子と、前記逆
電圧を阻止する接合の1つに並列接続された抵抗と、こ
の抵抗が並列接続された接合を除く前記逆電圧を阻止す
る接合と前記順電圧を阻止する接合との全体に並列接続
された主回路を有するp型MOSトランジスタおよびn
型MOSトランジスタとを含んでなり、このp型MOS
トランジスタとn型MOSトランジスタのゲートに共通
の駆動信号を入力する構成の高耐圧半導体スイッチとし
たのである。
In other words, it has at least one junction that primarily blocks forward voltage when a forward voltage is applied and at least one junction that mainly blocks reverse voltage when a reverse voltage is applied, and these junctions are connected in series between the main terminals. an element, a resistor connected in parallel to one of the junctions for blocking the reverse voltage, and the entirety of the junction for blocking the reverse voltage and the junction for blocking the forward voltage, excluding the junction to which this resistor is connected in parallel; A p-type MOS transistor with a main circuit connected in parallel and an n
type MOS transistor, and this p-type MOS transistor
This is a high-voltage semiconductor switch configured to input a common drive signal to the gates of the transistor and the n-type MOS transistor.

〔作用〕 このようにすれば、バイポーラ素子とゲート端子を電気
的に絶縁できるとともにバイポーラ素子の電位がゲート
電位より低い時はnチャネルMOS−FETにより駆動
でき、ゲート電位より高い時はnチャネルMOS−FE
Tにより駆動できるので、バイポーラの電位がフローテ
ング状態にあリゲート電位が固定されている場合に確実
に駆動せしめることができる。また、バイポーラ素子が
オンするまではMOS−FETと抵抗を介して電流が流
れるので通電電流の電圧依存性を線形にできるとともに
、抵抗の両端の電位がバイポーラ素子の順バイアス接合
が動作する約0.6V以上になるとバイポーラ素子がオ
ンするので小面積にもかかわらず大電流域でのオン抵抗
を小さくできる。
[Function] In this way, the bipolar element and the gate terminal can be electrically isolated, and when the potential of the bipolar element is lower than the gate potential, it can be driven by the n-channel MOS-FET, and when it is higher than the gate potential, it can be driven by the n-channel MOS-FET. -FE
Since it can be driven by T, it can be driven reliably when the bipolar potential is in a floating state and the alligator potential is fixed. In addition, since current flows through the MOS-FET and the resistor until the bipolar element is turned on, the voltage dependence of the conducting current can be made linear, and the potential across the resistor is approximately 0, at which the forward bias junction of the bipolar element operates. Since the bipolar element turns on when the voltage exceeds .6V, the on-resistance in a large current range can be reduced despite the small area.

この他、容量結合でなくMOS−FETのゲート酸化膜
で結合しているので直流ゲートバイアス信号でも駆動で
きるものである。
In addition, since the coupling is not by capacitive coupling but by the gate oxide film of the MOS-FET, it can also be driven by a DC gate bias signal.

〔実施例〕〔Example〕

以下、本発明を図示実施例に基づいて説明する。 Hereinafter, the present invention will be explained based on illustrated embodiments.

第1図は本発明の一実施例の高耐圧半導体スイッチの概
念構成図である。図示のように、主回路端子A、に間に
接続された主スイッチであるサイリスタ1と、このサイ
リスタ1のPEnBPCトランジスタ部分に、p’n両
チャネルMOS−FET3.5を並列に接続し、PB 
ng接合に抵抗4を並列に接続した構成としたものであ
る。また、p・n両チャネルMO8−FET3,5のゲ
ートには、信診端子Gから共通の駆動信号が入力される
FIG. 1 is a conceptual diagram of a high voltage semiconductor switch according to an embodiment of the present invention. As shown in the figure, a p'n double channel MOS-FET 3.5 is connected in parallel to a thyristor 1, which is a main switch connected between the main circuit terminal A, and a PEnBPC transistor part of this thyristor 1,
This configuration has a resistor 4 connected in parallel to the NG junction. Further, a common drive signal is inputted from the confidence terminal G to the gates of both the p- and n-channel MO8-FETs 3 and 5.

このように構成される実施例の動作を次に説明する。本
装置はゲート端子Gに接続した開動回路からオン信号を
供給することにより駆動される。
The operation of the embodiment configured as described above will be explained next. This device is driven by supplying an on signal from an opening circuit connected to the gate terminal G.

オン信号電位よりもサイリスタのカソード電位が高い場
合は、pチャネルMO8−FET3がオンするので抵抗
4を介してA−に間に電流が流れる。
When the cathode potential of the thyristor is higher than the on-signal potential, the p-channel MO8-FET3 is turned on, so that a current flows between A- and A- via the resistor 4.

pチャネルMO8−FET3がオンした場合ソース・ド
レイン間通電電流が比較的低電流領域ではソース・ドレ
イン間の電圧に線形的に依存するので、A−に間の通電
電流もA−に間電圧に線形的に依存する。この場合のA
−に間抵抗はMOS−FETのチャネル抵抗と抵抗4と
を加算した値にほぼ等しい。オン信号が大きくなりMO
S−FETのソース・ドレイン間電流が増大し抵抗4の
両端の電圧がサイリスタlのbuildup電圧(約0
.6V)以上になるとサイリスタ1がオンする。例えば
抵抗4を100Ωとした場合約6mAの電流がMOS−
FET3から供給されるとサイリスタはオンする。一般
にサイリスタのオン抵抗は同程度の素子面積のMOS−
FETに比べて著しく小さいので、大電流域ではもっば
ら電流はサイリスタ側を流れA−に間のオン抵抗は小さ
くなる。例えば4mA通電時のオン抵抗は少なくとも抵
抗4以上すなわち100Ω以上と大きいが、6mA以上
では200mA程度の範囲まで容易に10Ω以下のオン
抵抗にできる。
When the p-channel MO8-FET3 is turned on, the current flowing between the source and drain depends linearly on the voltage between the source and drain in a relatively low current region, so the current flowing between A- and A- also depends on the voltage between A- and linearly dependent. A in this case
The resistance between - and the resistance is approximately equal to the sum of the channel resistance of the MOS-FET and the resistance 4. The on signal increases and MO
The current between the source and drain of the S-FET increases, and the voltage across the resistor 4 increases to the build-up voltage of the thyristor 1 (approximately 0
.. 6V) or more, thyristor 1 turns on. For example, if resistor 4 is 100Ω, a current of about 6mA will flow through the MOS-
When supplied from FET3, the thyristor turns on. Generally, the on-resistance of a thyristor is equal to that of a MOS-
Since it is significantly smaller than a FET, in a large current range, most of the current flows through the thyristor side, and the on-resistance between A- and A- becomes small. For example, the on-resistance when energizing at 4 mA is as large as at least 4 or more, that is, 100 Ω or more, but at 6 mA or more, the on-resistance can easily be reduced to 10 Ω or less up to about 200 mA.

一方、オン信号電位よりもサイリスタのアノード電位が
低い場合はnチャネルMOS−FET5がオンし抵抗3
を介して線形の電圧依存性をもつtIl流が流れる。オ
ン信号電位がサイリスタのアノード電位より低く、カソ
ード電位より高い中間状態ではPan両MO5−FET
がオンされる場合があるが、やはり線形の電圧依存性を
もつ電流が流れる。いずれにしてもこれらの電流により
抵抗4の電圧が0.6V以上となるとサイリスタがオン
するのでサイリスタの電位がフローテング状態にあって
も確実にオン駆動できる。
On the other hand, when the anode potential of the thyristor is lower than the on signal potential, the n-channel MOS-FET 5 is turned on and the resistor 3
A tIl current with linear voltage dependence flows through. In an intermediate state where the on signal potential is lower than the anode potential of the thyristor and higher than the cathode potential, both Pan MO5-FET
may be turned on, but a current with linear voltage dependence still flows. In any case, when the voltage of the resistor 4 becomes 0.6 V or more due to these currents, the thyristor is turned on, so that even if the potential of the thyristor is in a floating state, it can be turned on reliably.

サイリスタとG端子間はMOS−FET3及び5のゲー
ト酸化膜が絶縁されているのでゲート絶縁破壊電圧に相
当する高い且つ良好な絶縁状態を実現できる。−例をあ
げるとMOS−FETのしきい値電圧を約3Vにした場
合、そのゲート絶縁破壊電圧すなわちサイリスタとG端
子間の絶縁耐圧を容易に500V程度にでき、且つサイ
リスタとG端子間のリーク電流も容易に10−”A以下
にできる。
Since the gate oxide films of MOS-FETs 3 and 5 are insulated between the thyristor and the G terminal, a high and good insulation state corresponding to the gate dielectric breakdown voltage can be achieved. -For example, if the threshold voltage of a MOS-FET is set to about 3V, its gate dielectric breakdown voltage, that is, the dielectric strength voltage between the thyristor and the G terminal, can easily be made to about 500V, and the leakage between the thyristor and the G terminal can be easily increased to about 500V. The current can also be easily reduced to 10-''A or less.

本実施例の場合バイポーラ素子がサイリスタなので一度
オンするとオン信号がなくなってもオン状態を維持する
自己保持機能を有する。
In this embodiment, since the bipolar element is a thyristor, it has a self-holding function to maintain the on state even if the on signal disappears once it is turned on.

また本実施例は基本構成素子が従来例に比べ少なく、且
つ主出力部がサイリスタなので大電流域での小さいオン
抵抗をMOS−FETよりも小さい面積で実現できる上
に、従来例のような大面積を要する容量が不要なのでI
C化した場合の開示例では400V、100mA級の半
導体装置を実現するのにLonm”以上のチップ占有面
積を必要としたが本実施例の場合2m2以下のチップ占
有面積で実現できる。更に容量結合でな(MOS−FE
Tのゲート酸化膜で結合しているので直流バイアス信号
を駆動できる。
In addition, this embodiment has fewer basic components than the conventional example, and the main output section is a thyristor, so it is possible to achieve a small on-resistance in a large current range with a smaller area than a MOS-FET, and it is I do not need a capacity that requires area.
In the disclosed example in the case of C conversion, a chip occupying area of Lonm'' or more was required to realize a 400 V, 100 mA class semiconductor device, but in this example, it can be realized with a chip occupying area of 2 m2 or less.Furthermore, capacitive coupling Dena (MOS-FE
Since they are connected through the T gate oxide film, a DC bias signal can be driven.

第2図に、本発明の他の実施例の高耐圧半導体スイッチ
の概念構成図を示す。本実施例は、バイポーラ素子とし
てnpnトランジスタ2を用い、コレクタ接合にp”n
両チャネルMO8−FET3.5を並列に接続し、エミ
ッタ接合に抵抗4を接続している。本実施例の基本動作
機構は前記実施例と同様なので説明は省略する。このよ
うにした場合バイポーラ素子がトランジスタなのでG端
子のオン信号の有無によりA−に間をオン・オフできる
という特徴を有する。
FIG. 2 shows a conceptual configuration diagram of a high voltage semiconductor switch according to another embodiment of the present invention. In this embodiment, an npn transistor 2 is used as a bipolar element, and the collector junction is p”n
Both channel MO8-FETs 3.5 are connected in parallel, and a resistor 4 is connected to the emitter junction. The basic operating mechanism of this embodiment is the same as that of the previous embodiment, so its explanation will be omitted. In this case, since the bipolar element is a transistor, it has the characteristic that it can be turned on and off between A- and A- depending on the presence or absence of an on signal at the G terminal.

また、大電流域でのオン抵抗はサイリスタより大きくな
るが、MOS−FETに比べるとより小さなチップ占有
面積で同等以下の低いオン抵抗を実現できる。
Furthermore, although the on-resistance in a large current range is larger than that of a thyristor, it is possible to achieve an on-resistance as low as that of a MOS-FET with a smaller chip area than a MOS-FET.

以上説明したように各実施例に基づき本発明の詳細とそ
の効果を説明したが、本発明はこれらの実施例に限定さ
れるものではなく、実施例と逆並列に接続して双方向性
スイッチング素子とすること、第↓図実施例においてp
”n両チャネルMO3−FETをnpnトランジスタ部
と並列に接続し且つ抵抗をPp  nn接合と並列に接
続すること等の各種の変形・応用が可能なことは当業者
には自明である。
As explained above, the details of the present invention and its effects have been explained based on each embodiment, but the present invention is not limited to these embodiments, and bidirectional switching can be achieved by connecting the embodiments in antiparallel. In the example shown in Fig.
It will be obvious to those skilled in the art that various modifications and applications are possible, such as connecting an n-channel MO3-FET in parallel with the npn transistor section and connecting a resistor in parallel with the Pp nn junction.

〔発明の効果〕〔Effect of the invention〕

以上説明したことから明らかなように、本発明による高
耐圧半導体スイッチによれば、バイポーラ素子がゲート
を連結したp”n両チャネルMO3−FETでトリガさ
れるので入出力間が電気的に絶縁でき且つ出力部がフロ
ーテング状態でも確実に駆動できる効果があり、さらに
低電流域ではMOS−FETと抵抗を介して通電できる
ので線形の電圧依存性を実現でき、大電流域ではバイポ
ーラ素子を介して通電できるので小さなチップ占有面積
で低いオン抵抗を達成でき電力損失を小さくできるとい
う効果を有するようになる。
As is clear from the above explanation, according to the high voltage semiconductor switch according to the present invention, since the bipolar element is triggered by the p"n double channel MO3-FET whose gates are connected, the input and output can be electrically isolated. In addition, it has the effect of being able to drive reliably even when the output section is in a floating state.Furthermore, in the low current range, current can be passed through a MOS-FET and a resistor, so linear voltage dependence can be achieved, and in the large current range, it can be driven via a bipolar element. Since current can be passed, low on-resistance can be achieved with a small chip area, and power loss can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による高耐圧半導体スイッチの一実施例
を示す構成図、第2図は本発明による高耐圧半導体スイ
ッチの他の実施例を示す構成図、第3図は従来の高耐圧
半導体スイッチの回路図である。 1・・・サイリスタ、2・・・バイポーラトランジスタ
、3・・・pチャネルMO5−FET、4・・・抵抗、
5− nチャネルMOS −F E T。
FIG. 1 is a block diagram showing one embodiment of a high voltage semiconductor switch according to the present invention, FIG. 2 is a block diagram showing another embodiment of a high voltage semiconductor switch according to the present invention, and FIG. 3 is a block diagram showing a conventional high voltage semiconductor switch. FIG. 3 is a circuit diagram of a switch. DESCRIPTION OF SYMBOLS 1... Thyristor, 2... Bipolar transistor, 3... P channel MO5-FET, 4... Resistor,
5- n-channel MOS-FET.

Claims (1)

【特許請求の範囲】 1、順電圧印加時に主として順電圧を阻止する接合と逆
電圧印加時に主として逆電圧を阻止する接合とをそれぞ
れ少なくとも1ケ以上有し、それらの接合が直列に主端
子間に接続されてなるバイポーラ素子と、 前記逆電圧を阻止する接合の1つに並列接続された抵抗
と、 この抵抗が並列接続された接合を除く前記逆電圧を阻止
する接合と前記順電圧を阻止する接合との全体に並列接
続された主回路を有するp型MOSトランジスタおよび
n型MOSトランジスタとを含んでなり、 このp型MOSトランジスタとn型MOSトランジスタ
のゲートに共通の駆動信号を入力する構成の高耐圧半導
体スイッチ。 2、特許請求の範囲第1項において、 前記バイポーラ素子が、サイリスタであり、前記抵抗が
そのサイリスタのpベースとnエミッタ又はnベースと
pエミッタとの間に並列接続され、 前記p型MOSトランジスタおよびn型MOSトランジ
スタがそのサイリスタの前記抵抗が接続されたベースと
このベースと同一導電型のエミッタとの間に並列接続さ
れてなることを特徴とする高耐圧半導体スイッチ。 3、特許請求の範囲第1項において、 前記バイポーラ素子が、トランジスタであり、前記抵抗
がそのトランジスタのベースと一方の主電極との間に並
列接続され、 前記p型MOSトランジスタおよびn型MOSトランジ
スタがそのトランジスタのベースと他方の主電極との間
に並列接続されてなることを特徴とする高耐圧半導体ス
イッチ。
[Claims] 1. There is at least one junction that mainly blocks forward voltage when forward voltage is applied and at least one junction that mainly blocks reverse voltage when reverse voltage is applied, and these junctions are connected in series between the main terminals. a bipolar element connected to a bipolar element, a resistor connected in parallel to one of the junctions for blocking the reverse voltage, and a junction for blocking the reverse voltage and the junction for blocking the forward voltage other than the junction to which this resistor is connected in parallel; A configuration including a p-type MOS transistor and an n-type MOS transistor having a main circuit connected in parallel to the junction, and a common drive signal is input to the gates of the p-type MOS transistor and the n-type MOS transistor. high voltage semiconductor switch. 2. In claim 1, the bipolar element is a thyristor, the resistor is connected in parallel between the p-base and n-emitter of the thyristor, or the n-base and p-emitter of the thyristor, and the p-type MOS transistor and an n-type MOS transistor connected in parallel between the base of the thyristor to which the resistor is connected and the emitter of the same conductivity type as the base. 3. In claim 1, the bipolar element is a transistor, the resistor is connected in parallel between the base of the transistor and one main electrode, and the p-type MOS transistor and the n-type MOS transistor is connected in parallel between the base of the transistor and the other main electrode.
JP33970490A 1990-11-30 1990-11-30 High voltage semiconductor switch Expired - Lifetime JPH0611105B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33970490A JPH0611105B2 (en) 1990-11-30 1990-11-30 High voltage semiconductor switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33970490A JPH0611105B2 (en) 1990-11-30 1990-11-30 High voltage semiconductor switch

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP19325584A Division JPS6171718A (en) 1984-09-14 1984-09-14 High dielectric strength semiconductor switch

Publications (2)

Publication Number Publication Date
JPH03183210A true JPH03183210A (en) 1991-08-09
JPH0611105B2 JPH0611105B2 (en) 1994-02-09

Family

ID=18330018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33970490A Expired - Lifetime JPH0611105B2 (en) 1990-11-30 1990-11-30 High voltage semiconductor switch

Country Status (1)

Country Link
JP (1) JPH0611105B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012124806A (en) * 2010-12-10 2012-06-28 Panasonic Corp Semiconductor relay
JP2012124807A (en) * 2010-12-10 2012-06-28 Panasonic Corp Semiconductor relay

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012124806A (en) * 2010-12-10 2012-06-28 Panasonic Corp Semiconductor relay
JP2012124807A (en) * 2010-12-10 2012-06-28 Panasonic Corp Semiconductor relay

Also Published As

Publication number Publication date
JPH0611105B2 (en) 1994-02-09

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